Datasheet ADCMP603 Datasheet (ANALOG DEVICES)

Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,

V

V

V

www.BDTIC.com/ADI

Single-Supply TTL/CMOS Comparator

ADCMP603

FEATURES FUNCTIONAL BLOCK DIAGRAM

Fully specified rail to rail at V = 2.5 V to 5.5 V
Input common-mode voltage from −0.2 V to V + 0.2 V

CC

CC

Low glitch CMOS-/TTL-compatible output stage
Complementary outputs

3.5 ns propagation delay
12 mW at 3.3 V
Shutdown pin
Single-pin control for programmable hysteresis and latch
Power supply rejection > 50 dB

−40°C to +125°C operation

APPLICATIONS

High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)

NONINVERTI NG

P

INVERTING

V

N

INPUT

CCI

INPUT

ADCMP603

Figure 1.

CCO

TTL

LE/HYS INPUT

INPUT

S

DN

Q OUTPUT

Q OUTPUT

05915-001

GENERAL DESCRIPTION

The ADCMP603 is a very fast comparator fabricated on
XFCB2, a
comparator is exceptionally versatile and easy to use. Features
include an input range from V
complementary TTL-/CMOS-compatible output drivers, latch
inputs with adjustable hysteresis and a shutdown input.

The device offers 3.5 ns propagation delay with 10 mV

verdrive on 4 mA typical supply current.

o

A flexible power supply scheme allows the device to operate
wi
input signal range up to a +5.5 V positive supply with a −0.5 V
to +5.8 V input signal range. Split input/output supplies with no
sequencing restrictions support a wide input signal range while
still allowing independent output swing control and power
savings.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

n Analog Devices, Inc. proprietary process. This

− 0.5 V to V

EE CC

+ 0.2 V, low noise

th a single +2.5 V positive supply and a −0.5 V to +2.8 V

The device passes 4.5 kV HBM ESD testing and the absolute
maximum ratings include current limits for all pins.

The complementary TTL-/CMOS-compatible output stage is
designed to drive up to 5 pF with full timing specs and to
degrade in a graceful and linear fashion as additional
capacitance is added. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded.
Latch and programmable hysteresis features are also provided
with a unique single-pin control option.

The ADCMP603 is available in a 12-lead LFCSP package.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADCMP603

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Timing Information ......................................................................... 5

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

REVISION HISTORY

10/06—Revision 0: Initial Version

Application Information................................................................ 10

Power/Ground Layout and Bypassing..................................... 10

TTL-/CMOS-Compatible Output Stage ................................. 10

Using/Disabling the Latch Feature........................................... 10

Optimizing Performance........................................................... 11

Comparator Propagation Delay Dispersion ........................... 11

Comparator Hysteresis .............................................................. 11

Crossover Bias Point .................................................................. 12

Minimum Input Slew Rate Requirement................................ 12

Typical Application Circuits ......................................................... 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. 0 | Page 2 of 16

ADCMP603

www.BDTIC.com/ADI

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

V

= V

CCI

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

DC INPUT CHARACTERISTICS

Voltage Range VP, V
Common-Mode Range VCC = 2.5 V to 5.5 V −0.2 VCC + 0.2 V
Differential Voltage VCC = 2.5 V to 5.5 V VCC + 0.8 V
Offset Voltage V
Bias Current IP, I
Offset Current −2.0 2.0 µA
Capacitance CP, C
Resistance, Differential Mode −0.5 V to VCC + 0.2 V 200 700 kΩ
Resistance, Common Mode −0.2 V to VCC + 0.2 V 100 350 kΩ
Active Gain A
Common-Mode Rejection Ratio CMRR

Hysteresis R

LATCH ENABLE PIN CHARACTERISTICS

V
V
I

IH

I

OL

HYSTERESIS MODE AND TIMING

Hysteresis Mode Bias Voltage Current sink −1 A 1.145 1.25 1.35 V
Resistor Value Hysteresis = 120 mV 65 80 95 kΩ
Hysteresis Current Hysteresis = 120 mV −18 −14 −10 µA
Latch Setup Time t
Latch Hold Time t
Latch-to-Output Delay t
Latch Minimum Pulse Width t

SHUTDOWN PIN CHARACTERISTICS

V
V
I

IH

I

OL

Sleep Time t
Wake-Up Time t

DC OUTPUT CHARACTERISTICS V

Output Voltage High Level V
Output Voltage High Level −40°C V
Output Voltage Low Level V
Output Voltage Low Level −40°C V

= 2.5 V, TA = 25°C, unless otherwise noted.

CCO

IH

IL

IH

IL

N

OS

N

N

V

Hysteresis is shut off 2.0 V

VCC = 2.5 V to 5.5 V −0.5 VCC + 0.2 V

−5.0 ±2 +5.0 mV

−5.0 ±2 +5.0 µA

1.0 pF

85 dB
V

= 2.5 V, V

CCI

= −0.2 V to +2.7 V

V

CM

V

= 5.5 V, V

CCI

V

= −0.2 V to +5.7 V

CM

= ∞ 0.1 mV

HYS

= 2.5 V,

CCO

= 5.5 V,

CCO

50 dB

50 dB

CC

V
Latch mode guaranteed −0.2 +0.4 +0.8 V
V
V

S

H

, t

PLOH

PLOL

PL

Comparator is operating 2.0 V

= V

IH

CC

= 0.4 V −0.1 mA

IL

−6 +6 µA

VOD = 50 mV −2.0 ns
VOD = 50 mV 2.0 ns
VOD = 50 mV 30 ns
VOD = 50 mV 23 ns

CCO

V
Shutdown guaranteed −0.2 +0.4 +0.6 V
V
V

SD

H

OH

OH

OL

OL

= VCC −6 +6 µA

IH

= 0 V −80 µA

IL

I

< 0.5 mA 20 ns

OUT

VOD = 100 mV, output valid 50 ns

= 2.5 V to 5.5 V

CCO

IOH = 8 mA V
IOH = 6 mA V
IOL = 8 mA, V
IOL = 6 mA, V

= 2.5 V VCC − 0.4 V

CCO

= 2.5 V VCC − 0.4 V

CCO

= 2.5 V 0.4 V

CCO

= 2.5 V 0.4 V

CCO

Rev. 0 | Page 3 of 16

ADCMP603

www.BDTIC.com/ADI

Parameter Symbol Conditions Min Typ Max Unit

AC PERFORMANCE

Rise Time /Fall time tR/t
10% to 90%, V

Propagation Delay t
V
V

Propagation Delay Skew—Rising to

Falling Transition

Propagation Delay Skew—Q to QB t

Overdrive Dispersion 10 mV < VOD < 125 mV 1.5 ns

Common-Mode Dispersion

Minimum Pulse Width PW

POWER SUPPLY

Input Supply Voltage Range V

Output Supply Voltage Range V

Positive Supply Differential V

Positive Supply Differential V

Input Section Supply Current I

Output Section Supply Current I

Power Dissipation P

P

Power Supply Rejection Ratio PSRR V

Shutdown Mode Supply Current VCC =2.5 V 290 430 µA

1

VIN = 100 mV square input at 50 MHz, VCM = 0 V, CL = 5 pF, V

1

F

PD

t

PINSKEW

DIFFSKEW

MIN

CCI

CCO

− V

CCI

− V

CCI

VCCI

VCCO

D

D

10% to 90%, V

VOD = 50 mV, V

= 50 mV, V

OD

= 10 mV, V

OD

V

= 2.5 V to 5.5 V

CCO

= 50 mV

V

OD

V

=2.5 V to 5.5 V

CCO

= 50 mV

V

OD

−2 V < V
V

V
PW

V
PW

= 50 mV

OD

= V

CCI

CCO

= 90% of PW

OUT

= V

CCI

CCO

= 90% of PW

OUT

CM

2.5 5.5 V

2.5 5.5 V
Operating −3.0 +3.0 V

CCO

Nonoperating −5.5 +5.5 V

CCO

V

= 2.5 V to 5.5 V 1.1 1.8 mA

CCI

V

= 2.5 V to 5.5 V 2.3 3.5 mA

CCI

VCC = 2.5 V 9 11 mW
VCC = 5.5 V 21 30 mW

= 2.5 V to 5.5 V −50 dB

CCI

= V

= 2.5 V, unless otherwise noted.

CCI

CCO

= 2.5 V 2.2 ns

CCO

= 5.5 V 4.5 ns

CCO

= 2.5 V 3.5 ns

CCO

= 5.5 V 4.8 ns

CCO

= 2.5 V 5 ns

CCO

500 ps

300 ps

< V

CCI

= 2.5 V

= 5.5 V

+ 2 V

IN

IN

200 ps

3.3 ns

5.5 ns

Rev. 0 | Page 4 of 16

ADCMP603

www.BDTIC.com/ADI

TIMING INFORMATION

Figure 2 illustrates the ADCMP603 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.

1.1V

LATCH ENABLE

DIFFERENTIAL

INPUT VOLTAGE

Q OUTPUT

Q OUTPUT

t

S

t

H

V

IN

V

OD

t

PDL

t

PDH

t

t

R

t

PL

± V

V

N

OS

t

PLOH

50%

F

50%

t

PLOL

05915-023

Figure 2. System Timing Diagram

Table 2. Timing Descriptions

Symbol Timing Description

t Input to output high delay

PDH

Propagation delay measured from the time the i

nput signal crosses the reference (± the

input offset voltage) to the 50% point of an output low-to-high transition.

t Input to output low delay

PDL

Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.

t Latch enable to output high delay

PLOH

Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.

t Latch enable to output low delay

PLOL

Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.

t Minimum hold time

H

Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.

t Minimum latch enable pulse width Minimum time that the latch enable signal must be high to acquire an input signal change.

PL

t Minimum setup time

S

Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.

t Output rise time

R

Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points.

t Output fall time

F

Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points.

V Voltage overdrive Difference between the input voltages V

OD A

and V .

B

Rev. 0 | Page 5 of 16

ADCMP603

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltages

Input Supply Voltage (V to GND) −0.5 V to +6.0 V

Output Supply Voltage

(V to GND)

CCO

Positive Supply Differential

(V − V )

CCI CCO

Input Voltages

Input Voltage −0.5 V to V + 0.5 V

Differential Input Voltage ±(V + 0.5 V)

Maximum Input/Output Current ±50 mA
Shutdown Control Pin

Applied Voltage (HYS to GND) −0.5 V to V

Maximum Input/Output Current ±50 mA
Latch/Hysteresis Control Pin

Applied Voltage (HYS to GND) −0.5 V to V

Maximum Input/Output Current ±50 mA
Output Current ±50 mA
Temperature

Operating Temperature, Ambient −40°C to +125°C

Operating Temperature, Junction 150°C

Storage Temperature Range −65°C to +150°C

CCI

−0.5 V to +6.0 V

−6.0 V to +6.0 V

CCI

CCI

+ 0.5 V

CCO

+ 0.5 V

CCO

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θ Unit

ADCMP603 LFCSP 12-lead 62 °C/W

1

Measurement in still air.

ESD CAUTION

1

JA

Rev. 0 | Page 6 of 16

ADCMP603

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

EE

Q

Q

V

11

10

12

PIN 1

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 V Output Section Supply.
2 V
3 V
4 V
5 V
6 V
7 S
8 LE/HYS
9 V
10

CCO

CCI

EE

P

EE

N

DN

Input Section Supply.
Negative Supply Voltage.
Noninverting Analog Input.
Negative Supply Voltage.
Inverting Analog Input.
Shutdown. Drive this pin low to shut down the device.
Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch.

EE

Negative Supply Voltage.

Q Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog

voltage at the inverting input, VN, if the comparator is in compare mode. See the LE/HYS pin description (Pin 8)
for more information.

11 V

EE

12 Q

Negative Supply Voltage.
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, V

analog voltage at the inverting input, V
(Pin 8) for more information.

Heat Sink

addle

P

V

EE

The metallic back surface of the package is electrically connected to V
Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the application board if
improved thermal and/or mechanical stability is desired. Exposed metal at package corners is connected to the
heat sink paddle.

CCO

CCI

EE

ADCMP603

2V

3V

(Not to Scale)

TOP VIEW

4

5

P

V

V

INDICATO R

1V

Figure 3. ADCMP603 Pin Configuration

, if the comparator is in compare mode. See the LE pin description

N

9V

EE

8LE/HYS

7S

DN

6

N

EE

V

05915-002

, is greater than the

P

. It can be left floating because Pin 3, Pin 5,

EE

Rev. 0 | Page 7 of 16

ADCMP603

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

V

= V

CCI

= 2.5 V, T = 25°C, unless otherwise noted.

CCO

800

A

4

600

400

200

0

–200

CURRENT (µA)

–400

–600

–800

–101234 567

V

= 2.5V

CC

LE/HYSTERESIS PIN VOLTAGE (V)

VCC= 5.5V

Figure 4. LE/HYS Pin I/V Curve Figure 7. V vs. Load Current

200

150

100

50

0

CURRENT (µA)

–50

VCC = 2.5V

VCC = 5.5V

3

2

1

0

TYPICAL OUTPUT VOLTAGE (V)

–1

05915-007

–2

–5 0 5 10

OUTPUT VO LTAGE

LOAD CURRENT (mA)

OL

15

20

1000

100

10

HYSTERESIS (mV)

VCC = 5.5V

VCC = 2.5V

05915-010

–100

–150

–1 76543210

20

VCC = 2.5V

15

10

5

0

(µA)

B

I

–5

–10

–15

–20

–1.0 –0.5 0 0. 5 1.0 1.5 2.0 2.5 3. 0 3.5

SHUTDOWN PIN VOLTAGE (V)

Figure 5. S Pin I/V Curve

DN

IB @ +125°C

COMMON-MODE VOLTAGE (V)

IB @ +25°C

I

@ –40°C

B

Figure 6. Input Bias Current vs. Input Common Mode

05915-006

05915-005

1

50 150 250 350 450 550 650

350

300

250

200

150

HYSTERESIS (mV)

100

50

0

0 –2 –4 –6 –8 –10 –12 –14 –16 –18

Figure 9. Hysteresis vs. Hysteresis

HYSTERESIS RESISTOR (kΩ)

Figure 8. Hysteresis vs. R

HYSTERESI S @ +125°C

HYSTERESIS @ +25°C

HYSTERESIS PIN CURRENT (µA)

HYS

HYSTERESI S @ –40°C

Pin Current

05915-004

05915-003

Rev. 0 | Page 8 of 16

ADCMP603

V

www.BDTIC.com/ADI

8

7

6

5

4

PROPAGATI ON DELAY (n s)

3

2

0 10 20 30 40 50 60 70 80 90 100 110 120 140130

OVERDRIVE (mV)

05915-009

500mV/DIV M2.00ns

Figure 10. Propagation Delay vs. Input Overdrive Figure 12. 50 MHz Output Voltage Waveform at V

4.0

VCC = 2.5V

3.8

3.6

DELAY (ns)

3.4

3.2

3.0
–0.6 0 0.6 1.2 1. 8 2. 4 3.0

Figure 11. Propagation Delay vs. Input Common Mode

PROP DELAY RI SE ns

PROP DELAY FALL ns

COMMON-MODE VOLTAGE (V)

05915-008

1.00V/DI

Figure 13. 50 MHz Output Voltage Waveform at V

= 2.5 V

CCO

M2.00ns

= 5.5 V

CCO

05915-024

05915-025

Rev. 0 | Page 9 of 16

ADCMP603

+IN–

www.BDTIC.com/ADI

APPLICATION INFORMATION

POWER/GROUND LAYOUT AND BYPASSING

The ADCMP603 comparator is a very high speed device. Despite
t

he low noise output stage, it is essential to use proper high speed
design techniques to achieve the specified performance. Because
comparators are uncompensated amplifiers, feedback in any phase
relationship is likely to cause oscillations or undesired hysteresis. Of
critical importance is the use of low impedance supply planes,
particularly the output supply plane (V
(GND). Individual supply planes are recommended as part of a
multilayer board. Providing the lowest inductance return path for
switching currents ensures the best possible performance in the
target application.

It is also important to adequately bypass the input and output
s

upplies. Multiple high quality 0.01 μF bypass capacitors should
be placed as close as possible to each of the V
pins and should be connected to the GND plane with redundant
vias. At least one of these should be placed to provide a physically
short return path for output currents flowing back from ground
to the V

pin. High frequency bypass capacitors should be

CCO

carefully selected for minimum inductance and ESR. Parasitic
layout inductance should also be strictly controlled to maximize
the effectiveness of the bypass at high frequencies.

If the input and output supplies have been connected separately
su

ch that V

CCI

≠ V

, care should be taken to bypass each of

CCO

these supplies separately to the GND plane. A bypass between
them is futile and defeats the purpose of having separate pins. It
is recommended that the GND plane separate the V
planes when the circuit board layout is designed to minimize
coupling between the two supplies and to take advantage of the
additional bypass capacitance from each respective supply to
the ground plane. This enhances the performance when split
input/output supplies are used. If the input and output supplies
are connected together for single-supply operation such that V
V

, coupling between the two supplies is unavoidable; however,

CCO

careful board placement can help keep output return currents
away from the inputs.

TTL-/CMOS-COMPATIBLE OUTPUT STAGE

Specified propagation delay performance can be achieved only
by keeping the capacitive load at or below the specified minimums.
The low skew complementary outputs of the ADCMP603 are
designed to directly drive one Schottky TTL or three low power
Schottky TTL loads or the equivalent. For large fan outputs,
buses, or transmission lines, use an appropriate buffer to
maintain the excellent speed and stability of the comparator.

With the rated 5 pF load capacitance applied, more than half of

he total device propagation delay is output stage slew time,

t
even at 2.5 V V
as V

decreases, and instability in the power supply may

CCO

appear as excess delay dispersion.

. Because of this, the total prop delay decreases

CC

) and the ground plane

CCO

and V

CCI

CCO

CCI

supply

and V

CCI

CCO

=

This delay is measured to the 50% point for the supply in use;
therefore, the fastest times are observed with the V

supply at

CC

2.5 V, and larger values are observed when driving loads that
switch at other levels.

When duty cycle accuracy is critical, the logic being driven
s

hould switch at 50% of V

minimized. When in doubt, it is best to power V

and load capacitance should be

CC

or the

CCO

entire device from the logic supply and rely on the input PSRR
and CMRR to reject noise.

Overdrive and input slew rate dispersions are not significantly
a

ffected by output loading and V

variations.

CC

The TTL-/CMOS-compatible output stage is shown in the

plified schematic diagram (Figure 14). Because of its

sim
inherent symmetry and generally good behavior, this output
stage is readily adaptable for driving various filters and other
unusual loads.

V

LOGIC

A1

A

V

IN

GAIN STAGE

Figure 14. Simplified Schematic Diagram of

TTL-/CMOS-Comp

A2

OUTPUT STAGE

atible Output Stage

Q1

Q2

OUTPUT

5915-012

USING/DISABLING THE LATCH FEATURE

The latch input is designed for maximum versatility. It can
s

afely be left floating for fixed hysteresis or be tied to V
remove the hysteresis, or it can be driven low by any standard
TTL/CMOS device as a high speed latch.

In addition, the pin can be operated as a hysteresis control pin

th a bias voltage of 1.25 V nominal and an input resistance of

wi
approximately 7000 Ω, allowing the comparator hysteresis to be
easily controlled by either a resistor or an inexpensive CMOS DAC.

Hysteresis control and latch mode can be used together if an
o

pen drain, an open collector, or a three-state driver is connected

parallel to the hysteresis control resistor or current source.

Due to the programmable hysteresis feature, the logic threshold

the latch pin is approximately 1.1 V regardless of V

of

to

CC

.

CC

Rev. 0 | Page 10 of 16

ADCMP603

www.BDTIC.com/ADI

OPTIMIZING PERFORMANCE

As with any high speed comparator, proper design and layout
techniques are essential for obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit performance
and often cause oscillation. Large discontinuities along input
and output transmission lines can also limit the specified pulse­width dispersion performance. The source impedance should
be minimized as much as is practicable. High source impedance,
in combination with the parasitic input capacitance of the
comparator, causes an undesirable degradation in bandwidth at
the input, thus degrading the overall response. Thermal noise
from large resistances can easily cause extra jitter with slowly
slewing input signals; higher impedances encourage undesired
coupling.

COMPARATOR PROPAGATION DELAY DISPERSION

The ADCMP603 comparator is designed to reduce propagation
delay dispersion over a wide input overdrive range of 5 mV to
V

– 1 V. Propagation delay dispersion is the variation in

CCI

propagation delay that results from a change in the degree of
overdrive or slew rate (that is, how far or how fast the input
signal exceeds the switching threshold).

Propagation delay dispersion is a specification that becomes

mportant in high speed, time-critical applications, such as data

i
communication, automatic test and measurement, and instru­mentation. It is also important in event-driven applications, such
as pulse spectroscopy, nuclear instrumentation, and medical
imaging. Dispersion is defined as the variation in propagation
delay as the input overdrive conditions are changed (Figure 15
and Figure 16).

ADCMP603 dispersion is typically < 2 ns as the overdrive varies
from 10 mV to 125 mV. This specification applies to both
positive and negative signals because the device has very closely
matched delays for both positive-going and negative-going
inputs.

500mV OVERDRIVE

INPUT VOLTAGE

10mV OVERDRIVE

± V

V

N

OS

DISPERSION

Q/Q OUTPUT

Figure 15. Propagation Delay—Overdrive Dispersion

05915-013

INPUT VOLTAGE

Q/Q OUTPUT

Figure 16. Propagation Delay—Slew Rate Dispersion

1V/ns

10V/ns

V

± V

N

DISPERSIO N

OS

05915-014

COMPARATOR HYSTERESIS

The addition of hysteresis to a comparator is often desirable in a
noisy environment, or when the differential input amplitudes
are relatively small or slow moving. Figure 17 shows the transfer
function for a comparator with hysteresis. As the input voltage
approaches the threshold (0.0 V, in this example) from below
the threshold region in a positive direction, the comparator
switches from low to high when the input crosses +V
new switching threshold becomes −V
in the high state until the new threshold, −V

/2. The comparator remains

H

/2, is crossed from

H

below the threshold region in a negative direction. In this manner,
noise or feedback output signals centered on 0.0 V input cannot
cause the comparator to switch states unless it exceeds the region
bounded by ±V

/2.

H

OUTPUT

V

OH

V

OL

–V

H

2

Figure 17. Comparator Hysteresis Transfer Function

0

INPUT

+V

H

2

The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. One limitation of this approach is that the amount of
hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that reduce high speed performance and induce
oscillation in some cases.

/2, and the

H

05915-015

Rev. 0 | Page 11 of 16

ADCMP603

www.BDTIC.com/ADI

The ADCMP603 comparator offers a programmable hysteresis
feature that can significantly improve accuracy and stability.
Connecting an external pull-down resistor or a current source
from the LE/HYS pin to GND varies the amount of hysteresis in
a predictable, stable manner. Leaving the LE/HYS pin
disconnected or driving it high removes the hysteresis. The
maximum hysteresis that can be applied using this pin is
approximately 160 mV. Figure 18 illustrates the amount of
hysteresis applied as a function of the external resistor value,
and Figure 9 illustrates hysteresis as a function of the current.

The hysteresis control pin appears as a 1.25 V bias voltage seen
t

hrough a series resistance of 7 kΩ ± 20% throughout the hysteresis
control range. The advantages of applying hysteresis in this manner
are improved accuracy, improved stability, reduced component
count, and maximum versatility. An external bypass capacitor is
not recommended on the HYS pin because it impairs the latch
function and often degrades the jitter performance of the device.
As described in the Using/Disabling the Latch Feature section,
hysteresis control need not compromise the latch function.

CROSSOVER BIAS POINT

In both op amps and comparators, rail-to-rail inputs of this type
have a dual front-end design. Certain devices are active near the
V

rail and others are active near the VEE rail. At some predeter-

CC

mined point in the common-mode range, a crossover occurs. At
this point, typically V
and the measured offset voltages and currents change.

The ADCMP603 slightly elaborates on this scheme. Crossover
p

oints can be found at approximately 0.8 V and 1.6 V.

/2, the direction of the bias current reverses

CC

1000

100

10

HYSTERESIS (mV)

1

50 150 250 350 450 550 650

Figure 18. Hysteresis vs. R Control Resistor

VCC = 5.5V

HYSTERESIS RESISTOR (kΩ)

HYS

VCC = 2.5V

05915-026

MINIMUM INPUT SLEW RATE REQUIREMENT

With the rated load capacitance and normal good PC Board
design practice, as discussed in the Optimizing Performance
section, these comparators should be stable at any input slew
rate with no hysteresis. Broadband noise from the input stage is
observed in place of the violent chattering seen with most other
high speed comparators. With additional capacitive loading or
poor bypassing, more persistent oscillations are seen. This
oscillation is due to the high gain bandwidth of the comparator
in combination with feedback parasitics in the package and PC
board. In many applications, chattering is not harmful since the
first cycle of the oscillation occurs close to V

.

OS

Rev. 0 | Page 12 of 16

ADCMP603

V

V

V

V

±

V

V

www.BDTIC.com/ADI

TYPICAL APPLICATION CIRCUITS

5

2.5V TO 5

LE/HYS

2.5V TO 5

ADCMP603

10kΩ

0.02µF

10kΩ

LE/HYS

+

OUTPUT

–

05915-020

5915-022

0.1µF

INPUT

2kΩ

2kΩ

0.1µF

ADCMP603

Figure 19. Self-Biased, 50% Slicer

100ΩLVDS

ADCMP603

Figure 20. LVDS-to-CMOS Receiver

CMOS
OUTPUT

CMOS
V

DD

2.5V TO 5V

CMOS
OUTPUT

INPUT

ADCMP603

V

REF

05915-017

0.1µF

Figure 22. Duty Cycle to Differential Voltage Converter

DIGITAL

HYSTERESIS

05915-018

CURRENT

Figure 23. Hysteresis Adjustment with Latch

INPUT

74 AHC

1G07

10kΩ

5

10kΩ

150pF

ADCMP603

LE/HYS

CONTROL

VOLTAGE

0V TO 2.5V

150kΩ

10kΩ

150kΩ

Figure 21. Voltage-Controlled Oscillator

OUTPUT

2.5

CMOS
PWM
OUTPUT

INPUT

1.25V
50m

INPUT

1.25V
REF

ADCMP603

10kΩ

10kΩ

ADCMP601

10kΩ

05915-019

82pF

LE/HYS

100kΩ

05915-021

Figure 24. Oscillator and Pulse-Width Modulator

Rev. 0 | Page 13 of 16

ADCMP603

www.BDTIC.com/ADI

2

OUTLINE DIMENSIONS

0.75

0.55

0.35

11

12

1

2

3

6

5

4

PIN 1
INDICATOR

*

1.45

1.30 SQ

1.15

0.25 MIN

PIN 1

INDICATOR

1.00

0.85

0.80

SEATING

PLANE

12° MAX

3.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

*
EXCEPT FO R EXPOSED PAD DI MENSION.

2.75

BSC SQ

EXPOSED PAD

(BOTTOM VIEW )

0.05 MAX

0.02 NOM

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1

0.45

0.60 MAX

10

9

8

7

0.50

BSC

COPLANARITY

0.08

Figure 25. 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

3 mm × 3 mm Body, Very Thin Quad

(CP-12-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

ADCMP603BCPZ-WP −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-12-1 G0D
ADCMP603BCPZ-R2 −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-12-1 G0D
ADCMP603BCPZ-R7 −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-12-1 G0D

1

Z = Pb-free part.

1

1

1

Rev. 0 | Page 14 of 16

ADCMP603

www.BDTIC.com/ADI

NOTES

Rev. 0 | Page 15 of 16

ADCMP603

www.BDTIC.com/ADI

2

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05915-0-10/06(0)

Rev. 0 | Page 16 of 16