ANALOG DEVICES ADCMP603 Service Manual

Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,

V

V

V

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Single-Supply TTL/CMOS Comparator

ADCMP603

FEATURES FUNCTIONAL BLOCK DIAGRAM

Fully specified rail to rail at V = 2.5 V to 5.5 V
Input common-mode voltage from −0.2 V to V + 0.2 V

CC

CC

Low glitch CMOS-/TTL-compatible output stage
Complementary outputs

3.5 ns propagation delay
12 mW at 3.3 V
Shutdown pin
Single-pin control for programmable hysteresis and latch
Power supply rejection > 50 dB

−40°C to +125°C operation

APPLICATIONS

High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)

NONINVERTI NG

P

INVERTING

V

N

INPUT

CCI

INPUT

ADCMP603

Figure 1.

CCO

TTL

LE/HYS INPUT

INPUT

S

DN

Q OUTPUT

Q OUTPUT

05915-001

GENERAL DESCRIPTION

The ADCMP603 is a very fast comparator fabricated on
XFCB2, a
comparator is exceptionally versatile and easy to use. Features
include an input range from V
complementary TTL-/CMOS-compatible output drivers, latch
inputs with adjustable hysteresis and a shutdown input.

The device offers 3.5 ns propagation delay with 10 mV

verdrive on 4 mA typical supply current.

o

A flexible power supply scheme allows the device to operate
wi
input signal range up to a +5.5 V positive supply with a −0.5 V
to +5.8 V input signal range. Split input/output supplies with no
sequencing restrictions support a wide input signal range while
still allowing independent output swing control and power
savings.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

n Analog Devices, Inc. proprietary process. This

− 0.5 V to V

EE CC

+ 0.2 V, low noise

th a single +2.5 V positive supply and a −0.5 V to +2.8 V

The device passes 4.5 kV HBM ESD testing and the absolute
maximum ratings include current limits for all pins.

The complementary TTL-/CMOS-compatible output stage is
designed to drive up to 5 pF with full timing specs and to
degrade in a graceful and linear fashion as additional
capacitance is added. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded.
Latch and programmable hysteresis features are also provided
with a unique single-pin control option.

The ADCMP603 is available in a 12-lead LFCSP package.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADCMP603

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Timing Information ......................................................................... 5

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

REVISION HISTORY

10/06—Revision 0: Initial Version

Application Information................................................................ 10

Power/Ground Layout and Bypassing..................................... 10

TTL-/CMOS-Compatible Output Stage ................................. 10

Using/Disabling the Latch Feature........................................... 10

Optimizing Performance........................................................... 11

Comparator Propagation Delay Dispersion ........................... 11

Comparator Hysteresis .............................................................. 11

Crossover Bias Point .................................................................. 12

Minimum Input Slew Rate Requirement................................ 12

Typical Application Circuits ......................................................... 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. 0 | Page 2 of 16

ADCMP603

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SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

V

= V

CCI

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

DC INPUT CHARACTERISTICS

Voltage Range VP, V
Common-Mode Range VCC = 2.5 V to 5.5 V −0.2 VCC + 0.2 V
Differential Voltage VCC = 2.5 V to 5.5 V VCC + 0.8 V
Offset Voltage V
Bias Current IP, I
Offset Current −2.0 2.0 µA
Capacitance CP, C
Resistance, Differential Mode −0.5 V to VCC + 0.2 V 200 700 kΩ
Resistance, Common Mode −0.2 V to VCC + 0.2 V 100 350 kΩ
Active Gain A
Common-Mode Rejection Ratio CMRR

Hysteresis R

LATCH ENABLE PIN CHARACTERISTICS

V
V
I

IH

I

OL

HYSTERESIS MODE AND TIMING

Hysteresis Mode Bias Voltage Current sink −1 A 1.145 1.25 1.35 V
Resistor Value Hysteresis = 120 mV 65 80 95 kΩ
Hysteresis Current Hysteresis = 120 mV −18 −14 −10 µA
Latch Setup Time t
Latch Hold Time t
Latch-to-Output Delay t
Latch Minimum Pulse Width t

SHUTDOWN PIN CHARACTERISTICS

V
V
I

IH

I

OL

Sleep Time t
Wake-Up Time t

DC OUTPUT CHARACTERISTICS V

Output Voltage High Level V
Output Voltage High Level −40°C V
Output Voltage Low Level V
Output Voltage Low Level −40°C V

= 2.5 V, TA = 25°C, unless otherwise noted.

CCO

IH

IL

IH

IL

N

OS

N

N

V

Hysteresis is shut off 2.0 V

VCC = 2.5 V to 5.5 V −0.5 VCC + 0.2 V

−5.0 ±2 +5.0 mV

−5.0 ±2 +5.0 µA

1.0 pF

85 dB
V

= 2.5 V, V

CCI

= −0.2 V to +2.7 V

V

CM

V

= 5.5 V, V

CCI

V

= −0.2 V to +5.7 V

CM

= ∞ 0.1 mV

HYS

= 2.5 V,

CCO

= 5.5 V,

CCO

50 dB

50 dB

CC

V
Latch mode guaranteed −0.2 +0.4 +0.8 V
V
V

S

H

, t

PLOH

PLOL

PL

Comparator is operating 2.0 V

= V

IH

CC

= 0.4 V −0.1 mA

IL

−6 +6 µA

VOD = 50 mV −2.0 ns
VOD = 50 mV 2.0 ns
VOD = 50 mV 30 ns
VOD = 50 mV 23 ns

CCO

V
Shutdown guaranteed −0.2 +0.4 +0.6 V
V
V

SD

H

OH

OH

OL

OL

= VCC −6 +6 µA

IH

= 0 V −80 µA

IL

I

< 0.5 mA 20 ns

OUT

VOD = 100 mV, output valid 50 ns

= 2.5 V to 5.5 V

CCO

IOH = 8 mA V
IOH = 6 mA V
IOL = 8 mA, V
IOL = 6 mA, V

= 2.5 V VCC − 0.4 V

CCO

= 2.5 V VCC − 0.4 V

CCO

= 2.5 V 0.4 V

CCO

= 2.5 V 0.4 V

CCO

Rev. 0 | Page 3 of 16

ADCMP603

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Parameter Symbol Conditions Min Typ Max Unit

AC PERFORMANCE

Rise Time /Fall time tR/t
10% to 90%, V

Propagation Delay t
V
V

Propagation Delay Skew—Rising to

Falling Transition

Propagation Delay Skew—Q to QB t

Overdrive Dispersion 10 mV < VOD < 125 mV 1.5 ns

Common-Mode Dispersion

Minimum Pulse Width PW

POWER SUPPLY

Input Supply Voltage Range V

Output Supply Voltage Range V

Positive Supply Differential V

Positive Supply Differential V

Input Section Supply Current I

Output Section Supply Current I

Power Dissipation P

P

Power Supply Rejection Ratio PSRR V

Shutdown Mode Supply Current VCC =2.5 V 290 430 µA

1

VIN = 100 mV square input at 50 MHz, VCM = 0 V, CL = 5 pF, V

1

F

PD

t

PINSKEW

DIFFSKEW

MIN

CCI

CCO

− V

CCI

− V

CCI

VCCI

VCCO

D

D

10% to 90%, V

VOD = 50 mV, V

= 50 mV, V

OD

= 10 mV, V

OD

V

= 2.5 V to 5.5 V

CCO

= 50 mV

V

OD

V

=2.5 V to 5.5 V

CCO

= 50 mV

V

OD

−2 V < V
V

V
PW

V
PW

= 50 mV

OD

= V

CCI

CCO

= 90% of PW

OUT

= V

CCI

CCO

= 90% of PW

OUT

CM

2.5 5.5 V

2.5 5.5 V
Operating −3.0 +3.0 V

CCO

Nonoperating −5.5 +5.5 V

CCO

V

= 2.5 V to 5.5 V 1.1 1.8 mA

CCI

V

= 2.5 V to 5.5 V 2.3 3.5 mA

CCI

VCC = 2.5 V 9 11 mW
VCC = 5.5 V 21 30 mW

= 2.5 V to 5.5 V −50 dB

CCI

= V

= 2.5 V, unless otherwise noted.

CCI

CCO

= 2.5 V 2.2 ns

CCO

= 5.5 V 4.5 ns

CCO

= 2.5 V 3.5 ns

CCO

= 5.5 V 4.8 ns

CCO

= 2.5 V 5 ns

CCO

500 ps

300 ps

< V

CCI

= 2.5 V

= 5.5 V

+ 2 V

IN

IN

200 ps

3.3 ns

5.5 ns

Rev. 0 | Page 4 of 16

ADCMP603

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TIMING INFORMATION

Figure 2 illustrates the ADCMP603 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.

1.1V

LATCH ENABLE

DIFFERENTIAL

INPUT VOLTAGE

Q OUTPUT

Q OUTPUT

t

S

t

H

V

IN

V

OD

t

PDL

t

PDH

t

t

R

t

PL

± V

V

N

OS

t

PLOH

50%

F

50%

t

PLOL

05915-023

Figure 2. System Timing Diagram

Table 2. Timing Descriptions

Symbol Timing Description

t Input to output high delay

PDH

Propagation delay measured from the time the i

nput signal crosses the reference (± the

input offset voltage) to the 50% point of an output low-to-high transition.

t Input to output low delay

PDL

Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.

t Latch enable to output high delay

PLOH

Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.

t Latch enable to output low delay

PLOL

Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.

t Minimum hold time

H

Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.

t Minimum latch enable pulse width Minimum time that the latch enable signal must be high to acquire an input signal change.

PL

t Minimum setup time

S

Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.

t Output rise time

R

Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points.

t Output fall time

F

Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points.

V Voltage overdrive Difference between the input voltages V

OD A

and V .

B

Rev. 0 | Page 5 of 16