Analog Devices ADCMP600BKJZ, ADCMP600BRJZ, ADCMP601BKJZ, ADCMP602BRMZ Schematic

Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,

Single-Supply TTL/CMOS Comparators

ADCMP600/ADCMP601/ADCMP602

FEATURES FUNCTIONAL BLOCK DIAGRAM

Fully specified rail to rail at VCC = 2.5 V to 5.5 V Input common-mode voltage from −0.2 V to V Low glitch CMOS-/TTL-compatible output stage

3.5 ns propagation delay 10 mW at 3.3 V Shutdown pin

+ 0.2 V

CC

NONINVERTI NG

INPUT

INVERTING

INPUT

ADCMP600/ ADCMP601/

ADCMP602

Q OUTPUT

Single-pin control for programmable hysteresis and latch Power supply rejection > 50 dB Improved replacement for MAX999

−40°C to +125°C operation

(EXCEPT ADCMP600)

LE/HYS

S

DN

(ADCMP602 ONLY)

Figure 1.

APPLICATIONS

High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current/voltage-controlled oscillators Automatic test equipment (ATE)

05914-001

GENERAL DESCRIPTION

The ADCMP600, ADCMP601, and ADCMP602 are very fast comparators fabricated on XFCB2, an Analog Devices, Inc. proprietary process. These comparators are exceptionally versatile and easy to use. Features include an input range from V

− 0.5 V to VCC + 0.2 V, low noise, TTL-/CMOS-compatible

EE

output drivers, and latch inputs with adjustable hysteresis and/or shutdown inputs.

The device offers 5 ns propagation delay with 10 mV overdrive on 3 mA typical supply current.

A flexible power supply scheme allows the devices to operate with a single +2.5 V positive supply and a −0.5 V to +2.8 V input signal range up to a +5.5 V positive supply with a −0.5 V to +5.8 V input signal range. Split input/output supplies with no sequencing restrictions on the ADCMP602 support a wide

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

input signal range while still allowing independent output swing control and power savings.

The TTL-/CMOS-compatible output stage is designed to drive up to 5 pF with full timing specs and to degrade in a graceful and linear fashion as additional capacitance is added. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. Latch and programmable hysteresis features are also provided with a unique single-pin control option.

The ADCMP600 is available in 5-lead SC70 and SOT-23 packages, the ADCMP601 is available in a 6-lead SC70 package, and the ADCMP602 is available in an 8-lead MSOP package.

ADCMP600/ADCMP601/ADCMP602

REVISION HISTORY

10/06—Revision 0: Initial Version

Power/Ground Layout and Bypassing..................................... 10

TTL-/CMOS-Compatible Output Stage ................................. 10

Using/Disabling the Latch Feature........................................... 10

Optimizing Performance........................................................... 11

Comparator Propagation Delay Dispersion ........................... 11

Comparator Hysteresis .............................................................. 11

Crossover Bias Point .................................................................. 12

Minimum Input Slew Rate Requirement ................................ 12

Typical Application Circuits ......................................................... 13

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. 0 | Page 2 of 16

ADCMP600/ADCMP601/ADCMP602

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

V

= V

CCI

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

DC INPUT CHARACTERISTICS

Voltage Range VP, VN V Common-Mode Range VCC = 2.5 V to 5.5 V −0.2 VCC + 0.2 V Differential Voltage VCC = 2.5 V to 5.5 V VCC + 0.8 V Offset Voltage VOS −5.0 ±2 +5.0 mV Bias Current IP, IN −5.0 ±2 +5.0 µA Offset Current −2.0 +2.0 µA Capacitance CP, CN 1 pF Resistance, Differential Mode −0.1 V to VCC 200 700 kΩ Resistance, Common Mode −0.5 V to VCC + 0.5 V 100 350 kΩ Active Gain AV 85 dB

Hysteresis (ADCMP600) 2 mV Hysteresis (ADCMP601/ADCMP602) R

LATCH ENABLE PIN CHARACTERISTICS

(ADCMP601/ADCMP602 Only) VIH Hysteresis is shut off 2.0 VCC V VIL Latch mode guaranteed −0.2 +0.4 +0.8 V IIH V IOL V

HYSTERESIS MODE AND TIMING (ADCMP601/ADCMP602 Only)

Hysteresis Mode Bias Voltage Current −1 A 1.145 1.25 1.35 V Resistor Value Hysteresis = 120 mV 65 80 120 kΩ Hysteresis Current Hysteresis = 120 mV −18 −12 −7 µA Latch Setup Time tS V Latch Hold Time tH V Latch-to-Output Delay t Latch Minimum Pulse Width tPL V

SHUTDOWN PIN CHARACTERISTICS

(ADCMP602 Only) VIH Comparator is operating 2.0 V VIL Shutdown guaranteed −0.2 +0.4 +0.6 V IIH V IOL V Sleep Time tSD I Wake-Up Time tH V

DC OUTPUT CHARACTERISTICS V

Output Voltage High Level VOH I Output Voltage Low Level VOL I Output Voltage High Level at −40°C VOH I Output Voltage Low Level at− 40°C VOL I

= 2.5 V, TA = 25°C, unless otherwise noted.

CCO

PLOH

= 2.5 V to 5.5 V −0.5 VCC + 0.2 V

CC

V

= 2.5 V, V

CCI

V

= −0.2 V to +2.7 V

CM

= 2.5 V, V

V

CCI

= ∞ 0.1 mV

HYS

= VCC −6 +6 µA

IH

= 0.4 V −0.1 +0.1 mA

IL

= 50 mV −2 ns

OD

= 50 mV 2.6 ns

OD

, t

VOD = 50 mV 27 ns

PLOL

= 50 mV 21 ns

OD

= VCC −6 6 µA

IH

= 0 V −100 µA

IL

< 500 µA 20 ns

CCO

= 100 mV, output valid 50 ns

OD

= 2.5 V to 5.5 V

CCO

= 8 mA, V

OH

= 8 mA, V

OL

= 6 mA, V

OH

= 6 mA, V

OL

= 2.5 V,

CCO

= 5.5 V 50 dB

CCO

= 2.5 V VCC − 0.4 V

CCO

= 2.5 V 0.4 V

CCO

= 2.5 V VCC − 0.4 V

CCO

= 2.5 V 0.4 V

CCO

50 dB Common-Mode Rejection Ratio CMRR

V

CCO

Rev. 0 | Page 3 of 16

ADCMP600/ADCMP601/ADCMP602

Parameter Symbol Conditions Min Typ Max Unit

AC PERFORMANCE

Rise Time /Fall Time tR tF 10% to 90%, V 10% to 90%, V

Propagation Delay tPD V V V

Propagation Delay Skew—Rising to

Falling Transition Overdrive Dispersion 10 mV < VOD < 125 mV 1.2 ns Common-Mode Dispersion

Minimum Pulse Width PW

POWER SUPPLY

Input Supply Voltage Range V Output Supply Voltage Range V Positive Supply Differential V

(ADCMP602 Only) V Positive Supply Current (ADCMP600/ADCMP601) Input Section Supply Current I

(ADCMP602 Only) V Output Section Supply Current I

(ADCMP602 Only) V Power Dissipation PD V P Power Supply Rejection Ratio PSRR V Shutdown Mode I

(ADCMP602 Only) Shutdown Mode I

(ADCMP602 Only)

1

VIN = 100 mV square input at 50 MHz, VCM = 0 V, CL = 5 pF, V

1

VCC = 2.5 V 240 400 µA

CCI

V

CCO

= 2.5 V 2.2 ns

CCO

= 5.5 V 4 ns

CCO

= 50 mV, V

OD

= 50 mV, V

OD

= 10 mV, V

OD

V

= 2.5 V to 5.5 V

CCO

= 50 mV

V

OD

−0.2 V < V V

= 50 mV

OD

MIN

2.5 5.5 V

CCI

2.5 5.5 V

CCO

− V

CCI

CCO

− V

CCI

CCO

I

V

VCC

V

VCCI

V

VCCO

V

D

= V

CCI

= V

V

CCI

CCO

= 90% of PWIN

PW

OUT

= V

V

CCI

CCO

= 90% of PWIN

PW

OUT

Operating −3.0 +3.0 V

Nonoperating −5.5 +5.5 V

= 2.5 V

CC

= 5.5 V

V

CC

= 2.5 V 0.9 1.4 mA

CCI

= 5.5 V 1.2 2.0 mA

CCI

= 2.5 V 1.45 3.0 mA

CCO

= 5.5 V 2.1 3.5 mA

CCO

= 2.5 V 7 9 mW

CC

= 5.5 V 20 23 mW

CC

= 2.5 V to 5 V −50 dB

CCI

=2.5 V 30 µA

CC

=2.5 V, unless otherwise noted.

CCO

= 2.5 V 3.5 ns

CCO

= 5.5 V 4.3 ns

CCO

= 2.5 V 5 ns

CCO

500 ps

< V

CM

= 2.5 V

= 5.5 V

+ 2 V

CCI

200 ps

3 ns

4.5 ns

3

3.5

4.0

mA

Rev. 0 | Page 4 of 16

ADCMP600/ADCMP601/ADCMP602

TIMING INFORMATION

Figure 2 illustrates the ADCMP600/ADCMP601/ADCMP602 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.

1.1V

LATCH ENABLE

DIFFERENTIAL

INPUT VOLTAGE

Q OUTPUT

t

S

t

H

V

IN

V

OD

t

PDL

t

PL

V

± V

N

OS

t

PLOH

50%

F

05914-025

Figure 2. System Timing Diagram

Table 2. Timing Descriptions

Symbol Timing Description

t

Input to output high delay

PDH

Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output low-to-high transition.

t

Input to output low delay

PDL

Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output high-to-low transition.

t

Latch enable to output high delay

PLOH

Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition.

t

Latch enable to output low delay

PLOL

Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition.

tH Minimum hold time

Minimum time after the negative transition of the latch enable signal that the input signal

must remain unchanged to be acquired and held at the outputs. tPL Minimum latch enable pulse width Minimum time that the latch enable signal must be high to acquire an input signal change. tS Minimum setup time

Minimum time before the negative transition of the latch enable signal occurs that an

input signal change must be present to be acquired and held at the outputs. tR Output rise time

Amount of time required to transition from a low to a high output as measured at the 20%

and 80% points. tF Output fall time

Amount of time required to transition from a high to a low output as measured at the 20%

and 80% points. VOD Voltage overdrive Difference between the input voltages VA and VB.

Rev. 0 | Page 5 of 16

ADCMP600/ADCMP601/ADCMP602

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltages

Input Supply Voltage (V Output Supply Voltage

to GND)

(V

CCO

Positive Supply Differential

− V

(V

CCI

CCO

)

to GND) −0.5 V to +6.0 V

CCI

−0.5 V to +6.0 V

−6.0 V to +6.0 V

Input Voltages

Input Voltage −0.5 V to V Differential Input Voltage ±(V

CCI

+ 0.5 V)

+ 0.5 V

Maximum Input/Output Current ±50 mA

Shutdown Control Pin

Applied Voltage (HYS to GND) −0.5 V to V

+ 0.5 V

CCO

Maximum Input/Output Current ±50 mA

Latch/Hysteresis Control Pin

Applied Voltage (HYS to GND) −0.5 V to V

+ 0.5 V

CCO

Maximum Input/Output Current ±50 mA Output Current ±50 mA Temperature

Operating Temperature, Ambient −40°C to +125°C

Operating Temperature, Junction 150°C

Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θ

ADCMP600 SC70 5-Lead 426 °C/W ADCMP600 SOT-23 5-Lead 302 °C/W ADCMP601 SC70 6-Lead 426 °C/W ADCMP602 MSOP 5-Lead 130 °C/W

1

Measurement in still air.

ESD CAUTION

1

Unit

JA

Rev. 0 | Page 6 of 16

Analog Devices ADCMP600BKJZ, ADCMP600BRJZ, ADCMP601BKJZ, ADCMP602BRMZ Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

TIMING INFORMATION

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION