Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply TTL/CMOS Comparators
ADCMP600/ADCMP601/ADCMP602
FEATURES FUNCTIONAL BLOCK DIAGRAM
Fully specified rail to rail at VCC = 2.5 V to 5.5 V
Input common-mode voltage from −0.2 V to V
Low glitch CMOS-/TTL-compatible output stage
3.5 ns propagation delay
10 mW at 3.3 V
Shutdown pin
+ 0.2 V
CC
NONINVERTI NG
INPUT
INVERTING
INPUT
ADCMP600/
ADCMP601/
ADCMP602
Q OUTPUT
Single-pin control for programmable hysteresis and latch
Power supply rejection > 50 dB
Improved replacement for MAX999
−40°C to +125°C operation
(EXCEPT ADCMP600)
LE/HYS
S
DN
(ADCMP602 ONLY)
Figure 1.
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current/voltage-controlled oscillators
Automatic test equipment (ATE)
05914-001
GENERAL DESCRIPTION
The ADCMP600, ADCMP601, and ADCMP602 are very fast
comparators fabricated on XFCB2, an Analog Devices, Inc.
proprietary process. These comparators are exceptionally
versatile and easy to use. Features include an input range from
V
− 0.5 V to VCC + 0.2 V, low noise, TTL-/CMOS-compatible
EE
output drivers, and latch inputs with adjustable hysteresis
and/or shutdown inputs.
The device offers 5 ns propagation delay with 10 mV overdrive
on 3 mA typical supply current.
A flexible power supply scheme allows the devices to operate
with a single +2.5 V positive supply and a −0.5 V to +2.8 V
input signal range up to a +5.5 V positive supply with a −0.5 V
to +5.8 V input signal range. Split input/output supplies with no
sequencing restrictions on the ADCMP602 support a wide
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
input signal range while still allowing independent output
swing control and power savings.
The TTL-/CMOS-compatible output stage is designed to drive
up to 5 pF with full timing specs and to degrade in a graceful
and linear fashion as additional capacitance is added. The
comparator input stage offers robust protection against large
input overdrive, and the outputs do not phase reverse when the
valid input signal range is exceeded. Latch and programmable
hysteresis features are also provided with a unique single-pin
control option.
The ADCMP600 is available in 5-lead SC70 and SOT-23
packages, the ADCMP601 is available in a 6-lead SC70 package,
and the ADCMP602 is available in an 8-lead MSOP package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
ADCMP600/ADCMP601/ADCMP602
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics ............................................................. 3
Timing Information......................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Application Information................................................................ 10
REVISION HISTORY
10/06—Revision 0: Initial Version
Power/Ground Layout and Bypassing..................................... 10
TTL-/CMOS-Compatible Output Stage ................................. 10
Using/Disabling the Latch Feature........................................... 10
Optimizing Performance........................................................... 11
Comparator Propagation Delay Dispersion ........................... 11
Comparator Hysteresis .............................................................. 11
Crossover Bias Point .................................................................. 12
Minimum Input Slew Rate Requirement ................................ 12
Typical Application Circuits ......................................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Rev. 0 | Page 2 of 16
ADCMP600/ADCMP601/ADCMP602
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
= V
CCI
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
DC INPUT CHARACTERISTICS
Voltage Range VP, VN V
Common-Mode Range VCC = 2.5 V to 5.5 V −0.2 VCC + 0.2 V
Differential Voltage VCC = 2.5 V to 5.5 V VCC + 0.8 V
Offset Voltage VOS −5.0 ±2 +5.0 mV
Bias Current IP, IN −5.0 ±2 +5.0 µA
Offset Current −2.0 +2.0 µA
Capacitance CP, CN 1 pF
Resistance, Differential Mode −0.1 V to VCC 200 700 kΩ
Resistance, Common Mode −0.5 V to VCC + 0.5 V 100 350 kΩ
Active Gain AV 85 dB
Hysteresis (ADCMP600) 2 mV
Hysteresis (ADCMP601/ADCMP602) R
LATCH ENABLE PIN CHARACTERISTICS
(ADCMP601/ADCMP602 Only)
VIH Hysteresis is shut off 2.0 VCC V
VIL Latch mode guaranteed −0.2 +0.4 +0.8 V
IIH V
IOL V
HYSTERESIS MODE AND TIMING
(ADCMP601/ADCMP602 Only)
Hysteresis Mode Bias Voltage Current −1 A 1.145 1.25 1.35 V
Resistor Value Hysteresis = 120 mV 65 80 120 kΩ
Hysteresis Current Hysteresis = 120 mV −18 −12 −7 µA
Latch Setup Time tS V
Latch Hold Time tH V
Latch-to-Output Delay t
Latch Minimum Pulse Width tPL V
SHUTDOWN PIN CHARACTERISTICS
(ADCMP602 Only)
VIH Comparator is operating 2.0 V
VIL Shutdown guaranteed −0.2 +0.4 +0.6 V
IIH V
IOL V
Sleep Time tSD I
Wake-Up Time tH V
DC OUTPUT CHARACTERISTICS V
Output Voltage High Level VOH I
Output Voltage Low Level VOL I
Output Voltage High Level at −40°C VOH I
Output Voltage Low Level at− 40°C VOL I
= 2.5 V, TA = 25°C, unless otherwise noted.
CCO
PLOH
= 2.5 V to 5.5 V −0.5 VCC + 0.2 V
CC
V
= 2.5 V, V
CCI
V
= −0.2 V to +2.7 V
CM
= 2.5 V, V
V
CCI
= ∞ 0.1 mV
HYS
= VCC −6 +6 µA
IH
= 0.4 V −0.1 +0.1 mA
IL
= 50 mV −2 ns
OD
= 50 mV 2.6 ns
OD
, t
VOD = 50 mV 27 ns
PLOL
= 50 mV 21 ns
OD
= VCC −6 6 µA
IH
= 0 V −100 µA
IL
< 500 µA 20 ns
CCO
= 100 mV, output valid 50 ns
OD
= 2.5 V to 5.5 V
CCO
= 8 mA, V
OH
= 8 mA, V
OL
= 6 mA, V
OH
= 6 mA, V
OL
= 2.5 V,
CCO
= 5.5 V 50 dB
CCO
= 2.5 V VCC − 0.4 V
CCO
= 2.5 V 0.4 V
CCO
= 2.5 V VCC − 0.4 V
CCO
= 2.5 V 0.4 V
CCO
50 dB Common-Mode Rejection Ratio CMRR
V
CCO
Rev. 0 | Page 3 of 16
ADCMP600/ADCMP601/ADCMP602
Parameter Symbol Conditions Min Typ Max Unit
AC PERFORMANCE
Rise Time /Fall Time tR tF 10% to 90%, V
10% to 90%, V
Propagation Delay tPD V
V
V
Propagation Delay Skew—Rising to
Falling Transition
Overdrive Dispersion 10 mV < VOD < 125 mV 1.2 ns
Common-Mode Dispersion
Minimum Pulse Width PW
POWER SUPPLY
Input Supply Voltage Range V
Output Supply Voltage Range V
Positive Supply Differential V
(ADCMP602 Only)
V
Positive Supply Current
(ADCMP600/ADCMP601)
Input Section Supply Current I
(ADCMP602 Only) V
Output Section Supply Current I
(ADCMP602 Only) V
Power Dissipation PD V
P
Power Supply Rejection Ratio PSRR V
Shutdown Mode I
(ADCMP602 Only)
Shutdown Mode I
(ADCMP602 Only)
1
VIN = 100 mV square input at 50 MHz, VCM = 0 V, CL = 5 pF, V
1
VCC = 2.5 V 240 400 µA
CCI
V
CCO
= 2.5 V 2.2 ns
CCO
= 5.5 V 4 ns
CCO
= 50 mV, V
OD
= 50 mV, V
OD
= 10 mV, V
OD
V
= 2.5 V to 5.5 V
CCO
= 50 mV
V
OD
−0.2 V < V
V
= 50 mV
OD
MIN
2.5 5.5 V
CCI
2.5 5.5 V
CCO
− V
CCI
CCO
− V
CCI
CCO
I
V
VCC
V
VCCI
V
VCCO
V
D
= V
CCI
= V
V
CCI
CCO
= 90% of PWIN
PW
OUT
= V
V
CCI
CCO
= 90% of PWIN
PW
OUT
Operating −3.0 +3.0 V
Nonoperating −5.5 +5.5 V
= 2.5 V
CC
= 5.5 V
V
CC
= 2.5 V 0.9 1.4 mA
CCI
= 5.5 V 1.2 2.0 mA
CCI
= 2.5 V 1.45 3.0 mA
CCO
= 5.5 V 2.1 3.5 mA
CCO
= 2.5 V 7 9 mW
CC
= 5.5 V 20 23 mW
CC
= 2.5 V to 5 V −50 dB
CCI
=2.5 V 30 µA
CC
=2.5 V, unless otherwise noted.
CCO
= 2.5 V 3.5 ns
CCO
= 5.5 V 4.3 ns
CCO
= 2.5 V 5 ns
CCO
500 ps
< V
CM
= 2.5 V
= 5.5 V
+ 2 V
CCI
200 ps
3 ns
4.5 ns
3
3.5
3.5
4.0
mA
Rev. 0 | Page 4 of 16
ADCMP600/ADCMP601/ADCMP602
TIMING INFORMATION
Figure 2 illustrates the ADCMP600/ADCMP601/ADCMP602 latch timing relationships. Table 2 provides definitions of the terms shown
in Figure 2.
1.1V
LATCH ENABLE
DIFFERENTIAL
INPUT VOLTAGE
Q OUTPUT
t
S
t
H
V
IN
V
OD
t
PDL
t
t
PL
V
± V
N
OS
t
PLOH
50%
F
05914-025
Figure 2. System Timing Diagram
Table 2. Timing Descriptions
Symbol Timing Description
t
Input to output high delay
PDH
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
t
Input to output low delay
PDL
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
t
Latch enable to output high delay
PLOH
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
t
Latch enable to output low delay
PLOL
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
tH Minimum hold time
Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.
tPL Minimum latch enable pulse width Minimum time that the latch enable signal must be high to acquire an input signal change.
tS Minimum setup time
Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.
tR Output rise time
Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points.
tF Output fall time
Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points.
VOD Voltage overdrive Difference between the input voltages VA and VB.
Rev. 0 | Page 5 of 16
ADCMP600/ADCMP601/ADCMP602
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltages
Input Supply Voltage (V
Output Supply Voltage
to GND)
(V
CCO
Positive Supply Differential
− V
(V
CCI
CCO
)
to GND) −0.5 V to +6.0 V
CCI
−0.5 V to +6.0 V
−6.0 V to +6.0 V
Input Voltages
Input Voltage −0.5 V to V
Differential Input Voltage ±(V
CCI
CCI
+ 0.5 V)
+ 0.5 V
Maximum Input/Output Current ±50 mA
Shutdown Control Pin
Applied Voltage (HYS to GND) −0.5 V to V
+ 0.5 V
CCO
Maximum Input/Output Current ±50 mA
Latch/Hysteresis Control Pin
Applied Voltage (HYS to GND) −0.5 V to V
+ 0.5 V
CCO
Maximum Input/Output Current ±50 mA
Output Current ±50 mA
Temperature
Operating Temperature, Ambient −40°C to +125°C
Operating Temperature, Junction 150°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θ
ADCMP600 SC70 5-Lead 426 °C/W
ADCMP600 SOT-23 5-Lead 302 °C/W
ADCMP601 SC70 6-Lead 426 °C/W
ADCMP602 MSOP 5-Lead 130 °C/W
1
Measurement in still air.
ESD CAUTION
1
Unit
JA
Rev. 0 | Page 6 of 16
ADCMP600/ADCMP601/ADCMP602
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Q
V
EE
V
P
1
ADCMP600
2
TOP VIEW
(Not to S cale)
3
5
4
V
CCI/VCCO
V
N
1
Q
ADCMP601
2
V
05914-002
EE
V
P
TOP VIEW
(Not to Scal e)
3
6
5
4
V
CCI/VCCO
LE/HYS
V
N
1
V
CCI
ADCMP602
2
V
P
TOP VIEW
3
V
N
(Not to Scale)
S
4
05914-003
DN
8
V
CCO
Q7
6
V
EE
LE/HYS5
Figure 3. ADCMP600 Pin Configuration Figure 4. ADCMP601 Pin Configuration Figure 5. ADCMP602 Pin Configuration
Table 5. ADCMP600 (SOT-23-5 and SC70-5) Pin Function Descriptions
Pin No. Mnemonic Description
1 Q
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, V
than the analog voltage at the inverting input, V
.
N
, is greater
P
2 VEE Negative Supply Voltage.
3 VP Noninverting Analog Input.
4 VN Inverting Analog Input.
5 V
Input Section Supply/Output Section Supply. Shared pin.
CCI/VCCO
Table 6. ADCMP601 (SC70-6) Pin Function Descriptions
Pin No. Mnemonic Description
1 Q
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, V
than the analog voltage at the inverting input, V
, if the comparator is in compare mode.
N
, is greater
P
2 VEE Negative Supply Voltage.
3 VP Noninverting Analog Input.
4 VN Inverting Analog Input.
5 LE/HYS Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch.
6 V
Input Section Supply/Output Section Supply. Shared pin.
CCI/VCCO
05914-004
Table 7. ADCMP602 (MSOP-8) Pin Function Descriptions
Pin No. Mnemonic Description
1 V
Input Section Supply.
CCI
2 VP Noninverting Analog Input.
3 VN Inverting Analog Input.
4 SDN Shutdown. Drive this pin low to shut down the device.
5 LE/HYS Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch.
6 VEE Negative Supply Voltage.
7 Q
8 V
Output Section Supply.
CCO
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, V
than the analog voltage at the inverting input, V
, if the comparator is in compare mode.
N
, is greater
P
Rev. 0 | Page 7 of 16
ADCMP600/ADCMP601/ADCMP602
TYPICAL PERFORMANCE CHARACTERISTICS
V
= V
CCI
= 2.5 V, TA = 25°C, unless otherwise noted.
CCO
800
600
400
200
0
–200
CURRENT (µA)
–400
–600
–800
–101234 567
V
CC
= 2.5V
LE/HYS (V)
VCC= 5.5V
Figure 6. LE/HYS Pin I/V Characteristics
150
100
50
0
CURRENT (µA)
–50
VCC = 2.5V VCC = 5.5V
20
15
10
5
0
–5
LOAD CURRENT (mA)
–10
–15
05914-007
–20
–1.0 –0.2 0.2 0.6–0.6 1.01.41.82.22.63.03.4
Figure 9. V
250
200
VCC= 5.5V
150
100
HYSTERESIS (mV)
IOL VS V
V
OUT
vs. Current Load
OH/VOL
OL
IOH VS V
(V)
OH
09514-011
–100
–150
–1 10235476
20
VCC = 2.5V
15
10
5
0
(µA)
B
I
–5
–10
–15
–20
–1.0 –0.5 0 0.5 1. 0 1.5 2.0 2.5 3. 0 3.5
SHUTDOWN PI N VOLTAGE (V)
Figure 7. S
IB @ +125°C
I
@ +25°C
B
I
B
Pin I/V Characteristics
DN
@ –40°C
COMMON-MODE VOLTAGE (V)
Figure 8. Input Bias Current vs. Input Common Mode
05914-027
05914-005
Rev. 0 | Page 8 of 16
50
V
= 2.5V
CC
0
50 150 250 450350 55 0 650
Figure 10. Hysteresis vs. R
450
400
350
300
250
200
150
HYSTERESIS (mV)
100
50
0
0 –5 –10 –15 –20
HYSTERESIS RESISTOR (kΩ)
Control Resistor
HYS
PIN CURRENT (µA)
Figure 11. Hysteresis vs. Pin Current
05914-008
LOT 1
LOT 2
05914-026
ADCMP600/ADCMP601/ADCMP602
4.8
4.6
4.4
4.2
4.0
3.8
3.6
PROPAG ATIO N DELAY (ns)
3.4
3.2
3.0
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140
OVERDRIVE (mV)
Figure 12. Propagation Delay vs. Input Overdrive at V
4.0
VCM AT VCC = 2.5V
3.8
3.6
RISE
= 2.5 V
CC
05914-009
1.00V/DIV M4.00ns
Figure 15. 50 MHz Output Waveform V
= 5.5 V
CC
05914-012
3.4
PROPAG ATIO N DELAY (ns)
3.2
3.0
–0.6 0 0.6 1.2 1.8 2.4 3.0
FALL
COMMON-MODE VOLTAGE (V)
Figure 13. Propagation Delay vs. Input Common-Mode Voltage
at V
= 2.5 V
CC
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
PROPAGATI ON DELAY (n s)
3.4
3.2
3.0
2.5 3.0 3.5 4.0 6.05.55. 04.5
Figure 14. Propagation Delay vs. V
RISE
V
FALL
CCO
(V)
CCO
05914-028
500mV/DIV M4.00ns
05914-013
Figure16. 50 MHz Output Waveforms @ 2.5 V
05914-029
Rev. 0 | Page 9 of 16
ADCMP600/ADCMP601/ADCMP602
+IN–
APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP600/ADCMP601/ADCMP602 comparators are very
high speed devices. Despite the low noise output stage, it is essential
to use proper high speed design techniques to achieve the specified
performance. Because comparators are uncompensated amplifiers,
feedback in any phase relationship is likely to cause oscillations or
undesired hysteresis. Of critical importance is the use of low
impedance supply planes, particularly the output supply plane
(V
) and the ground plane (GND). Individual supply planes are
CCO
recommended as part of a multilayer board. Providing the lowest
inductance return path for switching currents ensures the best
possible performance in the target application.
It is also important to adequately bypass the input and output
supplies. Multiple high quality 0.01 μF bypass capacitors should
be placed as close as possible to each of the V
pins and should be connected to the GND plane with redundant
vias. At least one of these should be placed to provide a physically
short return path for output currents flowing back from ground
to the V
pin. High frequency bypass capacitors should be
CC
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should also be strictly controlled to maximize
the effectiveness of the bypass at high frequencies.
If the package allows and the input and output supplies have
been connected separately such that V
CCI
taken to bypass each of these supplies separately to the GND
plane. A bypass capacitor should never be connected between
them. It is recommended that the GND plane separate the V
and V
planes when the circuit board layout is designed to
CCO
minimize coupling between the two supplies and to take
advantage of the additional bypass capacitance from each
respective supply to the ground plane. This enhances the
performance when split input/output supplies are used. If the
input and output supplies are connected together for single-supply
operation such that V
CCI
= V
, coupling between the two supplies
CCO
is unavoidable; however, careful board placement can help keep
output return currents away from the inputs.
TTL-/CMOS-COMPATIBLE OUTPUT STAGE
Specified propagation delay performance can be achieved only
by keeping the capacitive load at or below the specified minimums.
The outputs of the devices are designed to directly drive one
Schottky TTL or three low power Schottky TTL loads or the
equivalent. For large fan outputs, buses, or transmission lines,
use an appropriate buffer to maintain the excellent speed and
stability of the comparator.
With the rated 5 pF load capacitance applied, more than half of
the total device propagation delay is output stage slew time,
even at 2.5 V V
as V
decreases, and instability in the power supply may
CCO
appear as excess delay dispersion.
. Because of this, the total prop delay decreases
CC
≠ V
and V
CCI
CCO
supply
CCO
, care should be
CCI
This delay is measured to the 50% point for the supply in use;
therefore, the fastest times are observed with the V
supply at
CC
2.5 V, and larger values are observed when driving loads that
switch at other levels.
When duty cycle accuracy is critical, the logic being driven
should switch at 50% of V
minimized. When in doubt, it is best to power V
and load capacitance should be
CC
or the
CCO
entire device from the logic supply and rely on the input PSRR
and CMRR to reject noise.
Overdrive and input slew rate dispersions are not significantly
affected by output loading and V
variations.
CC
The TTL-/CMOS-compatible output stage is shown in the
simplified schematic diagram (Figure 17). Because of its
inherent symmetry and generally good behavior, this output
stage is readily adaptable for driving various filters and other
unusual loads.
V
LOGIC
A1
A
V
IN
GAIN STAGE
Figure 17. Simplified Schematic Diagram of
TTL-/CMOS-Compatible Output Stage
A2
OUTPUT STAGE
Q1
Q2
OUTPUT
5914-014
USING/DISABLING THE LATCH FEATURE
The latch input is designed for maximum versatility. It can
safely be left floating for fixed hysteresis or be tied to V
remove the hysteresis, or it can be driven low by any standard
TTL/CMOS device as a high speed latch.
In addition, the pin can be operated as a hysteresis control pin
with a bias voltage of 1.25 V nominal and an input resistance of
approximately 7000 Ω. This allows the comparator hysteresis to
be easily and accurately controlled by either a resistor or an
inexpensive CMOS DAC.
Hysteresis control and latch mode can be used together if an
open drain, an open collector, or a three-state driver is connected
parallel to the hysteresis control resistor or current source.
Due to the programmable hysteresis feature, the logic threshold
of the latch pin is approximately 1.1 V regardless of V
to
CC
.
CC
Rev. 0 | Page 10 of 16
ADCMP600/ADCMP601/ADCMP602
OPTIMIZING PERFORMANCE
As with any high speed comparator, proper design and layout
techniques are essential for obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit performance
and often cause oscillation. Large discontinuities along input
and output transmission lines can also limit the specified pulsewidth dispersion performance. The source impedance should
be minimized as much as is practicable. High source impedance,
in combination with the parasitic input capacitance of the
comparator, causes an undesirable degradation in bandwidth at
the input, thus degrading the overall response. Thermal noise
from large resistances can easily cause extra jitter with slowly
slewing input signals; higher impedances encourage undesired
coupling.
COMPARATOR PROPAGATION DELAY DISPERSION
The ADCMP600/ADCMP601/ADCMP602 comparators are
designed to reduce propagation delay dispersion over a wide
input overdrive range. Propagation delay dispersion is the
variation in propagation delay that results from a change in the
degree of overdrive or slew rate (that is, how far or how fast the
input signal exceeds the switching threshold).
Propagation delay dispersion is a specification that becomes
important in high speed, time-critical applications, such as data
communication, automatic test and measurement, and instrumentation. It is also important in event-driven applications, such
as pulse spectroscopy, nuclear instrumentation, and medical
imaging. Dispersion is defined as the variation in propagation
delay as the input overdrive conditions are changed (Figure 18
and Figure 19).
The device dispersion is typically < 2 ns as the overdrive varies
from 10 mV to 125 mV. This specification applies to both
positive and negative signals because the device has very closely
matched delays both positive-going and negative-going inputs.
500mV OVERDRI VE
INPUT VOLTAGE
10mV OVERDRIVE
V
± V
N
OS
DISPERSION
Q/Q OUTPUT
Figure 18. Propagation Delay—Overdrive Dispersion
05914-015
INPUT VOLTAGE
Q/Q OUTPUT
Figure 19. Propagation Delay—Slew Rate Dispersion
10V/ns
1V/ns
V
± V
N
DISPERSION
OS
05914-016
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in a
noisy environment, or when the differential input amplitudes
are relatively small or slow moving. Figure 20 shows the transfer
function for a comparator with hysteresis. As the input voltage
approaches the threshold (0.0 V, in this example) from below
the threshold region in a positive direction, the comparator
switches from low to high when the input crosses +V
new switching threshold becomes −V
in the high state until the new threshold, −V
/2. The comparator remains
H
H
below the threshold region in a negative direction. In this manner,
noise or feedback output signals centered on 0.0 V input cannot
cause the comparator to switch states unless it exceeds the region
bounded by ±V
/2.
H
OUTPUT
V
OH
V
OL
–V
H
2
Figure 20. Comparator Hysteresis Transfer Function
0
INPUT
+V
H
2
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. One limitation of this approach is that the amount of
hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that reduce high speed performance and induce
oscillation in some cases.
These ADCMP600 features a fixed hysteresis of approximately
2 mV. The ADCMP601 and ADCMP602 comparators offer a
programmable Hysteresis feature that can significantly improve
accuracy and stability. Connecting an external pull-down
resistor or a current source from the LE/HYS pin to GND,
varies the amount of hysteresis in a predictable, stable manner.
/2, and the
H
/2, is crossed from
05914-017
Rev. 0 | Page 11 of 16
ADCMP600/ADCMP601/ADCMP602
Leaving the LE/HYS pin disconnected results in a fixed
hysteresis of 2 mV; driving this pin high removes hysteresis. The
maximum hysteresis that can be applied using this pin is
approximately 160 mV. Figure 21 illustrates the amount of
hysteresis applied as a function of the external resistor value,
and Figure 11 illustrates hysteresis as a function of the current.
The hysteresis control pin appears as a 1.25 V bias voltage seen
through a series resistance of 7 kΩ ± 20% throughout the hysteresis
control range. The advantages of applying hysteresis in this manner
are improved accuracy, improved stability, reduced component
count, and maximum versatility. An external bypass capacitor is
not recommended on the HYS pin because it impairs the latch
function and often degrades the jitter performance of the device.
As described in the Using/Disabling the Latch Feature section,
hysteresis control need not compromise the latch function.
CROSSOVER BIAS POINT
In both op amps and comparators, rail-to-rail inputs of this type
have a dual front-end design. Certain devices are active near the
V
rail and others are active near the VEE rail. At some predeter-
CC
mined point in the common-mode range, a crossover occurs. At
this point, normally V
and the measured offset voltages and currents change.
The ADCMP600/ADCMP601/ADCMP602 comparators
slightly elaborate on this scheme. Crossover points can be found
at approximately 0.8 V and 1.6 V.
/2, the direction of the bias current reverses
CC
250
200
VCC= 5.5V
150
100
HYSTERESIS (mV)
50
= 2.5V
V
CC
0
50 150 250 450350 550 650
Figure 21. Hysteresis vs. R
HYSTERESIS RESISTOR (kΩ)
Control Resistor
HYS
05914-030
MINIMUM INPUT SLEW RATE REQUIREMENT
With the rated load capacitance and normal good PC Board
design practice, as discussed in the Optimizing Performance
section, these comparators should be stable at any input slew
rate with no hysteresis. Broadband noise from the input stage is
observed in place of the violent chattering seen with most other
high speed comparators. With additional capacitive loading or
poor bypassing, oscillation is observed. This oscillation is due to
the high gain bandwidth of the comparator in combination with
feedback parasitics in the package and PC board. In many
applications, chattering is not harmful.
Rev. 0 | Page 12 of 16
ADCMP600/ADCMP601/ADCMP602
V
V
±
V
V
V
TYPICAL APPLICATION CIRCUITS
5
0.1µF
2kΩ
2kΩ
ADCMP600
0.1µF
Figure 22. Self-Biased, 50% Slicer
100Ω
ADCMP600
Figure 23. LVDS-to-CMOS Receiver
2.5
OUTPUT
CMOS
V
DD
2.5V TO 5V
CMOS
2.5
05914-019
ADCMP600
INPUT
1.25V
50m
INPUT
1.25V
REF
10kΩ
10kΩ
CMOS
PWM
OUTPUT
ADCMP601
10kΩ
05914-020
82pF
LE/HYS
40kΩ
05914-022
Figure 25. Oscillator and Pulse-Width Modulator
2.5V TO 5
CONTROL
VOLTAGE
0V TO 2. 5V
20kΩ
20kΩ
82pF
10kΩ
ADCMP601
LE/HYS
OUTPUT
1.5MHz TO 30MHz
100kΩ100kΩ
05914-021
DIGITAL
INPUT
HYSTERESIS
CURRENT
74 AHC
1G07
10kΩ
ADCMP601
Figure 24. Voltage-Controlled Oscillator Figure 26. Hysteresis Adjustment with Latch
LE/HYS
5914-023
Rev. 0 | Page 13 of 16
ADCMP600/ADCMP601/ADCMP602
OUTLINE DIMENSIONS
2.20
2.00
1.80
1.35
1.25
1.15
1.00
0.90
0.70
0
.
1
0
M
123
PIN 1
A
X
0.10 COPLANARITY
0.30
0.15
COMPLIANT TO JEDEC STANDARDS MO-203-AA
Figure 27. 5-Lead Thin Shrink Small Outline Transistor Package (SC70)
Dimensions shown in millimeters
2.90 BSC
5
1.60 BSC
123
PIN 1
1.30
1.15
0.90
0.15 MAX
1.90
BSC
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 28. 5-Lead Small Outline Transistor Package (SOT-23)
Dimensions shown in millimeters
45
0.65 BSC
4
0.50
0.30
2.40
2.10
1.80
1.10
0.80
SEATING
PLANE
(KS-5)
2.80 BSC
0.95 BSC
1.45 MAX
SEATING
PLANE
(RJ-5)
0.40
0.10
0.22
0.08
0.22
0.08
10°
5°
0°
0.46
0.36
0.26
0.60
0.45
0.30
2.20
2.00
1.80
2.40
0.30
0.15
4 5 6
3 2 1
0.65 BSC
2.10
1.80
1.10
0.80
SEATING
PLANE
0.40
0.10
0.22
0.08
0.46
0.36
0.26
1.35
1.25
1.15
PIN 1
1.30 BSC
1.00
0.90
0.70
0.10 MAX
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 29. 6-Lead Thin Shrink Small Outline Transistor Package (SC70)
(KS-6)
Dimensions shown in millimeters
3.20
3.00
2.80
8
5
4
SEATING
PLANE
5.15
4.90
4.65
1.10 MAX
0.23
0.08
8°
0°
0.80
0.60
0.40
3.20
3.00
1
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
0.15
0.38
0.00
0.22
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 30. 8-Lead Mini Small Outline Package (MSOP)
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
ADCMP600BRJZ-R2
ADCMP600BRJZ-RL1 −40°C to +125°C 5-Lead SOT23 RJ-5 G0C
ADCMP600BRJZ-REEL71 −40°C to +125°C 5-Lead SOT23 RJ-5 G0C
ADCMP600BKSZ-R21 −40°C to +125°C 5-Lead SC70 KS-5 G0C
ADCMP600BKSZ-RL1 −40°C to +125°C 5-Lead SC70 KS-6 G0C
ADCMP600BKSZ-REEL71 −40°C to +125°C 5-Lead SC70 KS-6 G0C
ADCMP601BKSZ-R21 −40°C to +125°C 6-Lead SC70 KS-6 G0N
ADCMP601BKSZ-RL1 −40°C to +125°C 6-Lead SC70 KS-6 G0N
ADCMP601BKSZ-REEL71 −40°C to +125°C 6-Lead SC70 KS-6 G0N
ADCMP602BRMZ1 −40°C to +125°C 8-Lead MSOP RM-8 GF
ADCMP602BRMZ-REEL1 −40°C to +125°C 8-Lead MSOP RM-8 GF
ADCMP602BRMZ-REEL71 −40°C to +125°C 8-Lead MSOP RM-8 GF
1
Z = Pb-free part.
1
−40°C to +125°C 5-Lead SOT23 RJ-5 G0C
Rev. 0 | Page 14 of 16
ADCMP600/ADCMP601/ADCMP602
NOTES
Rev. 0 | Page 15 of 16
ADCMP600/ADCMP601/ADCMP602
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05914-0-10/06(0)
Rev. 0 | Page 16 of 16
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