ANALOG DEVICES ADCMP580, ADCMP581, ADCMP582 Service Manual

Ultrafast SiGe

V

V

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FEATURES

180 ps propagation delay
25 ps overdrive and slew rate dispersion
8 GHz equivalent input rise time bandwidth
100 ps minimum pulse width
37 ps typical output rise/fall
10 ps deterministic jitter (DJ)
200 fs random jitter (RJ)

−2 V to +3 V input range with +5 V/−5 V supplies
On-chip terminations at both input pins
Resistor-programmable hysteresis
Differential latch control
Power supply rejection > 70 dB

APPLICATIONS

Automatic test equipment (ATE)
High speed instrumentation
Pulse spectroscopy
Medical imaging and diagnostics
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Clock and data signal restoration

Voltage Comparators

ADCMP580/ADCMP581/ADCMP582

FUNCTIONAL BLOCK DIAGRAM

CCI

V

TERMINATION

TP

NONINVERTI NG

P

V

N

VTN TERMINATION

INVERTING

INPUT

INPUT

ADCMP580/
ADCMP581/

ADCMP582

V

EE

Figure 1.

CML/ECL/
PECL

LE INPUT

LE INPUTHYS

V

CCO

Q OUTPUT

Q OUTPUT

V

EE

04672-001

GENERAL DESCRIPTION

The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage
comparators fabricated on the Analog Devices, Inc. proprietary
XFCB3 Silicon Germanium (SiGe) bipolar process. The
ADCMP580 features CML output drivers, the ADCMP581
features reduced swing ECL (negative ECL) output drivers, and
the ADCMP582 features reduced swing PECL (positive ECL)
output drivers.

All three comparators offer 180 ps propagation delay and 100 ps

um pulse width for 10 Gbps operation with 200 fs random

minim
jitter (RJ). Overdrive and slew rate dispersion are typically less
than 15 ps.

The ±5 V power supplies enable a wide −2 V to +3 V input
ra

nge with logic levels referenced to the CML/NECL/PECL
outputs. The inputs have 50 Ω on-chip termination resistors
with the optional capability to be left open (on an individual
pin basis) for applications requiring high impedance input.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

The CML output stage is designed to directly drive 400 mV into
50

Ω transmission lines terminated to ground. The NECL output
stages are designed to directly drive 400 mV into 50 Ω terminated
to −2 V. The PECL output stages are designed to directly drive
400 mV into 50 Ω terminated to V

− 2 V. High speed latch

CCO

and programmable hysteresis are also provided. The differential
latch input controls are also 50 Ω terminated to an independent
V

pin to interface to either CML or ECL or to PECL logic.

TT

The ADCMP580/ADCMP581/ADCMP582 are available in a
16-lead LFCS

P_VQ.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005–2007 Analog Devices, Inc. All rights reserved.

ADCMP580/ADCMP581/ADCMP582

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Information ......................................................................... 5

Absolute Maximum Ratings............................................................ 6

Thermal Considerations.............................................................. 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

REVISION HISTORY

8/07—Rev. 0 to Rev. A

Changes to Figure 1.......................................................................... 1

Changes to Table 4............................................................................ 7

Changes to Figure 9.......................................................................... 8

Changes to Figure 21, Figure 22, and Figure 23 ......................... 10

Changes to Using/Disabling the Latch Feature.......................... 11

Changes to Comparator Hysteresis Section and Figure 29....... 13

Changes to Ordering Guide.......................................................... 14

7/05—Revision 0: Initial Version

Typical Applicat i o n C i rc uits ......................................................... 10

Application Information................................................................ 11

Power/Ground Layout and Bypassing..................................... 11

ADCMP58x Family of Output Stages ..................................... 11

Using/Disabling the Latch Feature........................................... 11

Optimizing High Speed Performance ..................................... 12

Comparator Propagation Delay Dispersion............................... 12

Comparator Hysteresis .............................................................. 13

Minimum Input Slew Rate Requirement ................................ 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. A | Page 2 of 16

ADCMP580/ADCMP581/ADCMP582

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SPECIFICATIONS

V

= 5.0 V; VEE = −5.0 V; V

CCI

Table 1.

Parameter Symbol Condition Min Typ Max Unit

DC INPUT CHARACTERISTICS

Input Voltage Range VP, V
Input Differential Range −2.0 +2.0 V
Input Offset Voltage V
Offset Voltage Temperature Coefficient ΔVOS/d
Input Bias Current IP, I
Input Bias Current Temperature Coefficient ΔIB/d
Input Offset Current +2 ±5.0 μA
Input Resistance 47 to 53 Ω
Input Resistance, Differential Mode Open termination 50 kΩ
Input Resistance, Common Mode Open termination 500 kΩ
Active Gain A
Common-Mode Rejection Ratio CMRR VCM = −2.0 V to +3.0 V 60 dB
Hysteresis R

LATCH ENABLE CHARACTERISTICS

Latch Enable Input Impedance Z
Latch-to-Output Delay t
Latch Minimum Pulse Width t

ADCMP580 (CML)

Latch Enable Input Range −0.8 0 V
Latch Enable Input Differential 0.2 0.4 0.5 V
Latch Setup Time t
Latch Hold Time t

ADCMP581 (NECL)

Latch Enable Input Range −1.8 +0.8 V
Latch Enable Input Differential 0.2 0.4 0.5 V
Latch Setup Time t
Latch Hold Time t

ADCMP582 (PECL)

Latch Enable Input Range V
Latch Enable Input Differential 0.2 0.4 0.5 V
Latch Setup Time t
Latch Hold Time t

DC OUTPUT CHARACTERISTICS

ADCMP580 (CML)

Output Impedance Z
Output Voltage High Level V
Output Voltage Low Level V
Output Voltage Differential 50 Ω to GND 340 395 450 mV

ADCMP581 (NECL)

Output Voltage High Level V

Output Voltage High Level V

Output Voltage High Level V

Output Voltage Low Level V

Output Voltage Low Level V

Output Voltage Low Level V

Output Voltage Differential 50 Ω to −2.0 V 340 395 450 mV

= 3.3 V; TA = 25°C, unless otherwise noted.

CCO

−2.0 +3.0 V

N

OS

N

V

IN

PLOH

PL

S

H

S

H

S

H

OUT

OH

OL

OH

OH

OH

OL

OL

OL

−10.0 ±4 +10.0 mV
10 μV/°C

T

Open termination 15 30.0 μA
50 nA/°C

T

48 dB

= ∞ 1 mV

HYS

Each pin, VTT at ac ground 47 to 53 Ω

, t

PLOLVOD

= 200 mV 175 ps

VOD = 200 mV 100 ps

VOD = 200 mV 95 ps
VOD = 200 mV −90 ps

VOD = 200 mV 70 ps
VOD = 200 mV −65 ps

VOD = 200 mV 30 ps
VOD = 200 mV −25 ps

50 Ω
50 Ω to GND −0.10 0 +0.03 V
50 Ω to GND −0.50 −0.40 −0.35 V

50 Ω to −2 V, TA = 125°C −0.99 −0.87 −0.75 V
50 Ω to −2 V, TA = 25°C −1.06 −0.94 −0.82 V
50 Ω to −2 V, TA = −55°C −1.11 −0.99 −0.87 V
50 Ω to −2 V, TA = 125°C −1.43 −1.26 −1.13 V
50 Ω to −2 V, TA = 25°C −1.50 −1.33 −1.20 V
50 Ω to −2 V, TA = −55°C −1.55 −1.38 −1.25 V

− 1.8 V

CCO

− 0.8 V

CCO

Rev. A | Page 3 of 16

ADCMP580/ADCMP581/ADCMP582

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Parameter Symbol Condition Min Typ Max Unit

ADCMP582 (PECL) V

Output Voltage High Level V
Output Voltage High Level V
Output Voltage High Level V
Output Voltage Low Level V
Output Voltage Low Level V
Output Voltage Low Level V

OH

OH

OH

OL

OL

OL

Output Voltage Differential 50 Ω to V

AC PERFORMANCE

Propagation Delay t
Propagation Delay Temperature Coefficient ΔtPD/d
Propagation Delay Skew—Rising

PD

T

V

Transition to Falling Transition

Overdrive Dispersion 50 mV < VOD < 1.0 V 10 ps

10 mV < VOD < 200 mV 15 ps
Slew Rate Dispersion 2 V/ns to 10 V/ns 15 ps
Pulse Width Dispersion 100 ps to 5 ns 15 ps
Duty Cycle Dispersion 5% to 95% 1.0 V/ns, 15 MHz, VCM = 0.0 V 10 ps
Common-Mode Dispersion VOD = 0.2 V, −2 V < VCM < 3 V 5 ps/V
Equivalent Input Bandwidth

1

BW

EQ

Toggle Rate >50% output swing 12.5 Gbps
Deterministic Jitter DJ

Deterministic Jitter DJ

RMS Random Jitter RJ VOD = 200 mV, 5 V/ns, 1.25 GHz 0.2 ps
Minimum Pulse Width PW
Minimum Pulse Width PW
Rise/Fall Time tR, t

MIN

MIN

F

POWER SUPPLY

Positive Supply Voltage V
Negative Supply Voltage V

CCI

EE

ADCMP580 (CML)

Positive Supply Current I
Negative Supply Current I
Power Dissipation P

VCCI

VEE

D

ADCMP581 (NECL)

Positive Supply Current I
Negative Supply Current I
Power Dissipation P

VCCI

VEE

D

ADCMP582 (PECL)
Logic Supply Voltage V

Input Supply Current I
Output Supply Current I
Negative Supply Current I
Power Dissipation P
Power Supply Rejection (V

) PSR

CCI

Power Supply Rejection (VEE) PSR
Power Supply Rejection (V

1

Equivalent input bandwidth assumes a simple first-order input response and is calculated with the following formula: BWEQ = 0.22/(tr

transition time of a quasi-Gaussian input edge applied to the comparator input and tr

) PSR

CCO

CCO

VCCI

VCCO

VEE

D

VCCI

VEE

VCCO

= 3.3 V

CCO

50 Ω to V
50 Ω to V
50 Ω to V
50 Ω to V
50 Ω to V
50 Ω to V

− 2 V, TA = 125°C V

CCO

− 2 V, TA = 25°C V

CCO

− 2 V, TA = −55°C V

CCO

− 2 V, TA = 125°C V

CCO

− 2 V, TA = 25°C V

CCO

− 2 V, TA = −55°C V

CCO

− 2.0 V 340 395 450 mV

CCO

− 0.99 V

CCO

− 1.06 V

CCO

− 1.11 V

CCO

− 1.43 V

CCO

− 1.50 V

CCO

− 1.55 V

CCO

− 0.87 V

CCO

− 0.94 V

CCO

− 0.99 V

CCO

− 1.26 V

CCO

− 1.33 V

CCO

− 1.35 V

CCO

− 0.75 V

CCO

− 0.82 V

CCO

− 0.87 V

CCO

− 1.13 V

CCO

− 1.20 V

CCO

− 1.25 V

CCO

VOD = 500 mV 180 ps

0.25 ps/°C
= 500 mV, 5 V/ns 10 ps

OD

0.0 V to 400 mV input,

= tF = 25 ps, 20/80

t

R

= 500 mV, 5 V/ns,

V

OD

31

− 1 NRZ, 5 Gbps

PRBS

= 200 mV, 5 V/ns,

V

OD

31

− 1 NRZ, 10 Gbps

PRBS

8 GHz

15 ps

25 ps

ΔtPD < 5 ps 100 ps
ΔtPD < 10 ps 80 ps
20/80 37 ps

+4.5 +5.0 +5.5 V

−5.5 −5.0 −4.5 V

V

= 5.0 V, 50 Ω to GND 6 8 mA

CCI

VEE = −5.0 V, 50 Ω to GND −50 −40 −34 mA
50 Ω to GND 230 260 mW

V

= 5.0 V, 50 Ω to −2 V 6 8 mA

CCI

VEE = −5.0 V, 50 Ω to −2 V −35 −25 −19 mA
50 Ω to −2 V 155 200 mW

+2.5 +3.3 +5.0 V
V

= 5.0 V, 50 Ω to V

CCI

V

= 5.0 V, 50 Ω to V

CCO

VEE = −5.0 V, 50 Ω to V
50 Ω to V
V

= 5.0 V + 5% −75 dB

CCI

− 2 V 310 350 mW

CCO

− 2 V 6 8 mA

CCO

− 2 V 44 55 mA

CCO

− 2 V −35 −25 −19 mA

CCO

VEE = −5.0 V + 5% −60 dB
V

= 3.3 V + 5% (ADCMP582) −75 dB

CCO

2

2

– tr

is the effective transition time digitized by the comparator.

COMP

COMP

), where trIN is the 20/80

IN

Rev. A | Page 4 of 16

ADCMP580/ADCMP581/ADCMP582

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TIMING INFORMATION

Figure 2 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 2 provides the definitions of the
terms shown in Figure 2.

LATCH ENABLE

50%

LATCH ENABLE

t

S

t

H

V

DIFFERENTIAL

INPUT VOLTAGE

Q OUTPUT

Q OUTPUT

N

V

OD

t

PDL

t

PDH

Figure 2. Comparator Timing Diagram

Table 2. Timing Descriptions

Symbol Timing Description

t

PDH

Input-to-Output High Delay

Propagation delay measured from the time the i
(± the input offset voltage) to the 50% point of an output low-to-high transition.

t

PDL

Input-to-Output Low Delay

Propagation delay measured from the time the i
(± the input offset voltage) to the 50% point of an output high-to-low transition.

t

PLOH

Latch Enable-to-Output High Delay

Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the

t

t

PLOL

H

Latch Enable-to-Output Low Delay

Minimum Hold Time

Propagation delay measured from the 50% point of the latch enable signal low-to-high

ansition to the 50% point of an output high-to-low transition.

tr
Minimum time after the negative transition of the la

signal must remain unchanged to be acquired and held at the outputs.

t

PL

t

S

Minimum Latch Enable Pulse Width Minimum time that the latch enable signal must be high to acquire an input signal change.
Minimum Setup Time

Minimum time before the negative transition of
signal change must be present to be acquired and held at the outputs.

t

R

Output Rise Time

Amount of time required to transition from a
20% and 80% points.

t

F

Output Fall Time

Amount of time required to transition from a high to a low output as measured at the
20% and 80% p

V

N

V

OD

Normal Input Voltage Difference between the input voltages VP and VN for output true.
Voltage Overdrive Difference between the input voltages VP and VN for output false.

t

PL

V

± V

N

t

PLOH

50%

t

F

50%

t

PLOL

t

R

nput signal crosses the reference

nput signal crosses the reference

50% point of an output low-to-high transition.

tch enable signal that the input

the latch enable signal that an input

low to a high output as measured at the

oints.

OS

04672-028

Rev. A | Page 5 of 16