ANALOG DEVICES ADCMP580, ADCMP581, ADCMP582 Service Manual

Ultrafast SiGe

V

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FEATURES

180 ps propagation delay 25 ps overdrive and slew rate dispersion 8 GHz equivalent input rise time bandwidth 100 ps minimum pulse width 37 ps typical output rise/fall 10 ps deterministic jitter (DJ) 200 fs random jitter (RJ)

−2 V to +3 V input range with +5 V/−5 V supplies On-chip terminations at both input pins Resistor-programmable hysteresis Differential latch control Power supply rejection > 70 dB

APPLICATIONS

Automatic test equipment (ATE) High speed instrumentation Pulse spectroscopy Medical imaging and diagnostics High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Clock and data signal restoration

Voltage Comparators

ADCMP580/ADCMP581/ADCMP582

FUNCTIONAL BLOCK DIAGRAM

CCI

V

TERMINATION

TP

NONINVERTI NG

P

V

N

VTN TERMINATION

INVERTING

INPUT

ADCMP580/ ADCMP581/

ADCMP582

V

EE

Figure 1.

CML/ECL/ PECL

LE INPUT

LE INPUTHYS

V

CCO

Q OUTPUT

V

EE

04672-001

GENERAL DESCRIPTION

The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage comparators fabricated on the Analog Devices, Inc. proprietary XFCB3 Silicon Germanium (SiGe) bipolar process. The ADCMP580 features CML output drivers, the ADCMP581 features reduced swing ECL (negative ECL) output drivers, and the ADCMP582 features reduced swing PECL (positive ECL) output drivers.

All three comparators offer 180 ps propagation delay and 100 ps

um pulse width for 10 Gbps operation with 200 fs random

minim jitter (RJ). Overdrive and slew rate dispersion are typically less than 15 ps.

The ±5 V power supplies enable a wide −2 V to +3 V input ra

nge with logic levels referenced to the CML/NECL/PECL outputs. The inputs have 50 Ω on-chip termination resistors with the optional capability to be left open (on an individual pin basis) for applications requiring high impedance input.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

The CML output stage is designed to directly drive 400 mV into 50

Ω transmission lines terminated to ground. The NECL output stages are designed to directly drive 400 mV into 50 Ω terminated to −2 V. The PECL output stages are designed to directly drive 400 mV into 50 Ω terminated to V

− 2 V. High speed latch

CCO

and programmable hysteresis are also provided. The differential latch input controls are also 50 Ω terminated to an independent V

pin to interface to either CML or ECL or to PECL logic.

TT

The ADCMP580/ADCMP581/ADCMP582 are available in a 16-lead LFCS

P_VQ.

ADCMP580/ADCMP581/ADCMP582

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REVISION HISTORY

8/07—Rev. 0 to Rev. A

Changes to Figure 1.......................................................................... 1

Changes to Table 4............................................................................ 7

Changes to Figure 9.......................................................................... 8

Changes to Figure 21, Figure 22, and Figure 23 ......................... 10

Changes to Using/Disabling the Latch Feature.......................... 11

Changes to Comparator Hysteresis Section and Figure 29....... 13

Changes to Ordering Guide.......................................................... 14

7/05—Revision 0: Initial Version

Typical Applicat i o n C i rc uits ......................................................... 10

Application Information................................................................ 11

Power/Ground Layout and Bypassing..................................... 11

ADCMP58x Family of Output Stages ..................................... 11

Using/Disabling the Latch Feature........................................... 11

Optimizing High Speed Performance ..................................... 12

Comparator Propagation Delay Dispersion............................... 12

Comparator Hysteresis .............................................................. 13

Minimum Input Slew Rate Requirement ................................ 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. A | Page 2 of 16

ADCMP580/ADCMP581/ADCMP582

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SPECIFICATIONS

V

= 5.0 V; VEE = −5.0 V; V

CCI

Table 1.

Parameter Symbol Condition Min Typ Max Unit

DC INPUT CHARACTERISTICS

Input Voltage Range VP, V Input Differential Range −2.0 +2.0 V Input Offset Voltage V Offset Voltage Temperature Coefficient ΔVOS/d Input Bias Current IP, I Input Bias Current Temperature Coefficient ΔIB/d Input Offset Current +2 ±5.0 μA Input Resistance 47 to 53 Ω Input Resistance, Differential Mode Open termination 50 kΩ Input Resistance, Common Mode Open termination 500 kΩ Active Gain A Common-Mode Rejection Ratio CMRR VCM = −2.0 V to +3.0 V 60 dB Hysteresis R

LATCH ENABLE CHARACTERISTICS

Latch Enable Input Impedance Z Latch-to-Output Delay t Latch Minimum Pulse Width t

ADCMP580 (CML)

Latch Enable Input Range −0.8 0 V Latch Enable Input Differential 0.2 0.4 0.5 V Latch Setup Time t Latch Hold Time t

ADCMP581 (NECL)

Latch Enable Input Range −1.8 +0.8 V Latch Enable Input Differential 0.2 0.4 0.5 V Latch Setup Time t Latch Hold Time t

ADCMP582 (PECL)

Latch Enable Input Range V Latch Enable Input Differential 0.2 0.4 0.5 V Latch Setup Time t Latch Hold Time t

DC OUTPUT CHARACTERISTICS

ADCMP580 (CML)

Output Impedance Z Output Voltage High Level V Output Voltage Low Level V Output Voltage Differential 50 Ω to GND 340 395 450 mV

ADCMP581 (NECL)

Output Voltage High Level V

Output Voltage Low Level V

Output Voltage Differential 50 Ω to −2.0 V 340 395 450 mV

= 3.3 V; TA = 25°C, unless otherwise noted.

CCO

−2.0 +3.0 V

N

OS

N

V

IN

PLOH

PL

S

H

S

H

S

H

OUT

OH

OL

OH

OL

−10.0 ±4 +10.0 mV 10 μV/°C

T

Open termination 15 30.0 μA 50 nA/°C

T

48 dB

= ∞ 1 mV

HYS

Each pin, VTT at ac ground 47 to 53 Ω

, t

PLOLVOD

= 200 mV 175 ps

VOD = 200 mV 100 ps

VOD = 200 mV 95 ps VOD = 200 mV −90 ps

VOD = 200 mV 70 ps VOD = 200 mV −65 ps

VOD = 200 mV 30 ps VOD = 200 mV −25 ps

50 Ω 50 Ω to GND −0.10 0 +0.03 V 50 Ω to GND −0.50 −0.40 −0.35 V

50 Ω to −2 V, TA = 125°C −0.99 −0.87 −0.75 V 50 Ω to −2 V, TA = 25°C −1.06 −0.94 −0.82 V 50 Ω to −2 V, TA = −55°C −1.11 −0.99 −0.87 V 50 Ω to −2 V, TA = 125°C −1.43 −1.26 −1.13 V 50 Ω to −2 V, TA = 25°C −1.50 −1.33 −1.20 V 50 Ω to −2 V, TA = −55°C −1.55 −1.38 −1.25 V

− 1.8 V

CCO

− 0.8 V

CCO

Rev. A | Page 3 of 16

ADCMP580/ADCMP581/ADCMP582

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Parameter Symbol Condition Min Typ Max Unit

ADCMP582 (PECL) V

Output Voltage High Level V Output Voltage High Level V Output Voltage High Level V Output Voltage Low Level V Output Voltage Low Level V Output Voltage Low Level V

OH

OL

Output Voltage Differential 50 Ω to V

AC PERFORMANCE

Propagation Delay t Propagation Delay Temperature Coefficient ΔtPD/d Propagation Delay Skew—Rising

PD

T

V

Transition to Falling Transition

Overdrive Dispersion 50 mV < VOD < 1.0 V 10 ps

10 mV < VOD < 200 mV 15 ps Slew Rate Dispersion 2 V/ns to 10 V/ns 15 ps Pulse Width Dispersion 100 ps to 5 ns 15 ps Duty Cycle Dispersion 5% to 95% 1.0 V/ns, 15 MHz, VCM = 0.0 V 10 ps Common-Mode Dispersion VOD = 0.2 V, −2 V < VCM < 3 V 5 ps/V Equivalent Input Bandwidth

1

BW

EQ

Toggle Rate >50% output swing 12.5 Gbps Deterministic Jitter DJ

Deterministic Jitter DJ

RMS Random Jitter RJ VOD = 200 mV, 5 V/ns, 1.25 GHz 0.2 ps Minimum Pulse Width PW Minimum Pulse Width PW Rise/Fall Time tR, t

MIN

F

POWER SUPPLY

Positive Supply Voltage V Negative Supply Voltage V

CCI

EE

ADCMP580 (CML)

Positive Supply Current I Negative Supply Current I Power Dissipation P

VCCI

VEE

D

ADCMP581 (NECL)

Positive Supply Current I Negative Supply Current I Power Dissipation P

VCCI

VEE

D

ADCMP582 (PECL) Logic Supply Voltage V

Input Supply Current I Output Supply Current I Negative Supply Current I Power Dissipation P Power Supply Rejection (V

) PSR

CCI

Power Supply Rejection (VEE) PSR Power Supply Rejection (V

1

Equivalent input bandwidth assumes a simple first-order input response and is calculated with the following formula: BWEQ = 0.22/(tr

transition time of a quasi-Gaussian input edge applied to the comparator input and tr

) PSR

CCO

VCCI

VCCO

VEE

D

VCCI

VEE

VCCO

= 3.3 V

CCO

50 Ω to V 50 Ω to V 50 Ω to V 50 Ω to V 50 Ω to V 50 Ω to V

− 2 V, TA = 125°C V

CCO

− 2 V, TA = 25°C V

CCO

− 2 V, TA = −55°C V

CCO

− 2 V, TA = 125°C V

CCO

− 2 V, TA = 25°C V

CCO

− 2 V, TA = −55°C V

CCO

− 2.0 V 340 395 450 mV

CCO

− 0.99 V

CCO

− 1.06 V

CCO

− 1.11 V

CCO

− 1.43 V

CCO

− 1.50 V

CCO

− 1.55 V

CCO

− 0.87 V

CCO

− 0.94 V

CCO

− 0.99 V

CCO

− 1.26 V

CCO

− 1.33 V

CCO

− 1.35 V

CCO

− 0.75 V

CCO

− 0.82 V

CCO

− 0.87 V

CCO

− 1.13 V

CCO

− 1.20 V

CCO

− 1.25 V

CCO

VOD = 500 mV 180 ps

0.25 ps/°C = 500 mV, 5 V/ns 10 ps

OD

0.0 V to 400 mV input,

= tF = 25 ps, 20/80

t

R

= 500 mV, 5 V/ns,

V

OD

31

− 1 NRZ, 5 Gbps

PRBS

= 200 mV, 5 V/ns,

V

OD

31

− 1 NRZ, 10 Gbps

PRBS

8 GHz

15 ps

25 ps

ΔtPD < 5 ps 100 ps ΔtPD < 10 ps 80 ps 20/80 37 ps

+4.5 +5.0 +5.5 V

−5.5 −5.0 −4.5 V

V

= 5.0 V, 50 Ω to GND 6 8 mA

CCI

VEE = −5.0 V, 50 Ω to GND −50 −40 −34 mA 50 Ω to GND 230 260 mW

V

= 5.0 V, 50 Ω to −2 V 6 8 mA

CCI

VEE = −5.0 V, 50 Ω to −2 V −35 −25 −19 mA 50 Ω to −2 V 155 200 mW

+2.5 +3.3 +5.0 V V

= 5.0 V, 50 Ω to V

CCI

V

= 5.0 V, 50 Ω to V

CCO

VEE = −5.0 V, 50 Ω to V 50 Ω to V V

= 5.0 V + 5% −75 dB

CCI

− 2 V 310 350 mW

CCO

− 2 V 6 8 mA

CCO

− 2 V 44 55 mA

CCO

− 2 V −35 −25 −19 mA

CCO

VEE = −5.0 V + 5% −60 dB V

= 3.3 V + 5% (ADCMP582) −75 dB

CCO

2

– tr

is the effective transition time digitized by the comparator.

COMP

), where trIN is the 20/80

IN

Rev. A | Page 4 of 16

ADCMP580/ADCMP581/ADCMP582

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TIMING INFORMATION

Figure 2 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 2 provides the definitions of the terms shown in Figure 2.

LATCH ENABLE

50%

LATCH ENABLE

t

S

t

H

V

DIFFERENTIAL

INPUT VOLTAGE

Q OUTPUT

N

V

OD

t

PDL

t

PDH

Figure 2. Comparator Timing Diagram

Table 2. Timing Descriptions

Symbol Timing Description

t

PDH

Input-to-Output High Delay

Propagation delay measured from the time the i (± the input offset voltage) to the 50% point of an output low-to-high transition.

t

PDL

Input-to-Output Low Delay

Propagation delay measured from the time the i (± the input offset voltage) to the 50% point of an output high-to-low transition.

t

PLOH

Latch Enable-to-Output High Delay

Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the

t

PLOL

H

Latch Enable-to-Output Low Delay

Minimum Hold Time

Propagation delay measured from the 50% point of the latch enable signal low-to-high

ansition to the 50% point of an output high-to-low transition.

tr Minimum time after the negative transition of the la

signal must remain unchanged to be acquired and held at the outputs.

t

PL

t

S

Minimum Latch Enable Pulse Width Minimum time that the latch enable signal must be high to acquire an input signal change. Minimum Setup Time

Minimum time before the negative transition of signal change must be present to be acquired and held at the outputs.

t

R

Output Rise Time

Amount of time required to transition from a 20% and 80% points.

t

F

Output Fall Time

Amount of time required to transition from a high to a low output as measured at the 20% and 80% p

V

N

V

OD

Normal Input Voltage Difference between the input voltages VP and VN for output true. Voltage Overdrive Difference between the input voltages VP and VN for output false.

t

PL

V

± V

N

t

PLOH

50%

t

F

50%

t

PLOL

t

R

nput signal crosses the reference

50% point of an output low-to-high transition.

tch enable signal that the input

the latch enable signal that an input

low to a high output as measured at the

oints.

OS

04672-028

Rev. A | Page 5 of 16

ADCMP580/ADCMP581/ADCMP582

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ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

SUPPLY VOLTAGES

Positive Supply Voltage (V Negative Supply Voltage (VEE to GND) –6.0 V to +0.5 V Logic Supply Voltage (V

INPUT VOLTAGES

Input Voltage −3.0 V to +4.0 V Differential Input Voltage −2 V to +2 V Input Voltage, Latch Enable −2.5 V to +5.5 V

HYSTERESIS CONTROL PIN

Applied Voltage (HYS to VEE) −5.5 V to +0.5 V Maximum Input/Output Current 1 mA

OUTPUT CURRENT

ADCMP580 (CML) −25 mA ADCMP581 (NECL) −40 mA ADCMP582 (PECL) −40 mA

TEMPERATURE

Operating Temperature Range, Ambient −40°C to +125°C Operating Temperature, Junction 125°C Storage Temperature Range −65°C to +150°C

to GND) −0.5 V to +6.0 V

CCI

to GND) −0.5 V to +6.0 V

CCO

Stresses above those listed under Absolute Maximum Ratings ma

y cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CONSIDERATIONS

The ADCMP580/ADCMP581/ADCMP582 16-lead LFCSP option has a θ 70°C/W in still air.

(junction-to-ambient thermal resistance) of

JA

ESD CAUTION

Rev. A | Page 6 of 16

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

I CC

EE

GND

HYS

V

14

13

15

16

PIN 1

TP

P

N

TN

1V

2V

ADCMP580

3V

4V

(Not to Scale)

INDICATOR

TOP VIEW

5

6

I

LE

CC

12 GND

11 Q

10

Q

9GND

8

7

E

TT

L

V

4672-003

Figure 3. ADCMP580 Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 V 2 V 3 V 4 V 5, 16 V 6

TP

P

N

TN

CCI

LE

Termination Resistor Return Pin for VP Input. Noninverting Analog Input. Inverting Analog Input. Termination Resistor Return Pin for VN Input. Positive Supply Voltage. Latch Enable Input Pin, Inverting Side. In compare mode (LE = low), the output tracks changes at the input of

the comparator. In latch mode (LE

placed into latch mode. LE must be driven in complement with LE.

7 LE

Latch Enable Input Pin, Noninverting Side. In compare mode (LE = input of the comparator. In latch mode (LE = low), the output reflects the input state just prior to the comparator being placed into latch mode. LE must be driven in complement with LE

8 V

TT

Termination Return Pin for the LE/LE Input Pins. For the ADCMP580 (CML output stage), this pin should be c For the ADCMP581 (ECL output stage), this pin should be c For the ADCMP582 (PECL output stage), this pin should be connected to the V

9, 12 GND/V

CCO

Digital Ground Pin/Positive Logic Power Supply Terminal. For the ADCMP580/ADCMP581, this pin should be connected to the GND pin. For the ADCMP582, this pin should be connected to the positive logic power V

10

Q

Inverting Output. Q is logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, V (Pin 6 to Pin 7) for more information.

11 Q

Noninverting Output. Q is logic high if the analog v analog voltage at the inverting input, V descriptions (Pin 6 to Pin 7) for more information.

13 V

EE

14 HYS

Negative Power Supply. Hysteresis Control. Leave this pin disconnected for zero hysteresis. Connect this pin to the V

suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 9 for proper sizing of the HYS h

ysteresis control resistor. 15 GND Analog Ground. Heat Sink

Paddle

N/C

The metallic back surface of the package is not electrically connected to any part of the circuit. It can be left floa

ting for optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. Exposed metal at package corners is connected to the heat sink paddle.

TP

P

N

TN

Figure 4. ADCMP581 Pin Configuration

I CC

1V

2V

ADCMP581

3V

4V

(Not to Scale)

GND

V

15

16

PIN 1 INDICATOR

TOP VIEW

5

6

I

LE

CC

EE

HYS

V

14

13

12 GND

11 Q

10

Q

9GND

8

7

E

TT

L

V

4672-004

TP

P

N

TN

1V

2V

ADCMP582

3V

4V

(Not to Scale)

CCI

GND

V

15

16

PIN 1 INDIC ATO R

TOP VIEW

5

6

LE

CCI

EE

HYS

V

14

13

12 V

CCO

11 Q

Q

10

9V

CCO

8

7

TT

LE

V

Figure 5. ADCMP582 Pin Configuration

= high), the output reflects the input state just prior to the comparator being

high), the output tracks changes at the

.

onnected to the GND ground.

onnected to the –2 V termination potential.

– 2 V termination potential.

CCO

supply.

CCO

, provided that the comparator is in compare mode. See the LE/LE descriptions

N

oltage at the noninverting input, V

, provided that the comparator is in compare mode. See the LE/LE

N

, is greater than the

P

supply with a

EE

4672-005

Rev. A | Page 7 of 16

ADCMP580/ADCMP581/ADCMP582

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TYPICAL PERFORMANCE CHARACTERISTICS

V

= 5.0 V, VEE = −5.0 V, V

CCI

12

= 3.3 V, TA = 25°C, unless otherwise noted.

CCO

80

10

8

6

4

BIAS CURRENT (µA)

2

0

–4

Figure 6. Bias Current vs. Co

0.8

–0.9

–1.0

–1.1

–1.2

OUTPUT (V)

–1.3

VOH vs. TEMPE RATURE

OUTPUT (NECL)

VOL vs. TEMPE RATURE

OUTPUT (NECL)

VIN COMMON-MO DE BIAS SWEEP

–2 0 2

COMMON-MODE (V)

mmon-Mode Voltage

70

60

50

40

30

HYSTERESIS (mV)

20

10

0

4

04672-006

1 10k

10 100 1k

CONTROL RESISTO R (Ω)

R

HYS

Figure 9. Hysteresis vs. R

Control Resistor

HYS

04672-009

2.5

2.4

VOH vs. TEMPERATURE

2.3

2.2

OUTPUT (V)

2.1

OUTPUT (PECL)

–1.4

–1.5

–55

–5 45 95

Figure 7. ADCMP581 Output V

80

70

60

50

40

30

HYSTERESIS (mV)

20

10

0

100 200 300 400 500

Figure 8. Hysteresis vs. −IHYST

TEMPERATURE (°C)

oltage vs. Temperature

–IHYST (µ A)

145

600

2.0

1.9 –55

04672-007

–5 45 95

VOL vs. TEMPE RATURE

OUTPUT (PECL)

TEMPERATURE (°C)

145

04672-010

Figure 10. ADCMP582 Output Voltage vs. Temperature

8

7

6

5

4

OFFSET (mV)

3

2

1

0

04672-008

+125°C COMMON-MODE OFFSET SWEEP

+25°C COMMO N-MODE OF FSET SW EEP

–55°C COMMO N-MODE OF FSET SWEEP

–2

Figure 11. A Typical V

02

COMMON-MODE (V)

vs. Common-Mode Voltage

OS

4

04672-011

Rev. A | Page 8 of 16

ADCMP580/ADCMP581/ADCMP582

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5

4

3

2

1

0

–1

–2

LOT2 CHAR1 RISE

–3

PROPAGATION DELAY ERROR (ps)

LOT2 CHAR1 FALL LOT3 CHAR1 RISE

–4

LOT3 CHAR1 FALL

–5

–2 3

–1012

(V)

V

CM

04672-012

45

43

41

39

37

(ps)

35

F

t

/

R

t

33

31

29

27

25

–55

–35 –15 5 25 45 65 85 105

TEMPERATURE (°C)

Q

RISE

Q

RISE

Q

FALL

Q

FALL

125

04672-015

Figure 12. ADCMP580 Propagation Delay Error vs. Common-Mode Voltage

M1

04672-013

Figure 13. ADCMP580 Eye Diagram at 7.5 Gbps

18

16

14

12

10

8

DISPERSIO N (ps)

6

4

2

OD DISPERSION RISE

0

50 100 150 200

OVERDRIVE (mV)

OD DISPERSI ON FALL

250

Figure 14. Dispersion vs. Overdrive

Figure 15. ADCMP581 t

vs. Temperature

R/tF

500mV

M1

500mV

20ps/DIV

04672-016

Figure 16. ADCMP582 Eye Diagram at 2.5 Gbps

04672-014

Rev. A | Page 9 of 16

ADCMP580/ADCMP581/ADCMP582

V

VPV

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TYPICAL APPLICATION CIRCUITS

GND

V

TP

V

IN

P

V

ADCMP580

N

V

TN

LATCH INPUTS

Figure 17. Zero-Crossing Detector with CML Outputs

TP

V

P

N

P

V

ADCMP581

N

V

TN

LATCH INPUTS

Figure 18. LVDS to a 50 Ω Back-Terminated (RS) ECL Receiver

50Ω50Ω

Q

4672-017

P

N

ADCMP580

1kΩ

V

EE

Figure 21. Disabling the Lat

CML

50Ω

ch Feature on the ADCMP580

04672-021

Q

50Ω50Ω

V

TT

4672-018

V

P

N

ADCMP581

= –2V

V

TT

750Ω

V

EE

Figure 22. Disabling the Lat

RSECL

50Ω50Ω

V

TT

ch Feature on the ADCMP581

04672-022

50Ω

CCO

RSPECL

50Ω

– 2V

04672-023

ADCMP580

HYS

0Ω TO 5kΩ

V

EE

Figure 19. Adding Hysteresis

V

IN

TH

+

ADCMP580

–

LATCH INPUTS

50Ω 50Ω

Using the HYS Control

GND

N

04672-019

Figure 23. Disabling the Latch Fe

ADCMP582

750Ω

V

CCO

VTT = V

ature on the ADCMP582

50Ω50Ω

Q

04672-020

Figure 20. Comparator with −2 to +3 V Input Range

Rev. A | Page 10 of 16

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APPLICATION INFORMATION

POWER/GROUND LAYOUT AND BYPASSING

The ADCMP58x family of comparators is designed for very high speed applications. Consequently, high speed design techniques must be used to achieve the specified performance. It is critically important to use low impedance supply planes, particularly for the negative supply (V plane (V

), and the ground plane (GND). Individual supply

CCO

planes are recommended as part of a multilayer board. Providing the lowest inductance return path for the switching currents ensures the best possible performance in the target application.

It is also important to adequately bypass the input and output su

pplies. A 1 µF electrolytic bypass capacitor should be placed within several inches of each power supply pin to ground. In addition, multiple high quality 0.1 µF bypass capacitors should be placed as close as possible to each of the V supply pins and should be connected to the GND plane with redundant vias. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should be strictly avoided to maximize the effectiveness of the bypass at high frequencies.

ADCMP58x FAMILY OF OUTPUT STAGES

Specified propagation delay dispersion performance is achieved by using proper transmission line terminations. The outputs of the ADCMP580 family comparators are designed to directly drive 400 mV into 50 Ω cable or microstrip/stripline transmission lines terminated with 50 Ω referenced to the proper return. The CML output stage for the ADCMP580 is shown in the simplified schematic diagram in

ck-terminated with 50 Ω for best transmission line matching.

ba The outputs of the ADCMP581/ADCMP582 are illustrated in Figure 25; they should be terminated to −2 V for ECL outputs of AD

CMP581 and V As an alternative, Thevenin equivalent termination networks can also be used. If these high speed signals must be routed more than a centimeter, either microstrip or stripline techniques are required to ensure proper transition times and to prevent excessive output ringing and pulse width-dependent propagation delay dispersion.

− 2 V for PECL outputs of ADCMP582.

CCO

), the output supply

EE

and V

EE, VCCI,

Figure 24. Each output is

CCO

GND

50Ω50Ω

Q

16mA

V

EE

Figure 24. Simplified Schematic Diagram of the ADCMP580 CML Output Stage

GND/V

CCO

V

EE

Figure 25. Simplified Schematic Diagram of the

A

DCMP581/ADCMP582 ECL/PECL Output Stage

04672-024

Q

04672-025

USING/DISABLING THE LATCH FEATURE

The latch inputs (LE/LE) are active low for latch mode and are internally terminated with 50 Ω resistors to the V using the ADCMP580, V When using the ADCMP581, V When using the ADCMP582, V to V

− 2 V, preferably with its own low inductance plane.

CCO

should be connected to ground.

TT

should be connected to −2 V.

TT

should be connected externally

TT

When using the ADCMP580, the latch function can be disabled

connecting the

by

LE

pin to VEE with an external pull-down resistor and by leaving the LE pin to ground. To prevent excessive power dissipation, the resistor should be 1 kΩ for the ADCMP580. When using the ADCMP581 comparators, the latch can be disabled by connecting the

LE

pin to VEE with an external 750 Ω resistor and leaving the LE pin connected to −2 V. The idea is to create an approximate 0.5 V offset using the internal resistor as half of the voltage divider. The V

pin should be connected as

TT

recommended.

pin. When

TT

Rev. A | Page 11 of 16

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OPTIMIZING HIGH SPEED PERFORMANCE

As with any high speed comparator, proper design and layout techniques are essential to obtaining the specified performance. Stray capacitance, inductance, inductive power, and ground impedances or other layout issues can severely limit performance and can cause oscillation. Discontinuities along input and output transmission lines can also severely limit the specified pulse width dispersion performance.

For applications in a 50 Ω environment, input and output ma

tching have a significant impact on data-dependent (or deterministic) jitter (DJ) and pulse width dispersion performance. The ADCMP58x family of comparators provides internal 50 Ω termination resistors for both V The return side for each termination is pinned out separately with the V is desired at one or both of the V

and VTN pins, respectively. If a 50 Ω termination

TP

inputs, the VTP and VTN

P/VN

pins can be connected (or disconnected) to (from) the desired termination potential as appropriate. The termination potential should be carefully bypassed using ceramic capacitors as discussed previously to prevent undesired aberrations on the input signal due to parasitic inductance in the termination return path. If a 50 Ω termination is not desired, either one or both of the V

termination pins can be left disconnected. In this

TP/VTN

case, the open pins should be left floating with no external pull downs or bypassing capacitors.

For applications that require high speed operation but do not

ave on-chip 50 Ω termination resistors, some reflections

h should be expected, because the comparator inputs can no longer provide matched impedance to the input trace leading up to the device. It then becomes important to back-match the drive source impedance to the input transmission path leading to the input to minimize multiple reflections. For applications in which the comparator is less than 1 cm from the driving signal source, the source impedance should be minimized. High source impedance in combination with parasitic input capacitance of the comparator could cause undesirable degradation in bandwidth at the input, thus degrading the overall response. It is therefore recommended that the drive source impedance should be no more than 50 Ω for best high speed performance.

and VN inputs.

P

COMPARATOR PROPAGATION DELAY DISPERSION

The ADCMP58x family of comparators has been specifically designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mV to 500 mV. Propagation delay dispersion is a change in propagation delays that results from a change in the degree of overdrive or slew rate (how far or fast the input signal exceeds the switching threshold). The overall result is a higher degree of timing accuracy.

Propagation delay dispersion is a specification that becomes im

portant in critical timing applications, such as data communications, automatic test and measurement, instrumentation, and event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in the overall propagation delay as the input overdrive conditions are changed (see Figure 27). For the ADCMP58x family of comparators, dispersio

n is typically <25 ps, because the overdrive varies from 5 mV to 500 mV, and the input slew rate varies from 1 V/ns to 10 V/ns. This specification applies for both positive and negative signals because the ADCMP58x family of comparators has almost equal delays for positive- and negative-going inputs.

500mV OVERDRIVE

INPUT VOLTAGE

5mV OVERDRIVE

Q/Q OUTPUT

Figure 26. Propagation Delay—Overdrive Dispersion

INPUT VOLTAGE

1V/ns

10V/ns

Figure 26 and

V

± V

N

DISPERSIO N

± V

V

N

OS

04672-026

OS

Rev. A | Page 12 of 16

DISPERSION

Q/Q OUTPUT

Figure 27. Propagation Delay—Slew Rate Dispersion

4672-027

ADCMP580/ADCMP581/ADCMP582

V

–V

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COMPARATOR HYSTERESIS

Adding hysteresis to a comparator is often desirable in a noisy environment or when the differential inputs are very small or slow moving. The transfer function for a comparator with hysteresis is shown in

e threshold from the negative direction, the comparator

th switches from a low to a high when the input crosses +V The new switching threshold becomes −V remains in the high state until the threshold −V from the positive direction. In this manner, noise centered on 0 V input does not cause the comparator to switch states unless it exceeds the region bounded by ±V

The customary technique for introducing hysteresis into a c

omparator uses positive feedback from the output back to the input. A limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. The external feedback network can also introduce significant parasitics that reduce high speed performance and can even reduce overall stability in some cases.

0

Figure 28. Comparator Hysteresis Transfer Function

The ADCMP58x family of comparators offers a programmable hysteresis feature that can significantly improve the accuracy and stability of the desired hysteresis. By connecting an external pull-down resistor from the HYS pin to V of hysteresis can be applied. Leaving the HYS pin disconnected disables the feature, and hysteresis is then less than 1 mV, as specified. The maximum range of hysteresis that can be applied by using this method is approximately ±70 mV.

Figure 29 illustrates the amount of applied hysteresis as a

unction of the external resistor value. The advantage of

f applying hysteresis in this manner is improved accuracy, stability, and reduced component count. An external bypass capacitor is not required on the HYS pin, and it would likely degrade the jitter performance of the device.

Figure 28. If the input voltage approaches

/2. The comparator

H

/2 is crossed

H

/2.

H

+

H

2

0V

OUTPUT

H

2

INPUT

1

4672-028

, a variable amount

EE

H

/2.

The hysteresis pin can also be driven by a current source.

t is biased approximately 400 mV above V

I

and has an

EE

internal series resistance of approximately 600 Ω.

80

70

60

50

40

30

20

COMPARATOR HYSTERESIS (mV)

10

0

1 10k

Figure 29. Comparator Hysteresis vs. R

10 100 1k

R

CONTROL RESISTO R (Ω)

HYS

Control Resistor

HYS

04672-029

MINIMUM INPUT SLEW RATE REQUIREMENT

As with many high speed comparators, a minimum slew rate requirement must be met to ensure that the device does not oscillate as the input signal crosses the threshold. This oscillation is due in part to the high input bandwidth of the comparator and the feedback parasitics inherent in the package. A minimum slew rate of 50 V/µs should ensure clean output transitions from the ADCMP58x family of comparators.

The slew rate may be too slow for other reasons. The extremely h

igh bandwidth of these devices means that broadband noise can be a significant factor when input slew rates are low. There is 120 V of thermal noise generated over the bandwidth of the comparator by the two 50  terminations at room temperature. With a slew rate of only 50 V/s, the inputs are inside this noise band for over 2 ps, rendering the comparator’s jitter performance of 200 fs irrelevant. Raising the slew rate of the input signal and/or reducing the bandwidth over which that resistance is seen at the input can greatly reduce jitter. Devices are not characterized this way but simply bypassing a reference input close to the package can reduce jitter 30% in low slew rate applications.

Rev. A | Page 13 of 16

ADCMP580/ADCMP581/ADCMP582

R

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OUTLINE DIMENSIONS

0.50

0.40

PIN 1

INDICATO

0.90

0.85

0.80

SEATING

PLANE

12° MAX

3.00

BSC SQ

TOP

VIEW

0.30

0.23

0.18

*

COMPLIANT EXCEPT FOR EXPOSED PAD DIMENSION.

2.75

BSC SQ

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

TO

JEDEC STANDARDS MO-220-VEED-2

0.45

0.50

BSC

1.50 REF

0.60 MAX

13

12

(BOTTOM VIEW)

9

8

Figure 30. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

3

mm × 3 mm Body, Very Thin Quad

(CP-16-3)

Dimensions shown in millimeters

EXPOSED

PAD

0.30

16

1

4

5

N

P

I

D

N

I

*

1.65

1.50 SQ

1.35

0.25 MIN

1

O

C

I

A

T

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

ADCMP580BCP-WP −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G07 ADCMP580BCP–R2 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G07 ADCMP580BCP–RL7 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G07 ADCMP580BCPZ-WP ADCMP580BCPZ–R2 ADCMP580BCPZ–RL7 ADCMP581BCP-WP −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G09 ADCMP581BCP–R2 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G09 ADCMP581BCP–RL7 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G09 ADCMP581BCPZ-WP ADCMP581BCPZ–R2 ADCMP581BCPZ–RL7 ADCMP582BCP-WP −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G0B ADCMP582BCP-R2 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G0B ADCMP582BCP-RL7 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G0B ADCMP582BCPZ-WP ADCMP582BCPZ-R2 ADCMP582BCPZ-RL7 EVAL-ADCMP580BCPZ EVAL-ADCMP581BCPZ EVAL-ADCMP582BCPZ

1

Z = RoHS Compliant Part.

1

−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G12

−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G11

−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G10

−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G10 Evaluation Board Evaluation Board Evaluation Board

Rev. A | Page 14 of 16

ADCMP580/ADCMP581/ADCMP582

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NOTES

Rev. A | Page 15 of 16

ADCMP580/ADCMP581/ADCMP582

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NOTES

T

Rev. A | Page 16 of 16

TTT

ANALOG DEVICES ADCMP580, ADCMP581, ADCMP582 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING INFORMATION

ABSOLUTE MAXIMUM RATINGS

THERMAL CONSIDERATIONS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TYPICAL APPLICATION CIRCUITS

APPLICATION INFORMATION

POWER/GROUND LAYOUT AND BYPASSING

ADCMP58x FAMILY OF OUTPUT STAGES

USING/DISABLING THE LATCH FEATURE

OPTIMIZING HIGH SPEED PERFORMANCE

COMPARATOR PROPAGATION DELAY DISPERSION

COMPARATOR HYSTERESIS

MINIMUM INPUT SLEW RATE REQUIREMENT

OUTLINE DIMENSIONS

ORDERING GUIDE