ANALOG DEVICES ADCMP572, ADCMP573 Service Manual

Ultrafast 3.3 V/5 V

FEATURES

3.3 V/5.2 V single-supply operation
150 ps propagation delay
15 ps overdrive and slew rate dispersion
8 GHz equivalent input rise time bandwidth
80 ps minimum pulse width
35 ps typical output rise/fall
10 ps deterministic jitter (DJ)
200 fs random jitter (RJ)
On-chip terminations at both input pins
Robust inputs with no output phase reversal
Resistor-programmable hysteresis
Differential latch control
Extended industrial −40°C to +125°C temperature range

APPLICATIONS

Clock and data signal restoration and level shifting
Automatic test equipment (ATE)
High speed instrumentation
Pulse spectroscopy
Medical imaging and diagnostics
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry

Single-Supply SiGe Comparators

ADCMP572/ADCMP573

FUNCTIONAL BLOCK DIAGRAM

V

CML/
RSPECL

LE INPUT

LE INPUTHYS

CCO

Q OUTPUT

Q OUTPUT

04409-025

V

TERMINATION

TP

VP NONINVERTING

V

N

V

TN

INPUT

INVERTING

INPUT

TERMINATION

V

CCI

ADCMP572
ADCMP573

Figure 1.

GENERAL DESCRIPTION

The ADCMP572 and ADCMP573 are ultrafast comparators
fabricated on Analog Devices’ proprietary XFCB3 Silicon
Germanium (SiGe) bipolar process. The ADCMP572 features
CML output drivers and latch inputs, and the ADCMP573
features reduced swing PECL (RSPECL) output drivers and
latch inputs.

Both devices offer 150 ps propagation delay and 80 ps
minimum pulse width for 10 Gbps operation with 200 fs rms
random jitter (RJ). Overdrive and slew rate dispersion are
typically less than 15 ps.

A flexible power supply scheme allows both devices to operate
with a single 3.3 V positive supply and a −0.2 V to +1.2 V input
signal range or with split input/output supplies to support a
wider −0.2 V to +3.2 V input signal range and an independent
range of output levels. 50 Ω on-chip termination resistors are

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devi ces for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

provided at both inputs with the optional capability to be left
open (on an individual pin basis) for applications requiring
high impedance inputs.

The CML output stage is designed to directly drive 400 mV into
50 Ω transmission lines terminated to between 3.3 V to 5.2 V.
The RSPECL output stage is designed to drive 400 mV into
50 Ω terminated to V

− 2 V and is compatible with several

CCO

commonly used PECL logic families. The comparator input
stage offers robust protection against large input overdrive, and
the outputs do not phase reverse when the valid input signal
range is exceeded. High speed latch and programmable
hysteresis features are also provided.

The ADCMP572 and ADCMP573 are available in a 16-lead
LFCSP package and have been characterized over an extended
industrial temperature range of −40°C to +125°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005–2009 Analog Devices, Inc. All rights reserved.

ADCMP572/ADCMP573

TABLE OF CONTENTS

Electrical Characteristics ................................................................. 3

Using/Disabling the Latch Feature ..............................................9

Absolute Maximum Ratings ............................................................ 5

Thermal Considerations .............................................................. 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

Application Information .................................................................. 9

Power/Ground Layout and Bypassing ....................................... 9

CML/RSPECL Output Stage ....................................................... 9

REVISION HISTORY

4/09—Rev. 0 to Rev. A

Changes to Figure 26 ...........................................................................12

Updated Outline Dimensions ............................................................14

Changes to Ordering Guide ...............................................................14

4/05—Revision 0: Initial Version

Optimizing High Speed Performance ..................................... 10

Comparator Propagation Delay Dispersion ........................... 10

Comparator Hysteresis .............................................................. 11

Minimum Input Slew Rate Requirements .............................. 11

Typical Application Circuits ......................................................... 12

Timing Information ....................................................................... 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. A | Page 2 of 16

ADCMP572/ADCMP573

ELECTRICAL CHARACTERISTICS

V

= V

CCI

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

DC INPUT CHARACTERISTICS

Input Voltage Range VP, VN V
V
Input Differential Voltage −1.2 +1.2 V
Input Offset Voltage VOS −5.0 ±2.0 +5.0 mV
Offset Voltage Tempco ∆VOS/dT 10.0 μV/°C
Input Bias Current IP, IN Open termination −50.0 −25.0 0.0 μA
Input Bias Current Tempco 50.0 nA/°C
Input Offset Current ±2.0 μA
Input Impedance 50 Ω
Input Resistance, Differential Open termination 50 kΩ
Input Resistance, Common-Mode Open termination 500 kΩ
Active Gain AV 54 dB
Common-Mode Rejection CMRR V

Power Supply Rejection—V
Hysteresis

LATCH ENABLE CHARACTERISTICS

ADCMP572

ADCMP573

Latch Enable Input Impedance 50.0 Ω
Latch to Output Delay t
Latch Minimum Pulse Width tPL V

DC OUTPUT CHARACTERISTICS

ADCMP572 (CML)

ADCMP573 (RSPECL)

= 3.3 V, TA = −40°C to +125°C, typical at TA = +25°C, unless otherwise noted.

CCO

= 3.3 V, V

CCI

= 5.2 V, V

CCI

= 3.3 V, V

CCI

V

= 0.0 V to 1.0 V

CM

V

= 5.2 V, V

CCI

V

= 0.0 V to 3.0 V

CM

PSR

CCI

V

VCCI

R

= 3.3 V ± 5%, V

CCI

= ∞

HYS

Latch Enable Input Range 2.8 V

= 3.3 V −0.2 +1.2 V

CCO

= 3.3 V −0.2 +3.1 V

CCO

= 3.3 V,

CCO

= 3.3 V,

CCO

= 3.3 V 74 dB

CCO

65 dB

65 dB

±1 mV

+ 0.2 V

CCO

Latch Enable Input Differential 0.2 0.4 0.5 V
Latch Setup Time tS V
Latch Hold Time tH V

Latch Enable Input Range 1.8 V

= 100 mV 15 ps

OD

= 100 mV 5 ps

OD

− 0.6 V

CCO

Latch Enable Input Differential 0.2 0.4 0.5 V
Latch Setup Time tS V
Latch Hold Time tH V

PLOH, tPLOL

Output Impedance Z

VOD = 100 mV 150 ps

−8 mA < I

OUT

Output Voltage High Level VOH 50 Ω terminate to V
Output Voltage Low Level VOL 50 Ω terminate to V
Output Voltage Differential 50 Ω terminate to V

Output Voltage High −40°C VOH 50 Ω terminate to V
Output Voltage High +25°C VOH 50 Ω terminate to V
Output Voltage High +125°C VOH 50 Ω terminate to V
Output Voltage Low −40°C VOL 50 Ω terminate to V
Output Voltage Low +25°C VOL 50 Ω terminate to V
Output Voltage Low +125°C VOL 50 Ω terminate to V
Output Voltage Differential 50 Ω terminate to V

= 100 mV 90 ps

OD

= 100 mV 100 ps

OD

= 100 mV 100 ps

OD

< 8 mA 50.0 Ω

OUT

V

CCO

V

CCO

300 375 450 mV

CCO

− 2.0 V

CCO

− 2.0 V

CCO

− 2.0 V

CCO

− 2.0 V

CCO

− 2.0 V

CCO

− 2.0 V

CCO

− 2.0 300 375 450 mV

CCO

− 0.10 V

CCO

− 0.60 V

CCO

− 1.14 V

CCO

− 1.10 V

CCO

− 1.04 V

CCO

− 1.54 V

CCO

− 1.50 V

CCO

− 1.44 V

CCO

− 0.05 V

CCO

− 0.45 V

CCO

− 1.02 V

CCO

− 0.98 V

CCO

− 0.92 V

CCO

− 1.39 V

CCO

− 1.35 V

CCO

− 1.29 V

CCO

V

CCO

− 0.30 V

CCO

− 0.90 V

CCO

− 0.86 V

CCO

− 0.80 V

CCO

− 1.24 V

CCO

− 1.20 V

CCO

− 1.14 V

CCO

Rev. A | Page 3 of 16

ADCMP572/ADCMP573

Parameter Symbol Conditions Min Typ Max Unit

AC PERFORMANCE

Propagation Delay tPD V

V

V
Propagation Delay Tempco ∆tPD/dT 0.5 ps/°C
Prop Delay Skew—Rising Transition

V

to Falling Transition
Overdrive Dispersion 50 mV < VOD < 0.2 V, 5 V/ns 15 ps

Slew Rate Dispersion 2 V/ns to 10 V/ns, 250 mV OD 15 ps
Pulse Width Dispersion 100 ps to 5 ns, 250 mV OD 5 ps
10% – 90% Duty Cycle Dispersion V

Common-Mode Dispersion VOD = 0.2 V, 0.0 V < VCM < 2.9 V 5 ps/V
Equivalent Input Bandwidth1 BWEQ

Toggle Rate >50% Output Swing 12.5 Gbps
Deterministic Jitter DJ

RMS Random Jitter RJ VOD = 200 mV, 5 V/ns, 1.25 GHz 0.2 ps
Minimum Pulse Width PW
PW

∆tPD/∆PW < 5 ps, 200 mV OD 100 ps

MIN

∆tPD/∆PW < 10 ps, 200 mV OD 80 ps

MIN

Rise Time tR 20/80 35 ps
Fall Time tF 20/80 35 ps

POWER SUPPLY

Input Supply Voltage Range V
Output Supply Voltage Range V
Positive Supply Differential V

3.1 5.4 V

CCI

3.1 5.4 V

CCO

−V

−0.2 +2.3 V

CCI

CCO

ADCMP572 (CML)

Positive Supply Current I

VCCI

+ I

VCCO

Device Power Dissipation PD

ADCMP573 (RSPECL)

Positive Supply Current I

VCCI

+ I

VCCO

Device Power Dissipation PD

1

Equivalent input bandwidth assumes a simple first-order response and is calculated with the following formula: BWEQ = 0.22/√(tr

transition time of a quasi-Gaussian signal applied to the comparator input, and tr

= 3.3 V, VOD = 200 mV 150 ps

CCI

= 3.3 V, VOD = 20 mV 165 ps

CCI

= 5.2 V, VOD = 200 mV 145 ps

CCI

= 200 mV, 5 V/ns 10 ps

OD

10 mV < VOD < 0.2 V, 5 V/ns 15 ps

= 3.3 V, 1 V/ns, 250 mV OD 5 ps

CCI

V

= 5.2 V, 1 V/ns, 250 mV OD 10

CCI

0.0 V to 250 mV input

8.0 GHz

tR = tF = 17 ps, 20/80

= 200 mV, 5 V/ns,

V

OD

31

− 1 NRZ, 4 Gbps

PRBS

= 200 mV, 5 V/ns,

V

OD

31

− 1 NRZ, 10 Gbps

PRBS

= 3.3 V, V

V

CCI

terminate 50 Ω to V
V

= 5.2 V, V

CCI

terminate 50 Ω to V

= 3.3 V, V

V

CCI

terminate 50 Ω to V
V

= 5.2 V, V

CCI

terminate 50 Ω to V

= 3.3 V, V

V

CCI

50 Ω to V
V

= 5.2 V, V

CCI

50 Ω to V

= 3.3 V, V

V

CCI

50 Ω to V
V

= 5.2 V, V

CCI

50 Ω to V

= 3.3 V,

CCO

CCO

CCO

CCO

CCO

− 2 V

CCO

CCO

– 2 V

CCO

CCO

− 2 V

CCO

CCO

− 2 V

CCO

is the effective transition time digitized by the comparator.

COMP

CCO

= 5.2 V,

CCO

= 3.3 V,

CCO

= 5.2 V,

CCO

= 3.3 V,

= 5.2 V,

= 3.3 V,

= 5.2 V,

10 ps

20 ps

44 52 mA

44 52

140 165 mW

230 265

62 80 mA

64 80

110 160 mW

146 230

2

2

−tr

), where trIN is the 20/80

COMP

IN

Rev. A | Page 4 of 16

ADCMP572/ADCMP573

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

SUPPLY VOLTAGE

Input Supply Voltage

to GND)

(V

CCI

Output Supply Voltage

(V

to GND)

CCO

Positive Supply Differential

− V

CCO

)

(V

CCI

INPUT VOLTAGE

Input Voltage −0.5 V to V
Differential Input Voltage ±(V
Input Voltage, Latch Enable −0.5 V to V

HYSTERESIS CONTROL PIN

Applied Voltage (HYS to GND) −0.5 V to +1.5 V
Maximum Input/Output Current ±1 mA

OUTPUT CURRENT

ADCMP572 (CML) ±20 mA
ADCMP573 (RSPECL) −35 mA

TEMPERATURE

Operating Temperature, Ambient −40°C to +125°C
Operating Temperature, Junction +150°C
Storage Temperature Range −65°C to +150°C

−0.5 V to +6.0 V

−0.5 V to +6.0 V

−0.5 V to +3.5 V

+ 0.5 V

CCI

+ 0.5 V)

CCI

+ 0.5 V

CCO

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CONSIDERATIONS

The ADCMP572/ADCMP573 LFCSP 16-lead package has a θJA
(junction-to-ambient thermal resistance) of 70°C/W in still air.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. A | Page 5 of 16

ADCMP572/ADCMP573

V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CCI

V

GND14HYS13GND

16

15

PIN1

1

V

TP

ADCMP572

2

V

P

ADCMP573

3

V

N

TN

4

TOP VIEW

(Not to Scale)

5

6LE7LE8

CCI

V

Figure 2. ADCMP572/ADCMP573 Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 VTP Termination Resistor Return Pin for VP Input.
2 VP Noninverting Analog Input.
3 VN Inverting Analog Input.
4 VTN Termination Resistor Return Pin for VN Input.
5, 16 V
6

7 LE

Positive Supply Voltage for Input Stage.

CCI

Latch Enable Input Pin, Inverting Side.

LE

In compare mode (LE
In latch mode (LE
into latch mode. LE

= low), the output tracks changes at the input of the comparator.

= high), the output reflects the input state just prior to the comparator’s being placed

must be driven in complement with LE.

Latch Enable Input Pin, Noninverting Side.
In compare mode (LE = high), the output tracks changes at the input of the comparator.
In latch mode (LE = low), the output reflects the input state just prior to the comparator’s being placed
into latch mode. LE must be driven in complement with LE

8 V

CCO/VTT

Termination Return Pin for the LE/LE
For the ADCMP572 (CML output stage), this pin is internally connected to and also should be externally
connected to the positive V

supply.

CCO

For the ADCMP573 (RSPECL output stage), this pin should normally be connected to the V
termination potential.

9, 12 V

Positive Supply Voltage for the CML/RSPECL Output Stage.

CCO

13, 15 GND Ground.
10

Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the

Q

analog voltage at the inverting input, V
descriptions (Pins 6 and 7) for more information.

11 Q

Noninverting Output. Q is at logic high if the analog voltage at the noninverting input V
than the analog voltage at the inverting input, V

descriptions (Pins 6 and 7) for more information.

14 HYS

See the LE/LE
Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect to GND with a suitably

sized resistor to add the desired amount of hysteresis. Refer to Figure 7 for proper sizing of R
hysteresis control resistor.

Isolated
Heat Sink

N/C

The metallic back surface of the package is not electrically connected to any part of the circuit, and it
can be left floating for best electrical isolation between the package handle and the substrate of the
die. However, it can be soldered to the application board if improved thermal and/or mechanical
stability is desired. Exposed metal at package corners is connected to the heat sink paddle.

12

V

CCO

11

Q

10

Q

9

V

CCO

TT

/V

CCO

V

Input Pins.

, provided the comparator is in compare mode. See the LE/LE

N

04409-026

.

– 2 V

CCO

is greater

, provided the comparator is in compare mode.

N

P

HYS

Rev. A | Page 6 of 16

ADCMP572/ADCMP573

TYPICAL PERFORMANCE CHARACTERISTICS

V

= V

CCI

= 3.3 V, TA = 25°C, unless otherwise noted.

CCO

20

15

39.0

38.5

38.0

10

5

PROPAGATION DELAY ERROR (ps)

0

0 50 100 150 200 250

INPUT OVERDRIVE VOLTAGE (mV)

Figure 3. Propagation Delay vs. Input Overdrive

158.5

158.0

157.5

157.0

156.5

PROPAGATION DELAY (ps)

156.0

155.5

0.4 0.60 0.2 0.8 1.0 1.2

INPUT COMMON-MODE VOLTAGE (V)

Figure 4. Propagation Delay vs. Input Common-Mode

04409-039

04409-040

37.5

37.0

RISE/FALL TIME (ps)

36.5

36.0

Figure 6. Rise/Fall Time vs. Temperature

60

50

40

30

20

HYSTERESIS (mV)

10

0

Figure 7. Hysteresis vs. R

200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

2301 456

R

(kΩ)

HYS

Control Resistor

HYS

04409-042

04409-043

160

158

156

154

152

150

PROPAGATION DELAY (ps)

148

146

200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

04409-041

Figure 5. Propagation Delay vs. Temperature

80

70

60

50

40

30

HYSTERESIS (mV)

20

10

0
–600 –500 –400 –300 –200 –100 0

Figure 8. Hysteresis vs. R

R

SINK CURRENT (μA)

HYS

Sink Current

HYS

04409-047

Rev. A | Page 7 of 16

ADCMP572/ADCMP573

–15.0

380

–15.5

A)

μ

–16.0

–16.5

–17.0

–17.5

INPUT BIAS CURRENT (

–18.0

–18.5

–0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5

INPUT VOLTAGE (VN = –0.2V)

V

P

Figure 9. Input Bias Current vs. Input Differential

–16.2

–16.3

A)

μ

–16.4

–16.5

–16.6

04409-044

379

378

377

376

OUTPUT LEVELS (mV)

375

374

373

200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

04409-046

Figure 12. Output Levels vs. Temperature

496.0mV

–16.7

INPUT BIAS CURRENT (

–16.8

–16.9

200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

Figure 10. Input Bias Current vs. Temperature

0.5

0.4

0.3

0.2

0.1

0

–0.1

OFFSET (mV)

–0.2

–0.3

–0.4

–0.5

–50 0 50 1007525–25 125

TEMPERATURE (°C)

Figure 11. Input Offset Voltage vs. Temperature

04409-045

04409-024

M1

504.0mV 60.00ps/DIV

04409-049

Figure 13. ADCMP572 Eye Diagram at 2.5 Gbps

500.0mV

500.0mV 25.00ps/DIV

04409-050

Figure 14. ADCMP572 Eye Diagram at 6.5 Gbps

Rev. A | Page 8 of 16

ADCMP572/ADCMP573

APPLICATION INFORMATION

POWER/GROUND LAYOUT AND BYPASSING

The ADCMP572/ADCMP573 comparators are very high speed

SiGe devices. Consequently, it is essential to use proper high

speed design techniques to achieve the specified performance.

Of critical importance is the use of low impedance supply

planes, particularly the output supply plane (V

) and the

CCO

ground plane (GND). Individual supply planes are recom-

mended as part of a multilayer board. Providing the lowest

inductance return path for switching currents ensures the best

possible performance in the target application.

It is important to adequately bypass the input and output

supplies. A 1 μF electrolytic bypass capacitor should be placed

within several inches of each power supply pin to ground. In

addition, multiple high quality 0.01 μF bypass capacitors should

be placed as close as possible to each of the V

CCI

and V

CCO

supply pins and should be connected to the GND plane with

redundant vias. High frequency bypass capacitors should be

carefully selected for minimum inductance and ESR. Parasitic

layout inductance should be avoided to maximize the

effectiveness of the bypass at high frequencies.

If the input and output supplies are connected separately such

that V

CCI

≠ V

, care should be taken to bypass each of these

CCO

supplies separately to the GND plane. A bypass capacitor

should not be connected between them. It is recommended that

the GND plane separate the V

CCI

and V

planes when the

CCO

circuit board layout is designed to minimize coupling between

the two supplies and to take advantage of the additional bypass

capacitance from each respective supply to the ground plane.

This enhances the performance when split input/output

supplies are used. If the input and output supplies are connected

together for single-supply operation such that V

CCI

= V

CCO

,
coupling between the two supplies is unavoidable; however,
every effort should be made to keep the supply plane adjacent
to the GND plane to maximize the additional bypass
capacitance this arrangement provides.

CML/RSPECL OUTPUT STAGE

Specified propagation delay dispersion performance can be
achieved only by using proper transmission line terminations.
The outputs of the ADCMP572 are designed to directly drive
400 mV into 50 Ω cable, microstrip, or strip line transmission
lines properly terminated to the V
output stage is shown in the simplified schematic diagram of
Figure 15. The outputs are each back terminated with 50 Ω for
best transmission line matching. The RSPECL outputs of the
ADCMP573 are illustrated in Figure 16 and should be
terminated to V

− 2 V. As an alternative, Thevenin

CCO

equivalent termination networks can be used in either case if
the direct termination voltage is not readily available. If high
speed output signals must be routed more than a centimeter,

supply plane. The CML

CCO

microstrip or strip line techniques are essential to ensure proper
transition times and to prevent output ringing and pulse width
dependent propagation delay dispersion. For the most timing
critical applications where transmission line reflections pose the
greatest risk to performance, the ADCMP572 provides the best
match to 50 Ω output transmission paths.

V

CCO

50

Ω

Q

Q

16mA

GND

Figure 15. Simplified Schematic Diagram of

the ADCMP572 CML Output Stage

V

CCO

GND

Figure 16. Simplified Schematic Diagram of

the ADCMP573 RSPECL Output Stage

04409-037

Q

Q

04409-038

USING/DISABLING THE LATCH FEATURE

The latch inputs (LE/LE) are active low for latch mode and are
internally terminated with 50 Ω resistors to Pin 8. This pin
corresponds to and is internally connected to the V
for the CML-compatible ADCMP572. With the aid of these
resistors the ADCMP572 latch function can be disabled by
connecting the

LE

pin to GND with an external pull-down
resistor and leaving the LE pin unconnected. To avoid excessive
power dissipation, the resistor should be 750 Ω when V

3.3 V, and 1.2 kΩ when V
ADCMP573, the V

TT

PECL termination supply at V
disabled by connecting the LE pin to V

= 5.2 V. In the PECL-compatible

CCO

pin should be connected externally to the

– 2 V. The latch can then be

CCO

with an external

CCO

CCO

supply

=

CCO

Rev. A | Page 9 of 16

ADCMP572/ADCMP573

500 Ω resistor and leaving the LE pin disconnected. In this case,
the resistor value does not depend on the V

is the signal return for the output stage and V

V

CCO

should of course be connected to a supply plane for maximum
performance.

OPTIMIZING HIGH SPEED PERFORMANCE

As with any high speed comparator, proper design and layout
techniques are essential to obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit
performance and often cause oscillation. Discontinuities along
input and output transmission lines can severely limit the
specified pulse width dispersion performance.

For applications working in a 50 Ω environment, input and
output matching has a significant impact on data dependent (or
deterministic) jitter (DJ) and on pulse width dispersion
performance. The ADCMP572/ADCMP573 comparators
provide internal 50 Ω termination resistors for both the V
V

inputs, and the ADCMP572 provides 50 Ω back terminated

N

outputs. The return side for each input termination is pinned
out separately with the V
termination is desired at one or both of the V
the V

and VTN pins can be connected (or disconnected) to

TP

(from) the desired termination potential as required. The
termination potential should be carefully bypassed using high
quality bypass capacitors as discussed earlier to prevent
undesired aberrations on the input signal due to parasitic
inductance in the circuit board layout. If a 50 Ω input
termination is not desired, either one or both of the V
termination pins can be left disconnected. In this case, the pins
should be left floating with no external pull-downs or bypassing
capacitors.

When leaving an input termination disconnected, the internal
resistor acts as a small stub on the input transmission path and
can cause problems for very high speed inputs. Reflections
should then be expected from the comparator inputs because
they no longer provide matched impedance to the input path
leading to the device. In this case, it is important to back match
the drive source impedance to the input transmission path to
minimize multiple reflections. For applications in which the
comparator is very close to the driving signal source, the source
impedance should be minimized. High source impedance in
combination with parasitic input capacitance of the comparator
might cause an undesirable degradation in bandwidth at the
input, therefore degrading the overall response. Although the
ADCMP572/
minimize in

ADCMP573 comparators have been designed to

put capacitance, some parasitic capacitance is
inevitable. It is therefore recommended that the drive source
impedance be no more than 50 Ω for best high speed
performance.

and VTN pins, respectively. If a 50 Ω

TP

supply voltage.

CCO

pins

CCO

inputs, then

P/VN

TP/VTN

and

P

COMPARATOR PROPAGATION DELAY DISPERSION

The ADCMP572/ADCMP573 comparators are designed to
reduce propagation delay dispersion over a wide input overdrive
range of 5 mV to 500 mV. Propagation delay dispersion is
variation in the propagation delay that results from a change in
the degree of overdrive or slew rate (how far or how fast the
input signal exceeds the switching threshold).

Propagation delay dispersion is a specification that becomes
important in high speed, time-critical applications such as data
communication, automatic test and measurement, instrumenta­tion, and event driven applications such as pulse spectroscopy,
nuclear instrumentation, and medical imaging. Dispersion is
defined as the variation in propagation delay as the input over­drive conditions vary (Figure 17 and Figure 18). For the
ADCMP572/ADCMP573, dispersion is typically <15 ps
because the overdrive varies from 10 mV to 500 mV, and the
input slew rate varies from 2 V/ns to 10 V/ns. This specification
applies for both positive and negative signals since the
ADCMP572/ADCMP573 has substantially equal delays for

ther positive going or negative going inputs.

ei

500mV OVERDRIVE

INPUT VOLTAGE

10mV OVERDRIVE

± V

V

N

OS

DISPERSION

Q/Q OUTPUT

Figure 17. Propagation Delay—Overdrive Dispersion

INPUT VOLTAGE

1V/ns

V

10V/ns

DISPERSION

Q/Q OUTPUT

Figure 18. Propagation Delay—Slew Rate Dispersion

04409-0-027

± V

N

OS

04409-0-028

Rev. A | Page 10 of 16

ADCMP572/ADCMP573

COMPARATOR HYSTERESIS

The addition of hysteresis to a comparator is often desirable in a
noisy environment or when the differential input amplitudes are
relatively small or slow moving, but excessive hysteresis has a
cost in degraded accuracy and slew-induced timing shifts. The
transfer function for a comparator with hysteresis is shown in
Figure 19. If the input voltage approaches the threshold (0.0 V
in this example) from the negative direction, the comparator
switches from low to high when the input crosses +VH/2. The
new switching threshold becomes −V
remains in the high state until the threshold −V
from the positive direction. In this manner, noise centered on

0.0 V input does not cause the comparator to switch states
unless it exceeds the region bounded by ±V

/2. The comparator

H

/2 is crossed

H

/2.

H

applied as a function of external resistor value. The advantages
of applying hysteresis in this manner are improved accuracy,
stability, and reduced component count. An external bypass
capacitor is not recommended on the HYS pin because it would
likely degrade the jitter performance of the device. The
hysteresis pin could also be driven by a CMOS DAC. It is biased
to approximately 250 mV and has an internal series resistance
of 600 Ω.

60

50

40

30

OUTPUT

V

OH

V

OL

–V

H

2

Figure 19. Comparator Hysteresis Transfer Function

0

INPUT

+V

H

2

04409-005

The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. A limitation of this approach is that the amount of
hysteresis varies with the output logic levels, resulting in
hysteresis that can be load dependent and is not symmetrical
about the threshold. The external feedback network can also
introduce significant parasitics, which reduce high speed
performance and can even induce oscillation in some cases.

The ADCMP572/ADCMP573 comparators offer a program­mable hysteresis feature that can significantly improve the
accuracy and stability of the desired hysteresis. By connecting
an external pull-down resistor from the HYS pin to GND, a
variable amount of hysteresis can be applied. Leaving the HYS
pin disconnected disables the feature, and hysteresis is then less
than 1 mV as specified. The maximum hysteresis that can be
applied using this method is approximately ±25 mV with the
pin grounded. Figure 20 illustrates the amount of hysteresis

20

HYSTERESIS (mV)

10

0

Figure 20. Hysteresis vs. R

2301 456

(kΩ)

R

HYS

Control Resistor

HYS

MINIMUM INPUT SLEW RATE REQUIREMENTS

As with all high speed comparators, a minimum slew rate
requirement must be met to ensure that the device does not
oscillate as the input signal crosses the threshold. This
oscillation is due in part to the high input bandwidth of the
comparator and the feedback parasitics inherent in the package.
A minimum slew rate of 50 V/μs should ensure clean output
transitions from the ADCMP572/

lew rate may be too slow for other reasons. The extremely

The s
high bandwidth of these devices means that broadband noise
can be a significant factor when input slew rates are low. There
will be at least 120 μv of thermal noise generated over the full
comparator bandwidth by two 50 Ω terminations at room
temperature. With a slew rate of only 50 V/μs the input will be
inside this noise band for over 2 ps, rendering the comparator’s
jitter performance of 200 fs moot. Raising the slew rate of the
input signal and/or reducing the bandwidth over which this
resistance is seen at the input can greatly reduce jitter.

ADCMP573 comparators.

04409-043

Rev. A | Page 11 of

16

ADCMP572/ADCMP573

VPV

V

TYPICAL APPLICATION CIRCUITS

3.3V

CCI

CCO

V

V

TP

V

V

IN

P

V

N

V

TN

V

ADCMP572

LATCH
INPUTS

Figure 21. Zero-Crossing Detector with 3.3 V CML Outputs

V

= 5.2V

CCI

V

CCO

V

TP

V

P

V

ADCMP572

N

N

V

TN

LATCH
INPUTS

Figure 22. LVDS to 50 Ω Back Terminated RSPECL Receiver

50Ω 50Ω

Q

Q

04409-029

50Ω50Ω

V

CCI

V

= 3.3V 5V

CCO

75Ω

ADCMP572

LATCH
INPUTS

100Ω

100Ω

50Ω

50Ω

04409-034

Figure 25. Interfacing 3.3 V CML to a 50 Ω

Ground Terminated Instrument

CCI

V

= 3.3V V

Q

Q

04409-030

CCO

V

P

V

N

ADCMP572

1.35kΩ

V

CCO

CCO

50Ω

50Ω

4409-035

Figure 26. Disabling the ADCMP572 Latch Feature

V

V

= 3.3V

CCI

V

= 2.5V/3.3V 2.5V/3.3V

CCO

50Ω50Ω

V

IN

V

TH

+

ADCMP572

–

LATCH
INPUTS

GND = –1V

Figure 23. Comparator with ±1 V Input Range and

Q

Q

04409-031

V

P

V

N

Figure 27. Disabling the ADCMP573 Latch Feature

2.5 V or 3.3 V CML Outputs

V

= 5.2V

CCI

V

= 3.3V/5.2V 3.3V/5.2V

CCO

50Ω50Ω

V

IN

V

TH

ADCMP572

LATCH
INPUTS

Figure 24. Comparator with 0 V to 3 V Input Range and

3.3 V or 5.2 V Positive CML Outputs

Q

Q

04409-032

Figure 28. Adding Hysteresis Using the HYS Control Pin

= 5.2V = V

CCI

ADCMP573

500Ω

V

CCO

V

CCI

V

CCO

ADCMP572

HYS

CCO

VTT = 3.2V

0Ω TO 5kΩ

50Ω 50Ω

V

CCO

50Ω 50Ω

04409-036

04409-048

Rev. A | Page 12 of 16

ADCMP572/ADCMP573

TIMING INFORMATION

Figure 29 illustrates the ADCMP572/ADCMP573 compare and latch timing relationships. Tab le 4 provides definitions of the terms
shown in the figure.

LATCH ENABLE

50%

LATCH ENABLE

DIFFERENTIAL

INPUT VOLTAGE

Q OUTPUT

Q OUTPUT

t

S

t

H

V

IN

V

OD

t

PDL

t

PDH

t

R

t

PL

t

PLOH

t

F

t

PLOL

Figure 29. System Timing Diagram

Table 4. Timing Descriptions

Symbol Timing Description

t

Input to output high delay

PDH

Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.

t

Input to output low delay

PDL

Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.

t

Latch enable to output high delay

PLOH

Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.

t

Latch enable to output low delay

PLOL

Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.

tH Minimum hold time

Minimum time after the negative transition of the latch enable signal that the input
signal must remain unchanged to be acquired and held at the outputs.

tPL Minimum latch enable pulse width

Minimum time that the latch enable signal must be high to acquire an input signal
change.

tS Minimum setup time

Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs.

tR Output rise time

Amount of time required to transition from a low to a high output as measured at the
20% and 80% points.

tF Output fall time

Amount of time required to transition from a high to a low output as measured at the
20% and 80% points.

VOD Voltage overdrive Difference between the input voltages VA and VB.

V

50%

50%

± V

N

OS

04409-003

Rev. A | Page 13 of 16

ADCMP572/ADCMP573

OUTLINE DIMENSIONS

0.50

0.40

PIN 1

INDICATOR

1.00

0.85

0.80

SEATING

PLANE

12° MAX

3.00

BSC SQ

TOP

VIEW

0.30

0.23

0.18

*

COMPLIANT

EXCEPT FOR EXPOSED PAD DIMENSION.

2.75

BSC SQ

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

TO

JEDEC STANDARDS MO-220-VEED-2

0.45

0.50

BSC

1.50 REF

0.60 MAX

13

12

9

8

FOR PROPER CONNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

Figure 30. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

3 mm × 3 mm Body, Very Thin Quad

(CP-16-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

ADCMP572BCP-WP −40°C to +85°C 16-Lead LFCSP_VQ CP-16-2 G03
ADCMP572BCPZ-WP1 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-2 G0Y
ADCMP572BCP-R2 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-2 G03
ADCMP572BCP-RL7 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-2 G03
ADCMP572BCPZ-R21 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-2 G0Y
ADCMP572BCPZ-RL71 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-2 G0Y
ADCMP573BCP-WP −40°C to +85°C 16-Lead LFCSP_VQ CP-16-2 G05
ADCMP573BCPZ-WP1 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-2 G0Z
ADCMP573BCP-R2 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-2 G05
ADCMP573BCP-RL7 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-2 G05
ADCMP573BCPZ-R21 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-2 G0Z
ADCMP573BCPZ-RL71 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-2 G0Z
EVAL-ADCMP572BCPZ1 Evaluation Board
EVAL-ADCMP573BCPZ1 Evaluation Board

1

Z = RoHS Compliant Part.

(BOTTOM VIEW)

EXPOSED

PAD

0.30

16

1

4

5

PIN 1
INDICATOR

*

1.45

1.30 SQ

1.15

0.25 MIN

072208-A

Rev. A | Page 14 of 16

ADCMP572/ADCMP573

NOTES

Rev. A | Page 15 of 16

ADCMP572/ADCMP573

NOTES

© 2005–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04409–0–4/09(A)

Rev. A | Page 16 of 16