Analog Devices ADCMP572 3 prb Datasheet

Ultrafast 3.3 V

Preliminary Technical Data

FEATURES

3.3 V/5.2 V single-supply operation
150 ps propagation delay
15 ps overdrive and slew rate dispersion
8 GHz equivalent input risetime bandwidth
80 ps minimum pulse width
35 ps typical output rise/fall
10 ps deterministic jitter (DJ)

200 fs random jitter (RJ)
On-chip terminations at both input pins
Robust inputs with no output phase reversal
Resistor programmable hysteresis
Differential latch control
Power supply rejection > 70 dB

APPLICATIONS

Automatic test equipment (ATE)
High speed instrumentation
Pulse spectroscopy
Medical imaging and diagnostics
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Clock and data signal restoration

GENERAL DESCRIPTION

Single-Supply Comparators

ADCMP572/ADCMP573

FUNCTIONAL BLOCK DIAGRAM

V

TERMINATION

TP

VP NONINVERTING

V

N

V

TN

INPUT

INVERTING

INPUT

TERMINATION

V

CCI

ADCMP572
ADCMP573

Figure 1.

V

CML/
RSPECL

LE INPUT
LE INPUTHYS

CCO

Q OUTPUT

Q OUTPUT

04409-0-025

The ADCMP572/ADCMP573 are ultrafast comparators
fabricated on Analog Devices, Inc.’s proprietary XFCB3 Silicon
Germanium (SiGe) bipolar process. The ADCMP572 features
CML output drivers, and the ADCMP573 features reduced
swing PECL (RSPECL) output drivers.

Both devices offer 150 ps propagation delay and 100 ps
minimum pulse width for 10 Gbps operation with 200 fs RMS
random jitter (RJ). Overdrive and slew rate dispersion is
typically less than 15 ps.

A flexible power supply scheme allows either device to operate
with a single +3.3 V positive supply and a −0.2 V to +1.2 V
input signal range, or with split input/output supplies to
support a wider −0.2 V to +3.2 V input signal range and an
independent range of output levels. 50 Ω on-chip termination

Rev. PrB

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

resistors are provided at both inputs with the optional capability
to leave open (on an individual pin basis) for applications
requiring high impedance inputs.

The CML output stage is designed to directly drive 400 mV into
50 Ω transmission lines terminated to between 3.3 V to 5.2 V.
The RSPECL output stage is designed to drive 400 mV into
50 Ω terminated to V

− 2 V and is compatible with several

CCO

commonly used PECL logic families. The comparator input
stage offers robust protection against large input overdrive, and
the outputs do not phase reverse when the valid input signal
range is exceeded. High speed latch and programmable
hysteresis features are also provided.

The ADCMP572/ADCMP573 are available in a 16-lead LFCSP
package.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

ADCMP572/ADCMP573 Preliminary Technical Data

TABLE OF CONTENTS

Electrical Characteristics ................................................................. 3

Optimizing High Speed Performance ..................................... 10

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Application Information.................................................................. 9

Power/Ground Layout and Bypassing....................................... 9

CML/RSPECL Output Stage ....................................................... 9

Using/Disabling the Latch Feature............................................. 9

REVISION HISTORY

6/04—Revision PrB: Preliminary Version

2/04—Revision PrA: Preliminary Version

Comparator Propagation Delay Dispersion ........................... 10

Comparator Hysteresis .............................................................. 11

Minimum Input Slew Rate Requirement................................ 11

Typical Application Circuits .......................................................... 12

Timing Information ....................................................................... 13

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. PrB | Page 2 of 16

Preliminary Technical Data ADCMP572/ADCMP573

ELECTRICAL CHARACTERISTICS

V

= V

CCI

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

DC INPUT CHARACTERISTICS

LATCH ENABLE CHARACTERISTICS

DC OUTPUT CHARACTERISTICS

= 3.3 V, TA = 25°C, unless otherwise noted.

CCO

Input Voltage Range VP, V
V

V

N

= 3.3 V, V

CCI

= 5.2 V, V

CCI

= 3.3 V −0.2 +1.2 V

CCO

= 3.3 V −0.2 +3.2 V

CCO

Input Differential Voltage −1.2 +1.2 V
Input Offset Voltage V
Offset Voltage Tempco

∆V

Input Bias Current IP, I

OS

OS

N

−5.0 ±2.0 +5.0 mV

10.0 µV/°C

/dT

Open termination −50.0 −25.0 0.0 µA
Input Bias Current Tempco 50.0 nA/°C
Input Offset Current −5.0 ±2.0 +5.0 µA
Input Capacitance CP, C

TBD pF

N

Input Impedance 47.5 50 52.5 Ω
Input Resistance, Differential Mode Open termination 50 kΩ
Input Resistance, Common Mode Open termination 500 kΩ
Active Gain A

V

Common-Mode Rejection CMRR

Hysteresis

54 dB

V

= 3.3 V, V

CCI

V

= 0.0 V to 1.0 V

CM

= 5.2 V, V

V

CCI

V

= 0.0 V to 3.0 V

CM

R

= ∞

HYS

= 3.3 V,

CCO

= 3.3 V,

CCO

50 dB

40 dB

±1 mV

ADCMP572

Latch Enable Input Range 2.8 V

+0.2 V

CCO

Latch Enable Input Differential 0.2 0.4 0.5 V
Latch Setup Time t
Latch Hold Time t

S

H

VOD = 100 mV 15 ps

VOD = 100 mV 0 ps
ADCMP573

Latch Enable Input Range 1.8 V

−0.6 V

CCO

Latch Enable Input Differential 0.2 0.4 0.5 V
Latch Setup Time t
Latch Hold Time t

S

H

VOD = 100 mV 0 ps

VOD = 100 mV 50 ps
Latch Enable Input Impedance 47.5 50.0 52.5 Ω
Latch to Output Delay

Latch Minimum Pulse Width t

t

PLOH,

t

PLOL

PL

VOD = 100 mV 150 ps

VOD = 100 mV 100 ps

ADCMP572 (CML)

Output Impedance Z
Output Voltage High Level V
Output Voltage Low Level V

OUT

OH

OL

Output Voltage Differential 50 Ω terminate to V
Temperature Coefficient, V

Temperature Coefficient, V

OH

OL

∆VOH/dT
∆VOL/dT

−8 mA < I

< 8 mA 47.5 50.0 52.5 Ω

OUT

50 Ω terminate to V

50 Ω terminate to V

50 Ω terminate to V

50 Ω terminate to V

V

CCO

CCO

CCO

CCO

CCO

−0.10 V

CCO

−0.05 V

CCO

CCO

V
VOH−0.45 VOH−0.40 VOH−0.35 V
350 400 450 mV
TBD mV/°C

TBD mV/°C

ADCMP573 (RSPECL)

Output Voltage High Level V
Output Voltage Low Level V

OH

OL

Output Voltage Differential 50 Ω terminate to V

50 Ω terminate to V
50 Ω terminate to V

−2.0 V

CCO

−2.0 VOH−0.45 VOH−0.40 VOH−0.35 V

CCO

−2.0 350 400 450 mV

CCO

−0.90 V

CCO

−0.80 V

CCO

−0.70 V

CCO

Rev. PrB | Page 3 of 16

ADCMP572/ADCMP573 Preliminary Technical Data

Parameter Symbol Conditions Min Typ Max Unit

AC PERFORMANCE

Propagation Delay t

PD

V
V
Propagation Delay Tempco

Prop Delay Skew—Rising Transition

∆t

PD

V

to Falling Transition

Slew Rate Dispersion 2 V/ns to 10 V/ns 15 ps
Pulse Width Dispersion 100 ps to 5 ns 5 ps

Common-Mode Dispersion VOD=0.4V, 0.0 V < VCM < 1.0 V 5 ps/V
Equivalent Input Bandwidth

1

BW

EQ

Toggle Rate > 50% Output Swing 12.5 Gbps
Deterministic Jitter DJ

Deterministic Jitter DJ

RMS Random Jitter RJ
Minimum Pulse Width PW

Minimum Pulse Width PW
Rise Time t

Fall Time t

MIN

MIN

R

F

POWER SUPPLY

Input Supply Voltage Range V
Output Supply Voltage Range V
Positive Supply Differential

V

−V

CCI

CCO

CCI

CCO

ADCMP572 (CML)

+

I

VCCI

I

VCCO

D

ADCMP573 (RSPECL)

Positive Supply Current

Power Dissipation P

Power Supply Rejection—V

CCI

I

VCCI

I

VCCO

D

PSR

+

VCCI

1

Equivalent Input Bandwidth assumes a simple first-order response and is calculated with the following formula: BWEQ = 0.22/•(tr

transition time of a quasi-Gaussian signal applied to the comparator input and tr

V

= 3.3 V, VOD = 200 mV 150 ps

CCI

= 3.3 V, VOD = 20 mV 165 ps

CCI

= 5.2 V, VOD = 200 mV 145 ps

CCI

0.5 ps/°C

/dT

= 200 mV, 5 V/ns 10 ps

OD

50 mV < VOD < 1.0 V, 5 V/ns 10 Overdrive Dispersion
10 mV < V

V

= 3.3 V, 1 V/ns, V

CCI

V

= 5.2 V, 1 V/ns, VCM = 0 V 10

CCI

0.0 V to 400 mV input
t

= tF = 25 ps, 20/80

R

= 200 mV, 5 V/ns,

V

OD

PRBS

= 200 mV, 5 V/ns,

V

OD

PRBS

VOD = 200 mV, 5 V/ns, 1.25 GHz

∆tPD/∆PW < 5 ps
∆tPD/∆PW < 10 ps

< 1.0 V, 5 V/ns 15

OD

= 0 V 5 Duty Cycle Dispersion

CM

8.0 GHz

31

−1 NRZ, 4 Gbps

31

−1 NRZ, 10 Gbps

0.2 ps
100 ps

80 ps

10

TBD

ps

ps

ps
ps

ps

20/80 35 ps
20/80 35 ps

3.1 5.4 V

3.1 5.4 V

−0.2 +2.3 V

V

= 3.3 V, V

CCI

= 3.3 V,

CCO

terminate 50 Ω to V
V

= 5.2 V, V

CCI

= 5.2 V,

CCO

terminate 50 Ω to V
V

= 3.3 V, V

CCI

= 3.3 V,

CCO

terminate 50 Ω to V
V

= 5.2 V, V

CCI

= 5.2 V,

CCO

terminate 50 Ω to V

V

= 3.3 V, V

CCI

50 Ω to V
V

= 5.2 V, V

CCI

50 Ω to V
V

= 3.3 V, V

CCI

50 Ω to V
V

= 5.2 V, V

CCI

50 Ω to V
V

= 3.3 V ±5%,

CCI

V

= 3.3 V

CCO

= 3.3 V,

CCO

− 2 V

CCO

= 5.2 V,

CCO

− 2V

CCO

= 3.3 V,

CCO

− 2 V

CCO

= 5.2 V,

CCO

− 2 V

CCO

is the effective transition time digitized by the comparator.

COMP

CCO

CCO

CCO

CCO

44 52 Positive Supply Current

44 52

145 160 Power Dissipation P

240 265

66 74

68 76

145 160

175 195

74 dB

2

2

-tr

), where trIN is the 20/80

COMP

IN

mA

mW

mA

mW

Rev. PrB | Page 4 of 16

Preliminary Technical Data ADCMP572/ADCMP573

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

SUPPLY VOLTAGES

Input Supply Voltage (V
Output Supply Voltage

(V

to GND)

CCO

Positive Supply Differential

− V

(V

CCI

CCO

)

to GND) −0.5 V to +6.0 V

CCI

−0.5 V to +6.0 V

−0.5 V to +3.5 V

INPUT VOLTAGES

Input Voltage −0.5 V to V
Differential Input Voltage

±(V

CCI

Input Voltage, Latch Enable −0.5 V to V

CCI

+ 0.5 V)

CCO

+ 0.5 V

+ 0.5 V

HYSTERESIS CONTROL PIN

Applied Voltage (HYS to GND) −0.5 V to +1.5 V
Maximum Input/Output Current

±1 mA

OUTPUT CURRENT

ADCMP572 (CML)

±20 mA

ADCMP573 (RSPECL) −35 mA

TEMPERATURE

Operating Temperature, Ambient −40°C to +85°C
Operating Temperature, Junction 125°C
Storage Temperature Range −65°C to +150°C

Thermal Considerations

The ADCMP572/ADCMP573 LFCSP 16-lead package has a θ
(junction to ambient thermal resistance) of 70°C/W in still air.

Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. PrB | Page 5 of 16