Ultrafast 3.3 V
Preliminary Technical Data
FEATURES
3.3 V/5.2 V single-supply operation
150 ps propagation delay
15 ps overdrive and slew rate dispersion
8 GHz equivalent input risetime bandwidth
80 ps minimum pulse width
35 ps typical output rise/fall
10 ps deterministic jitter (DJ)
200 fs random jitter (RJ)
On-chip terminations at both input pins
Robust inputs with no output phase reversal
Resistor programmable hysteresis
Differential latch control
Power supply rejection > 70 dB
APPLICATIONS
Automatic test equipment (ATE)
High speed instrumentation
Pulse spectroscopy
Medical imaging and diagnostics
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Clock and data signal restoration
GENERAL DESCRIPTION
Single-Supply Comparators
ADCMP572/ADCMP573
FUNCTIONAL BLOCK DIAGRAM
V
TERMINATION
TP
VP NONINVERTING
V
N
V
TN
INPUT
INVERTING
INPUT
TERMINATION
V
CCI
ADCMP572
ADCMP573
Figure 1.
V
CML/
RSPECL
LE INPUT
LE INPUTHYS
CCO
Q OUTPUT
Q OUTPUT
04409-0-025
The ADCMP572/ADCMP573 are ultrafast comparators
fabricated on Analog Devices, Inc.’s proprietary XFCB3 Silicon
Germanium (SiGe) bipolar process. The ADCMP572 features
CML output drivers, and the ADCMP573 features reduced
swing PECL (RSPECL) output drivers.
Both devices offer 150 ps propagation delay and 100 ps
minimum pulse width for 10 Gbps operation with 200 fs RMS
random jitter (RJ). Overdrive and slew rate dispersion is
typically less than 15 ps.
A flexible power supply scheme allows either device to operate
with a single +3.3 V positive supply and a −0.2 V to +1.2 V
input signal range, or with split input/output supplies to
support a wider −0.2 V to +3.2 V input signal range and an
independent range of output levels. 50 Ω on-chip termination
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
resistors are provided at both inputs with the optional capability
to leave open (on an individual pin basis) for applications
requiring high impedance inputs.
The CML output stage is designed to directly drive 400 mV into
50 Ω transmission lines terminated to between 3.3 V to 5.2 V.
The RSPECL output stage is designed to drive 400 mV into
50 Ω terminated to V
− 2 V and is compatible with several
CCO
commonly used PECL logic families. The comparator input
stage offers robust protection against large input overdrive, and
the outputs do not phase reverse when the valid input signal
range is exceeded. High speed latch and programmable
hysteresis features are also provided.
The ADCMP572/ADCMP573 are available in a 16-lead LFCSP
package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
ADCMP572/ADCMP573 Preliminary Technical Data
TABLE OF CONTENTS
Electrical Characteristics ................................................................. 3
Optimizing High Speed Performance ..................................... 10
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Application Information.................................................................. 9
Power/Ground Layout and Bypassing....................................... 9
CML/RSPECL Output Stage ....................................................... 9
Using/Disabling the Latch Feature............................................. 9
REVISION HISTORY
6/04—Revision PrB: Preliminary Version
2/04—Revision PrA: Preliminary Version
Comparator Propagation Delay Dispersion ........................... 10
Comparator Hysteresis .............................................................. 11
Minimum Input Slew Rate Requirement................................ 11
Typical Application Circuits .......................................................... 12
Timing Information ....................................................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Rev. PrB | Page 2 of 16
Preliminary Technical Data ADCMP572/ADCMP573
ELECTRICAL CHARACTERISTICS
V
= V
CCI
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
DC INPUT CHARACTERISTICS
LATCH ENABLE CHARACTERISTICS
DC OUTPUT CHARACTERISTICS
= 3.3 V, TA = 25°C, unless otherwise noted.
CCO
Input Voltage Range VP, V
V
V
N
= 3.3 V, V
CCI
= 5.2 V, V
CCI
= 3.3 V −0.2 +1.2 V
CCO
= 3.3 V −0.2 +3.2 V
CCO
Input Differential Voltage −1.2 +1.2 V
Input Offset Voltage V
Offset Voltage Tempco
∆V
Input Bias Current IP, I
OS
OS
N
−5.0 ±2.0 +5.0 mV
10.0 µV/°C
/dT
Open termination −50.0 −25.0 0.0 µA
Input Bias Current Tempco 50.0 nA/°C
Input Offset Current −5.0 ±2.0 +5.0 µA
Input Capacitance CP, C
TBD pF
N
Input Impedance 47.5 50 52.5 Ω
Input Resistance, Differential Mode Open termination 50 kΩ
Input Resistance, Common Mode Open termination 500 kΩ
Active Gain A
V
Common-Mode Rejection CMRR
Hysteresis
54 dB
V
= 3.3 V, V
CCI
V
= 0.0 V to 1.0 V
CM
= 5.2 V, V
V
CCI
V
= 0.0 V to 3.0 V
CM
R
= ∞
HYS
= 3.3 V,
CCO
= 3.3 V,
CCO
50 dB
40 dB
±1 mV
ADCMP572
Latch Enable Input Range 2.8 V
+0.2 V
CCO
Latch Enable Input Differential 0.2 0.4 0.5 V
Latch Setup Time t
Latch Hold Time t
S
H
VOD = 100 mV 15 ps
VOD = 100 mV 0 ps
ADCMP573
Latch Enable Input Range 1.8 V
−0.6 V
CCO
Latch Enable Input Differential 0.2 0.4 0.5 V
Latch Setup Time t
Latch Hold Time t
S
H
VOD = 100 mV 0 ps
VOD = 100 mV 50 ps
Latch Enable Input Impedance 47.5 50.0 52.5 Ω
Latch to Output Delay
Latch Minimum Pulse Width t
t
PLOH,
t
PLOL
PL
VOD = 100 mV 150 ps
VOD = 100 mV 100 ps
ADCMP572 (CML)
Output Impedance Z
Output Voltage High Level V
Output Voltage Low Level V
OUT
OH
OL
Output Voltage Differential 50 Ω terminate to V
Temperature Coefficient, V
Temperature Coefficient, V
OH
OL
∆VOH/dT
∆VOL/dT
−8 mA < I
< 8 mA 47.5 50.0 52.5 Ω
OUT
50 Ω terminate to V
50 Ω terminate to V
50 Ω terminate to V
50 Ω terminate to V
V
CCO
CCO
CCO
CCO
CCO
−0.10 V
CCO
−0.05 V
CCO
CCO
V
VOH−0.45 VOH−0.40 VOH−0.35 V
350 400 450 mV
TBD mV/°C
TBD mV/°C
ADCMP573 (RSPECL)
Output Voltage High Level V
Output Voltage Low Level V
OH
OL
Output Voltage Differential 50 Ω terminate to V
50 Ω terminate to V
50 Ω terminate to V
−2.0 V
CCO
−2.0 VOH−0.45 VOH−0.40 VOH−0.35 V
CCO
−2.0 350 400 450 mV
CCO
−0.90 V
CCO
−0.80 V
CCO
−0.70 V
CCO
Rev. PrB | Page 3 of 16
ADCMP572/ADCMP573 Preliminary Technical Data
Parameter Symbol Conditions Min Typ Max Unit
AC PERFORMANCE
Propagation Delay t
PD
V
V
Propagation Delay Tempco
Prop Delay Skew—Rising Transition
∆t
PD
V
to Falling Transition
Slew Rate Dispersion 2 V/ns to 10 V/ns 15 ps
Pulse Width Dispersion 100 ps to 5 ns 5 ps
Common-Mode Dispersion VOD=0.4V, 0.0 V < VCM < 1.0 V 5 ps/V
Equivalent Input Bandwidth
1
BW
EQ
Toggle Rate > 50% Output Swing 12.5 Gbps
Deterministic Jitter DJ
Deterministic Jitter DJ
RMS Random Jitter RJ
Minimum Pulse Width PW
Minimum Pulse Width PW
Rise Time t
Fall Time t
MIN
MIN
R
F
POWER SUPPLY
Input Supply Voltage Range V
Output Supply Voltage Range V
Positive Supply Differential
V
−V
CCI
CCO
CCI
CCO
ADCMP572 (CML)
+
I
VCCI
I
VCCO
D
ADCMP573 (RSPECL)
Positive Supply Current
Power Dissipation P
Power Supply Rejection—V
CCI
I
VCCI
I
VCCO
D
PSR
+
VCCI
1
Equivalent Input Bandwidth assumes a simple first-order response and is calculated with the following formula: BWEQ = 0.22/•(tr
transition time of a quasi-Gaussian signal applied to the comparator input and tr
V
= 3.3 V, VOD = 200 mV 150 ps
CCI
= 3.3 V, VOD = 20 mV 165 ps
CCI
= 5.2 V, VOD = 200 mV 145 ps
CCI
0.5 ps/°C
/dT
= 200 mV, 5 V/ns 10 ps
OD
50 mV < VOD < 1.0 V, 5 V/ns 10 Overdrive Dispersion
10 mV < V
V
= 3.3 V, 1 V/ns, V
CCI
V
= 5.2 V, 1 V/ns, VCM = 0 V 10
CCI
0.0 V to 400 mV input
t
= tF = 25 ps, 20/80
R
= 200 mV, 5 V/ns,
V
OD
PRBS
= 200 mV, 5 V/ns,
V
OD
PRBS
VOD = 200 mV, 5 V/ns, 1.25 GHz
∆tPD/∆PW < 5 ps
∆tPD/∆PW < 10 ps
< 1.0 V, 5 V/ns 15
OD
= 0 V 5 Duty Cycle Dispersion
CM
8.0 GHz
31
−1 NRZ, 4 Gbps
31
−1 NRZ, 10 Gbps
0.2 ps
100 ps
80 ps
10
TBD
ps
ps
ps
ps
ps
20/80 35 ps
20/80 35 ps
3.1 5.4 V
3.1 5.4 V
−0.2 +2.3 V
V
= 3.3 V, V
CCI
= 3.3 V,
CCO
terminate 50 Ω to V
V
= 5.2 V, V
CCI
= 5.2 V,
CCO
terminate 50 Ω to V
V
= 3.3 V, V
CCI
= 3.3 V,
CCO
terminate 50 Ω to V
V
= 5.2 V, V
CCI
= 5.2 V,
CCO
terminate 50 Ω to V
V
= 3.3 V, V
CCI
50 Ω to V
V
= 5.2 V, V
CCI
50 Ω to V
V
= 3.3 V, V
CCI
50 Ω to V
V
= 5.2 V, V
CCI
50 Ω to V
V
= 3.3 V ±5%,
CCI
V
= 3.3 V
CCO
= 3.3 V,
CCO
− 2 V
CCO
= 5.2 V,
CCO
− 2V
CCO
= 3.3 V,
CCO
− 2 V
CCO
= 5.2 V,
CCO
− 2 V
CCO
is the effective transition time digitized by the comparator.
COMP
CCO
CCO
CCO
CCO
44 52 Positive Supply Current
44 52
145 160 Power Dissipation P
240 265
66 74
68 76
145 160
175 195
74 dB
2
2
-tr
), where trIN is the 20/80
COMP
IN
mA
mW
mA
mW
Rev. PrB | Page 4 of 16
Preliminary Technical Data ADCMP572/ADCMP573
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
SUPPLY VOLTAGES
Input Supply Voltage (V
Output Supply Voltage
(V
to GND)
CCO
Positive Supply Differential
− V
(V
CCI
CCO
)
to GND) −0.5 V to +6.0 V
CCI
−0.5 V to +6.0 V
−0.5 V to +3.5 V
INPUT VOLTAGES
Input Voltage −0.5 V to V
Differential Input Voltage
±(V
CCI
Input Voltage, Latch Enable −0.5 V to V
CCI
+ 0.5 V)
CCO
+ 0.5 V
+ 0.5 V
HYSTERESIS CONTROL PIN
Applied Voltage (HYS to GND) −0.5 V to +1.5 V
Maximum Input/Output Current
±1 mA
OUTPUT CURRENT
ADCMP572 (CML)
±20 mA
ADCMP573 (RSPECL) −35 mA
TEMPERATURE
Operating Temperature, Ambient −40°C to +85°C
Operating Temperature, Junction 125°C
Storage Temperature Range −65°C to +150°C
Thermal Considerations
The ADCMP572/ADCMP573 LFCSP 16-lead package has a θ
(junction to ambient thermal resistance) of 70°C/W in still air.
Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
JA
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrB | Page 5 of 16
ADCMP572/ADCMP573 Preliminary Technical Data
V
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CCI
V
GND14HYS13GND
16
15
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 V
2 V
3 V
4 V
5, 16 V
6
TP
P
N
TN
CCI
LE Latch Enable Input Pin, Inverting Side.
Termination Resistor Return Pin for VP Input.
Noninverting Analog Input.
Inverting Analog Input.
Termination Resistor Return Pin for VN Input.
Positive Supply Voltage for Input Stage.
In compare mode (
In latch mode (
placed in latch mode.
7 LE
Latch Enable Input Pin, Noninverting Side.
In compare mode (LE = high), the output tracks changes at the input of the comparator.
In latch mode (LE = low), the output reflects the input state just prior to the comparator’s being
placed in latch mode. LE must be driven in compliment with
8 V
CCO/VTT
Termination Return Pin for the LE/LE Input Pins.
For the ADCMP572 (CML output stage), this pin should be connected to the positive V
For the ADCMP573 (RSPECL output stage), this pin should be connected to the V
termination potential.
13, 15 GND Ground.
9, 12 V
10
CCO
Q Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than
Positive Supply Voltage for the CML/RSPECL Output Stage.
the analog voltage at the inverting input, V
LE/
LE description (Pins 6 and 7) for more information.
11 Q
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input V
than the analog voltage at the inverting input, V
the LE/
LE description (Pins 6 and 7) for more information.
14 HYS
Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect to GND with a
suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 7 for proper sizing of
hysteresis control resistor.
R
HYS
Heatsink N/C
The metallic back surface of the package is not electrically connected to any part of the circuit, and it
can be left floating for best electrical isolation between the package handle and the substrate of the
die. But it can also be soldered to the application board if improved thermal and/or mechanical
stability is desired.
PIN1
1
V
TP
ADCMP572
2
V
P
ADCMP573
3
V
N
TN
4
TOP VIEW
(Not to Scale)
5
6LE7LE8
CCI
V
Figure 2. ADCMP572/ADCMP573 Pin Configuration
LE = low), the output tracks changes at the input of the comparator.
LE = high), the output reflects the input state just prior to the comparator’s being
LE must be driven in compliment with LE.
12
V
CCO
11
Q
10
Q
9
V
CCO
TT
/V
CCO
V
04409-0-026
LE.
supply.
CCO
– 2 V
CCO
, provided the comparator is in compare mode. See the
N
is greater
, provided the comparator is in compare mode. See
N
P
Rev. PrB | Page 6 of 16
Preliminary Technical Data ADCMP572/ADCMP573
TYPICAL PERFORMANCE CHARACTERISTICS
V
= V
CCI
= 3.3 V, TA = 25°C, unless otherwise noted.
CCO
20
15
39.0
38.5
38.0
10
5
PROPAGATION DELAY ERROR (ps)
0
0 50 100 150 200 250
INPUT OVERDRIVE VOLTAGE (mV)
Figure 3. Propagation Delay vs. Input Overdrive
158.5
158.0
157.5
157.0
156.5
PROPAGATION DELAY (ps)
156.0
155.5
0.4 0.60 0.2 0.8 1.0 1.2
INPUT COMMON-MODE VOLTAGE (V)
Figure 4. Propagation Delay vs. Input Common Mode
04409-0-039
04409-0-040
37.5
37.0
RISE/FALL TIME (ps)
36.5
36.0
Figure 6. Rise/Fall Time vs. Temperature
60
50
40
30
20
HYSTERESIS (mV)
10
0
Figure 7. Hysteresis vs. R
200–40 –20–60 40 60 80 100
TEMPERATURE (°C)
2301 456
R
(kΩ)
HYS
Control Resistor
HYS
04409-0-042
04409-0-043
160
158
156
154
152
150
PROPAGATION DELAY (ps)
148
146
200–40 –20–60 40 60 80 100
TEMPERATURE (°C)
04409-0-041
Figure 5. Propagation Delay vs. Temperature
–15.0
–15.5
A)
µ
–16.0
–16.5
–17.0
–17.5
INPUT BIAS CURRENT (
–18.0
–18.5
–0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5
VP INPUT VOLTAGE (VN = –0.2V)
Figure 8. Input Bias Current vs. Input Differential
04409-0-044
Rev. PrB | Page 7 of 16
ADCMP572/ADCMP573 Preliminary Technical Data
–16.2
380
–16.3
A)
µ
–16.4
–16.5
–16.6
–16.7
INPUT BIAS CURRENT (
–16.8
–16.9
200–40 –20–60 40 60 80 100
TEMPERATURE (°C)
Figure 9. Input Bias Current vs. Temperature
04409-0-045
379
378
377
376
OUTPUT LEVELS (mV)
375
374
373
200–40 –20–60 40 60 80 100
TEMPERATURE (°C)
04409-0-046
Figure 11. Output Levels vs. Temperature
Figure 10. Input Offset Voltage vs. Temperature
Rev. PrB | Page 8 of 16
Preliminary Technical Data ADCMP572/ADCMP573
APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP572/ADCMP573 comparators are very high speed
SiGe devices. Consequently, it is essential to use proper high
speed design techniques to achieve the specified performance.
Of critical importance is the use of low impedance supply
planes, particularly the output supply plane (V
) and the
CCO
ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest
inductance return path for switching currents ensures the best
possible performance in the target application.
It is also important to adequately bypass the input and output
supplies. A 1 µF electrolytic bypass capacitor should be placed
within several inches of each power supply pin to ground. In
addition, multiple high quality 0.1 µF bypass capacitors should
be placed as close as possible to each of the V
CCI
and V
CCO
supply pins and should be connected to the GND plane with
redundant vias. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should also be strictly avoided to maximize
the effectiveness of the bypass at high frequencies.
If the input and output supplies are connected separately such
≠ V
that V
CCI
, then care should be taken to bypass each of
CCO
these supplies separately to the GND plane. A bypass capacitor
should not be connected between them. It is recommended that
the GND plane separate the V
CCI
and V
planes when the
CCO
circuit board layout is designed to minimize coupling between
the two supplies and to take advantage of the additional bypass
capacitance from each respective supply to the ground plane.
This enhances the performance when split input/output supplies
are used. If the input and output supplies are connected
= V
together for single-supply operation such that V
CCI
CCO
, then
coupling between the two supplies is unavoidable; however,
every effort should be made to keep the supply plane adjacent
to the GND plane to maximize the additional bypass capacitance
this arrangement provides.
CML/RSPECL OUTPUT STAGE
Specified propagation delay dispersion performance can be
achieved only by using proper transmission line terminations.
The outputs of the ADCMP572 are designed to directly drive
400 mV into 50 Ω cable or microstrip and/or stripline transmission lines properly terminated to the V
CML output stage is shown in the simplified schematic diagram
of Figure 12. The outputs are each back-terminated with 50 Ω
for best transmission line matching. The RSPECL outputs of the
ADCMP573 are illustrated in Figure 13 and should be terminated
− 2 V. As an alternative, Thevenin equivalent termina-
to V
CCO
tion networks may also be used in either case if the direct
termination voltage is not readily available. If high speed output
signals must be routed more than a centimeter, microstrip or
supply plane. The
CCO
stripline techniques are essential to ensure proper transition
times and to prevent output ringing and pulse-width dependant
propagation delay dispersion. For the most timing critical
applications where transmission line reflections pose the
greatest risk to performance, the ADCMP572 provides the best
match to 50 Ω output transmission paths.
V
CCO
Ω
50
Q
Q
16mA
GND
Figure 12. Simplified Schematic Diagram of
the ADCMP572 CML Output Stage
V
CCO
GND
Figure 13. Simplified Schematic Diagram of
the ADCMP573 RSPECL Output Stage
04409-0-037
Q
Q
04409-0-038
USING/DISABLING THE LATCH FEATURE
The latch inputs (LE/LE) are active low for latch mode, and are
internally terminated with 50 Ω resistors to Pin 8. This
corresponds to the V
pin for the ADCMP573. All V
the supply plane for maximum performance, and the V
should be connected externally to V
own low inductance plane. When using the ADCMP572, the
latch function can be disabled by connecting the
GND with an external pull-down resistor and leaving the LE
pin unconnected. To prevent excessive power dissipation, the
resistor should be 750 Ω when V
V
= 5.2 V. When using the ADCMP573 comparator, the latch
CCO
can be disabled by connecting the LE pin to V
supply for the ADCMP572 and the VTT
CCO
pins should be connected to
CCO
TT
– 2 V, preferably to its
CCO
LE
pin to
= 3.3 V, and 1.2 kΩ when
CCO
with an
CCO
pin
Rev. PrB | Page 9 of 16
ADCMP572/ADCMP573 Preliminary Technical Data
external 500 Ω resistor, and leaving the LE pin disconnected. In
this case, the resistor value does not depend on the chosen V
supply voltage, assuming the V
– 2 V.
V
CCO
pin is properly connected to
TT
CCO
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed comparator, proper design and layout
techniques are essential to obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit performance
and can often cause oscillation. Discontinuities along input and
output transmission lines can also severely limit the specified
pulse-width dispersion performance.
For applications working in a 50 Ω environment, input and
output matching has a significant impact on data dependant (or
deterministic) jitter (DJ) and pulse-width dispersion performance. The ADCMP572/ADCMP573 comparators provide
internal 50 Ω termination resistors for both V
and the ADCMP572 provides 50 Ω back terminated outputs.
The return side for each input termination is pinned out
separately with the V
and VTN pins, respectively. If a 50 Ω
TP
termination is desired at one or both of the V
and VTN pins can be connected (or disconnected) to
the V
TP
(from) the desired termination potential as required. The
termination potential should be carefully bypassed using high
quality bypass capacitors as discussed above to prevent undesired
aberrations on the input signal due to parasitic inductance in
the circuit board layout. If a 50 Ω input termination is not
desired, either one or both of the V
TP/VTN
be left disconnected. In this case, the pins should be left floating
with no external pull-downs or bypassing capacitors.
It should be understood that when leaving an input termination
disconnected, the internal resistor acts as a small stub on the
input transmission path and can cause problems for very high
speed inputs. Reflections should then be expected from the
comparator inputs because they no longer provide a matched
impedance to the input path leading to the device. It then
becomes important to back-match the drive source impedance
to the input transmission path to minimize multiple reflections.
For applications in which the comparator is very close to the
driving signal source, the source impedance should be minimized. High source impedance in combination with parasitic
input capacitance of the comparator could cause an undesirable
degradation in bandwidth at the input, thus degrading the overall
response. Although the ADCMP572/ ADCMP573 comparators
have been designed to minimize input capacitance, some parasitic
capacitance is inevitable. It is therefore recommended that the
drive source impedance be no more than 50 Ω for best high
speed performance.
and VN inputs,
P
inputs, then
P/VN
termination pins can
COMPARATOR PROPAGATION DELAY DISPERSION
The ADCMP572/ADCMP573 comparators are designed to
reduce propagation delay dispersion over a wide input overdrive
range of 5 mV to 500 mV. Propagation delay dispersion is a
variation in propagation delay that results from a change in the
degree of overdrive or slew rate (how far or how fast the input
signal exceeds the switching threshold).
Propagation delay dispersion is a specification that becomes
important in high speed time critical applications such as data
communication, automatic test and measurement, instrumentation, and event-driven applications such as pulse spectroscopy,
nuclear instrumentation, and medical imaging. Dispersion is
defined as the variation in propagation delay as the input overdrive conditions are changed (Figure 14 and Figure 15). For the
ADCMP572/ADCMP573, dispersion is typically <15 ps because
the overdrive is varied from 10 mV to 500 mV, and the input
slew rate is varied from 2 V/ns to 10 V/ns. This specification
applies for both positive and negative signals since the
ADCMP572/ADCMP573 has substantially equal delays for
either positive-going or negative-going inputs.
500mV OVERDRIVE
INPUT VOLTAGE
10mV OVERDRIVE
± V
V
N
OS
DISPERSION
Q/Q OUTPUT
Figure 14. Propagation Delay—Overdrive Dispersion
INPUT VOLTAGE
1V/ns
V
10V/ns
DISPERSION
Q/Q OUTPUT
Figure 15. Propagation Delay—Slew Rate Dispersion
04409-0-027
± V
N
OS
04409-0-028
Rev. PrB | Page 10 of 16
Preliminary Technical Data ADCMP572/ADCMP573
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in a
noisy environment or when the differential input amplitudes are
relatively small or slow moving. The transfer function for a
comparator with hysteresis is shown in Figure 16. If the input
voltage approaches the threshold (0.0 V in this example) from
the negative direction, the comparator switches from a low to a
high when the input crosses +V
becomes −V
the threshold −V
/2. The comparator remains in the high state until
H
/2 is crossed from the positive direction. In
H
this manner, noise centered on 0.0 V input does not cause the
comparator to switch states unless it exceeds the region
bounded by ±V
H
/2.
/2. The new switching threshold
H
connecting an external pull-down resistor from the HYS pin to
GND, a variable amount of hysteresis can be applied. Leaving
the HYS pin disconnected disables the feature, and hysteresis is
then less than 1 mV as specified. The maximum hysteresis that
can be applied using this method is approximately ±25 mV.
Figure 17 illustrates the amount of hysteresis applied as a
function of external resistor value. The advantages of applying
hysteresis in this manner are improved accuracy, stability, and
reduced component count. An external bypass capacitor is not
recommended on the HYS pin because it would likely degrade
the jitter performance of the device.
60
50
OUTPUT
V
OH
V
OL
–V
H
2
Figure 16. Comparator Hysteresis Transfer Function
0
INPUT
+V
H
2
04409-0-005
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. A limitation of this approach is that the amount of
hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that reduce high speed performance, and can even
induce oscillation in some cases.
The ADCMP572/ADCMP573 comparators offer a
programmable hysteresis feature that can significantly improve
the accuracy and stability of the desired hysteresis. By
40
30
20
HYSTERESIS (mV)
10
0
Figure 17. Hysteresis vs. R
2301 456
R
(kΩ)
HYS
Control Resistor
HYS
MINIMUM INPUT SLEW RATE REQUIREMENT
As with all high speed comparators, a minimum slew rate
requirement must be met to ensure that the device does not
oscillate as the input signal crosses the threshold. This
oscillation is due in part to the high input bandwidth of the
comparator and the feedback parasitics inherent in the package.
Analog Devices recommends a minimum slew rate of 50 V/µs
to ensure a clean output transition from the ADCMP572/
ADCMP573 comparators unless hysteresis is programmed as
discussed previously.
04409-0-043
Rev. PrB | Page 11 of 16
ADCMP572/ADCMP573 Preliminary Technical Data
VPV
TYPICAL APPLICATION CIRCUITS
V
3.3V
CCI
CCO
V
V
TP
V
V
IN
P
V
N
V
TN
V
ADCMP572
LATCH
INPUTS
50Ω 50Ω
Figure 18. Zero-Crossing Detector with 3.3 V CML Outputs
V
= 5.2V
CCI
V
CCO
V
TP
V
P
V
ADCMP572
N
N
V
TN
LATCH
INPUTS
Figure 19. LVDS to50 Ω Back-Terminated (RS)PECL Receiver
V
= 3.3V
CCI
V
= 2.5V/3.3V 2.5V/3.3V
CCO
V
IN
V
TH
+
ADCMP572
–
LATCH
INPUTS
GND = –1V
Figure 20. Comparator with ±1 V Input Range and
2.5 V or 3.3 V CML Outputs
Q
Q
04409-0-029
V
IN
V
TH
Figure 21. Comparator with 0 V to 3 V Input Range and
50Ω50Ω
Q
Q
04409-0-030
50Ω50Ω
Q
Q
04409-0-031
V
P
V
N
= 5.2V
CCI
V
= 3.3V/5.2V 3.3V/5.2V
CCO
ADCMP572
LATCH
INPUTS
3.3 V or 5.2 V Positive CML Outputs
V
CCI
V
= 3.3V 5V
CCO
75Ω
ADCMP572
LATCH
INPUTS
100Ω
100Ω
Figure 22. Interfacing 3.3 V CML to a 50 Ω
Ground Terminated Instrument
V
CCI
V
= 3.3V V
CCO
CCO
50Ω 50Ω
ADCMP572
V
CCO
750Ω
Figure 23. Disabling the Latch Feature
V
CCI
50Ω50Ω
50Ω
Q
Q
04409-0-032
50Ω
04409-0-035
04409-0-034
V
CCO
V
CCO
50Ω 50Ω
ADCMP572
HYS
0Ω TO 5kΩ
04409-0-036
Figure 24. Adding Hysteresis Using the HYS Control Pin
Rev. PrB | Page 12 of 16
Preliminary Technical Data ADCMP572/ADCMP573
TIMING INFORMATION
Figure 25 illustrates the ADCMP572/ADCMP573 compare and
latch timing relationships. Table 4 provides definitions of the
terms shown in the figure.
LATCH ENABLE
50%
LATCH ENABLE
t
S
t
V
DIFFERENTIAL
INPUT VOLTAGE
Q OUTPUT
Q OUTPUT
IN
V
OD
t
PDL
t
PDH
Figure 25. System Timing Diagram
Table 4. Timing Descriptions
Symbol Timing Description
t
PDH
Input to output high delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
t
PDL
Input to output low delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
t
PLOH
Latch enable to output high delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
t
PLOL
Latch enable to output low delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
t
H
Minimum hold time
Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.
t
PL
t
S
Minimum latch enable pulse width Minimum time that the latch enable signal must be high to acquire an input signal change.
Minimum setup time
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs.
t
R
Output rise time
Amount of time required to transition from a low to a high output as measured at the
20% and 80% points.
t
F
Output fall time
Amount of time required to transition from a high to a low output as measured at the
20% and 80% points.
V
OD
Voltage overdrive Difference between the input voltages VA and VB.
t
PL
H
V
± V
N
OS
t
PLOH
50%
t
F
50%
t
PLOL
t
R
04409-0-003
Rev. PrB | Page 13 of 16
ADCMP572/ADCMP573 Preliminary Technical Data
OUTLINE DIMENSIONS
0.50
0.40
PIN 1
INDICATOR
1.00
0.85
0.80
SEATING
PLANE
12° MAX
3.00
BSC SQ
TOP VIEW
0.30
0.23
0.18
2.75
BSC SQ
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.20 REF
*
COMPLIANTTO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION
0.45
0.50
BSC
1.50 REF
0.60 MAX
13
12
9
8
Figure 26. 16-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-16)
Dimensions shown in millimeters
BOTTOM
VIEW
0.30
16
1
4
5
PIN 1 INDICATOR
1.65
*
1.50 SQ
1.35
0.25 MIN
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADCMP572BCP −40°C to 85°C LFCSP-16 CP-16
ADCMP573BCP −40°C to 85°C LFCSP-16 CP-16
Rev. PrB | Page 14 of 16
Preliminary Technical Data ADCMP572/ADCMP573
NOTES
Rev. PrB | Page 15 of 16
ADCMP572/ADCMP573 Preliminary Technical Data
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR04409–0–6/04(PrB)
Rev. PrB | Page 16 of 16
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