ANALOG DEVICES ADCMP572, ADCMP573 Service Manual
Ultrafast 3.3 V/5 V
FEATURES
3.3 V/5.2 V single-supply operation
150 ps propagation delay
15 ps overdrive and slew rate dispersion
8 GHz equivalent input rise time bandwidth
80 ps minimum pulse width
35 ps typical output rise/fall
10 ps deterministic jitter (DJ)
200 fs random jitter (RJ)
On-chip terminations at both input pins
Robust inputs with no output phase reversal
Resistor-programmable hysteresis
Differential latch control
Extended industrial −40°C to +125°C temperature range
APPLICATIONS
Clock and data signal restoration and level shifting
Automatic test equipment (ATE)
High speed instrumentation
Pulse spectroscopy
Medical imaging and diagnostics
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Single-Supply SiGe Comparators
ADCMP572/ADCMP573
FUNCTIONAL BLOCK DIAGRAM
V
CML/
RSPECL
LE INPUT
LE INPUTHYS
CCO
Q OUTPUT
Q OUTPUT
04409-025
V
TERMINATION
TP
VP NONINVERTING
V
N
V
TN
INPUT
INVERTING
INPUT
TERMINATION
V
CCI
ADCMP572
ADCMP573
Figure 1.
GENERAL DESCRIPTION
The ADCMP572 and ADCMP573 are ultrafast comparators
fabricated on Analog Devices’ proprietary XFCB3 Silicon
Germanium (SiGe) bipolar process. The ADCMP572 features
CML output drivers and latch inputs, and the ADCMP573
features reduced swing PECL (RSPECL) output drivers and
latch inputs.
Both devices offer 150 ps propagation delay and 80 ps
minimum pulse width for 10 Gbps operation with 200 fs rms
random jitter (RJ). Overdrive and slew rate dispersion are
typically less than 15 ps.
A flexible power supply scheme allows both devices to operate
with a single 3.3 V positive supply and a −0.2 V to +1.2 V input
signal range or with split input/output supplies to support a
wider −0.2 V to +3.2 V input signal range and an independent
range of output levels. 50 Ω on-chip termination resistors are
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devi ces for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
provided at both inputs with the optional capability to be left
open (on an individual pin basis) for applications requiring
high impedance inputs.
The CML output stage is designed to directly drive 400 mV into
50 Ω transmission lines terminated to between 3.3 V to 5.2 V.
The RSPECL output stage is designed to drive 400 mV into
50 Ω terminated to V
− 2 V and is compatible with several
CCO
commonly used PECL logic families. The comparator input
stage offers robust protection against large input overdrive, and
the outputs do not phase reverse when the valid input signal
range is exceeded. High speed latch and programmable
hysteresis features are also provided.
The ADCMP572 and ADCMP573 are available in a 16-lead
LFCSP package and have been characterized over an extended
industrial temperature range of −40°C to +125°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005–2009 Analog Devices, Inc. All rights reserved.
ADCMP572/ADCMP573
TABLE OF CONTENTS
Electrical Characteristics ................................................................. 3
Using/Disabling the Latch Feature ..............................................9
Absolute Maximum Ratings ............................................................ 5
Thermal Considerations .............................................................. 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Application Information .................................................................. 9
Power/Ground Layout and Bypassing ....................................... 9
CML/RSPECL Output Stage ....................................................... 9
REVISION HISTORY
4/09—Rev. 0 to Rev. A
Changes to Figure 26 ...........................................................................12
Updated Outline Dimensions ............................................................14
Changes to Ordering Guide ...............................................................14
4/05—Revision 0: Initial Version
Optimizing High Speed Performance ..................................... 10
Comparator Propagation Delay Dispersion ........................... 10
Comparator Hysteresis .............................................................. 11
Minimum Input Slew Rate Requirements .............................. 11
Typical Application Circuits ......................................................... 12
Timing Information ....................................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
Rev. A | Page 2 of 16
ADCMP572/ADCMP573
ELECTRICAL CHARACTERISTICS
V
= V
CCI
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
DC INPUT CHARACTERISTICS
Input Voltage Range VP, VN V
V
Input Differential Voltage −1.2 +1.2 V
Input Offset Voltage VOS −5.0 ±2.0 +5.0 mV
Offset Voltage Tempco ∆VOS/dT 10.0 μV/°C
Input Bias Current IP, IN Open termination −50.0 −25.0 0.0 μA
Input Bias Current Tempco 50.0 nA/°C
Input Offset Current ±2.0 μA
Input Impedance 50 Ω
Input Resistance, Differential Open termination 50 kΩ
Input Resistance, Common-Mode Open termination 500 kΩ
Active Gain AV 54 dB
Common-Mode Rejection CMRR V
Power Supply Rejection—V
Hysteresis
LATCH ENABLE CHARACTERISTICS
ADCMP572
ADCMP573
Latch Enable Input Impedance 50.0 Ω
Latch to Output Delay t
Latch Minimum Pulse Width tPL V
DC OUTPUT CHARACTERISTICS
ADCMP572 (CML)
ADCMP573 (RSPECL)
= 3.3 V, TA = −40°C to +125°C, typical at TA = +25°C, unless otherwise noted.
CCO
= 3.3 V, V
CCI
= 5.2 V, V
CCI
= 3.3 V, V
CCI
V
= 0.0 V to 1.0 V
CM
V
= 5.2 V, V
CCI
V
= 0.0 V to 3.0 V
CM
PSR
CCI
V
VCCI
R
= 3.3 V ± 5%, V
CCI
= ∞
HYS
Latch Enable Input Range 2.8 V
= 3.3 V −0.2 +1.2 V
CCO
= 3.3 V −0.2 +3.1 V
CCO
= 3.3 V,
CCO
= 3.3 V,
CCO
= 3.3 V 74 dB
CCO
65 dB
65 dB
±1 mV
+ 0.2 V
CCO
Latch Enable Input Differential 0.2 0.4 0.5 V
Latch Setup Time tS V
Latch Hold Time tH V
Latch Enable Input Range 1.8 V
= 100 mV 15 ps
OD
= 100 mV 5 ps
OD
− 0.6 V
CCO
Latch Enable Input Differential 0.2 0.4 0.5 V
Latch Setup Time tS V
Latch Hold Time tH V
PLOH, tPLOL
Output Impedance Z
VOD = 100 mV 150 ps
−8 mA < I
OUT
Output Voltage High Level VOH 50 Ω terminate to V
Output Voltage Low Level VOL 50 Ω terminate to V
Output Voltage Differential 50 Ω terminate to V
Output Voltage High −40°C VOH 50 Ω terminate to V
Output Voltage High +25°C VOH 50 Ω terminate to V
Output Voltage High +125°C VOH 50 Ω terminate to V
Output Voltage Low −40°C VOL 50 Ω terminate to V
Output Voltage Low +25°C VOL 50 Ω terminate to V
Output Voltage Low +125°C VOL 50 Ω terminate to V
Output Voltage Differential 50 Ω terminate to V
= 100 mV 90 ps
OD
= 100 mV 100 ps
OD
= 100 mV 100 ps
OD
< 8 mA 50.0 Ω
OUT
V
CCO
V
CCO
300 375 450 mV
CCO
− 2.0 V
CCO
− 2.0 V
CCO
− 2.0 V
CCO
− 2.0 V
CCO
− 2.0 V
CCO
− 2.0 V
CCO
− 2.0 300 375 450 mV
CCO
− 0.10 V
CCO
− 0.60 V
CCO
− 1.14 V
CCO
− 1.10 V
CCO
− 1.04 V
CCO
− 1.54 V
CCO
− 1.50 V
CCO
− 1.44 V
CCO
− 0.05 V
CCO
− 0.45 V
CCO
− 1.02 V
CCO
− 0.98 V
CCO
− 0.92 V
CCO
− 1.39 V
CCO
− 1.35 V
CCO
− 1.29 V
CCO
V
CCO
− 0.30 V
CCO
− 0.90 V
CCO
− 0.86 V
CCO
− 0.80 V
CCO
− 1.24 V
CCO
− 1.20 V
CCO
− 1.14 V
CCO
Rev. A | Page 3 of 16
ADCMP572/ADCMP573
Parameter Symbol Conditions Min Typ Max Unit
AC PERFORMANCE
Propagation Delay tPD V
V
V
Propagation Delay Tempco ∆tPD/dT 0.5 ps/°C
Prop Delay Skew—Rising Transition
V
to Falling Transition
Overdrive Dispersion 50 mV < VOD < 0.2 V, 5 V/ns 15 ps
Slew Rate Dispersion 2 V/ns to 10 V/ns, 250 mV OD 15 ps
Pulse Width Dispersion 100 ps to 5 ns, 250 mV OD 5 ps
10% – 90% Duty Cycle Dispersion V
Common-Mode Dispersion VOD = 0.2 V, 0.0 V < VCM < 2.9 V 5 ps/V
Equivalent Input Bandwidth1 BWEQ
Toggle Rate >50% Output Swing 12.5 Gbps
Deterministic Jitter DJ
RMS Random Jitter RJ VOD = 200 mV, 5 V/ns, 1.25 GHz 0.2 ps
Minimum Pulse Width PW
PW
∆tPD/∆PW < 5 ps, 200 mV OD 100 ps
MIN
∆tPD/∆PW < 10 ps, 200 mV OD 80 ps
MIN
Rise Time tR 20/80 35 ps
Fall Time tF 20/80 35 ps
POWER SUPPLY
Input Supply Voltage Range V
Output Supply Voltage Range V
Positive Supply Differential V
3.1 5.4 V
CCI
3.1 5.4 V
CCO
−V
−0.2 +2.3 V
CCI
CCO
ADCMP572 (CML)
Positive Supply Current I
VCCI
+ I
VCCO
Device Power Dissipation PD
ADCMP573 (RSPECL)
Positive Supply Current I
VCCI
+ I
VCCO
Device Power Dissipation PD
1
Equivalent input bandwidth assumes a simple first-order response and is calculated with the following formula: BWEQ = 0.22/√(tr
transition time of a quasi-Gaussian signal applied to the comparator input, and tr
= 3.3 V, VOD = 200 mV 150 ps
CCI
= 3.3 V, VOD = 20 mV 165 ps
CCI
= 5.2 V, VOD = 200 mV 145 ps
CCI
= 200 mV, 5 V/ns 10 ps
OD
10 mV < VOD < 0.2 V, 5 V/ns 15 ps
= 3.3 V, 1 V/ns, 250 mV OD 5 ps
CCI
V
= 5.2 V, 1 V/ns, 250 mV OD 10
CCI
0.0 V to 250 mV input
8.0 GHz
tR = tF = 17 ps, 20/80
= 200 mV, 5 V/ns,
V
OD
31
− 1 NRZ, 4 Gbps
PRBS
= 200 mV, 5 V/ns,
V
OD
31
− 1 NRZ, 10 Gbps
PRBS
= 3.3 V, V
V
CCI
terminate 50 Ω to V
V
= 5.2 V, V
CCI
terminate 50 Ω to V
= 3.3 V, V
V
CCI
terminate 50 Ω to V
V
= 5.2 V, V
CCI
terminate 50 Ω to V
= 3.3 V, V
V
CCI
50 Ω to V
V
= 5.2 V, V
CCI
50 Ω to V
= 3.3 V, V
V
CCI
50 Ω to V
V
= 5.2 V, V
CCI
50 Ω to V
= 3.3 V,
CCO
CCO
CCO
CCO
CCO
− 2 V
CCO
CCO
– 2 V
CCO
CCO
− 2 V
CCO
CCO
− 2 V
CCO
is the effective transition time digitized by the comparator.
COMP
CCO
= 5.2 V,
CCO
= 3.3 V,
CCO
= 5.2 V,
CCO
= 3.3 V,
= 5.2 V,
= 3.3 V,
= 5.2 V,
10 ps
20 ps
44 52 mA
44 52
140 165 mW
230 265
62 80 mA
64 80
110 160 mW
146 230
2
2
−tr
), where trIN is the 20/80
COMP
IN
Rev. A | Page 4 of 16
ADCMP572/ADCMP573
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
SUPPLY VOLTAGE
Input Supply Voltage
to GND)
(V
CCI
Output Supply Voltage
(V
to GND)
CCO
Positive Supply Differential
− V
CCO
)
(V
CCI
INPUT VOLTAGE
Input Voltage −0.5 V to V
Differential Input Voltage ±(V
Input Voltage, Latch Enable −0.5 V to V
HYSTERESIS CONTROL PIN
Applied Voltage (HYS to GND) −0.5 V to +1.5 V
Maximum Input/Output Current ±1 mA
OUTPUT CURRENT
ADCMP572 (CML) ±20 mA
ADCMP573 (RSPECL) −35 mA
TEMPERATURE
Operating Temperature, Ambient −40°C to +125°C
Operating Temperature, Junction +150°C
Storage Temperature Range −65°C to +150°C
−0.5 V to +6.0 V
−0.5 V to +6.0 V
−0.5 V to +3.5 V
+ 0.5 V
CCI
+ 0.5 V)
CCI
+ 0.5 V
CCO
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CONSIDERATIONS
The ADCMP572/ADCMP573 LFCSP 16-lead package has a θJA
(junction-to-ambient thermal resistance) of 70°C/W in still air.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 16
Loading...