Analog Devices ADCMP567 Datasheet

Dual Ultrafast

FEATURES

250 ps propagation delay input to output
50 ps propagation delay dispersion
Differential PECL compatible outputs
Differential latch control
Robust input protection
Input common-mode range −2.0 V to +3.0 V
Input differential range ±5 V
ESD protection >3 kV HBM, >200 V MM
Power supply sensitivity >65 dB
200 ps minimum pulsewidth
5 GHz equivalent input rise time bandwidth
Typical output rise/fall of 165 ps

APPLICATIONS

High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers and signal restoration
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Disk drive read channel detection
Hand-held test instruments
Zero-crossing detectors
Clock drivers
Automatic test equipment

Voltage Comparator

ADCMP567

FUNCTIONAL BLOCK DIAGRAM

NONINVERTING
INPUT

INVERTING
INPUT

LATCH ENABLE
INPUT

GENERAL DESCRIPTION

The ADCMP567 is an ultrafast voltage comparator fabricated
on Analog Devices’ proprietary XFCB process. The device
features 250 ps propagation delay with less than 35 ps overdrive
dispersion. Overdrive dispersion, a particularly important
characteristic of high speed comparators, is a measure of the
difference in propagation delay under differing overdrive
conditions.

A fast, high precision differential input stage permits consis-
tent propagation delay with a wide variety of signals in the
common-mode range from −2.0 V to +3.0 V. Outputs are
complementary digital signals fully compatible with PECL 10 K
and 10 KH logic families. The outputs provide sufficient drive
current to directly drive transmission lines terminated in 50 Ω

− 2 V. A latch input is included, which permits tracking,

to V

DD

track-and-hold, or sample-and-hold modes of operation.

The ADCMP567 is available in a 32-lead LFCSP package.

ADCMP567

LATCH ENABLE
INPUT

Figure 1.

Q OUTPUT

Q OUTPUT

03632-0-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

www.analog.com

ADCMP567

TABLE OF CONTENTS

Specifications..................................................................................... 3

Optimizing High Speed Performance ........................................9

Absolute Maximum Ratings............................................................ 5

Thermal Considerations.............................................................. 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Timing Information ......................................................................... 8

Application Information.................................................................. 9

Clock Timing Recovery............................................................... 9

REVISION HISTORY

Revision 0: Initial Version

Comparator Propagation Delay Dispersion ..............................9

Comparator Hysteresis .............................................................. 10

Minimum Input Slew Rate Requirement................................ 10

Typical Application Circuits ..................................................... 11

Typical Perfor m a n c e Character i stics ........................................... 12

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. 0 | Page 2 of 16

ADCMP567

SPECIFICATIONS

Table 1. ADCMP567 ELECTRICAL CHARACTERISTICS (VCC = +5.0 V, VEE = −5.2 V, VDD = +3.3 V, TA = 25°C, unless otherwise noted.)

Parameter Symbol Condition Min Typ Max Unit

DC INPUT CHARACTERISTICS (See Note)

Input Common-Mode Range V

CM

Input Differential Voltage −5 +5 V
Input Offset Voltage V

OS

Input Offset Voltage Channel Matching ±1.0 mV
Offset Voltage Tempco DVOS/d
Input Bias Current I

BC

Input Bias Current Tempco 10.0 nA/°C
Input Offset Current −8.0 ±0.5 +8.0 µA
Input Capacitance C

IN

Input Resistance, Differential Mode 100 kΩ
Input Resistance, Common Mode 600 kΩ
Open Loop Gain 60 dB
Common-Mode Rejection Ratio CMRR VCM = −2.0 V to +3.0 V 69 dB
Hysteresis ±1.0 mV

LATCH ENABLE CHARACTERISTICS

Latch Enable Common-Mode Range V
Latch Enable Differential Input Voltage V

LCM

LD

Input High Current @ 0.0 V −12 +6 +12 µA
Input Low Current @ −2.0 V −12 +6 +12 µA
Latch Setup Time t
Latch to Output Delay t
Latch Pulsewidth t
Latch Hold Time t

S

PLOH, tPLOL

PL

H

OUTPUT CHARACTERISTICS

Output Voltage—High Level V
Output Voltage—Low Level V
Rise Time t
Fall Time t

OH

OL

R

F

AC PERFORMANCE

Propagation Delay t
Propagation Delay t

PD

PD

Propagation Delay Tempco 0.5 ps/°C
Prop Delay Skew—Rising Transition to

±10 ps

Falling Transition
Within Device Propagation Delay Skew—

±10 ps

Channel to Channel
Propagation Delay Dispersion vs.

±10 ps

Duty Cycle
Propagation Delay Dispersion vs.

50 mV to 1.5 V 35 ps

Overdrive
Propagation Delay Dispersion vs.

20 mV to 1.5 V 50 ps

Overdrive
Propagation Delay Dispersion vs.

Slew Rate

Propagation Delay Dispersion vs.
Common-Mode Voltage

−2.0 +3.0 V

−5.0 ±1.0 +5.0 mV

10.0 µV/°C

T

−10 +24 +42 µA

0.75 pF

V

− 2.0 V

DD

DD

V

0.4 2.0 V

250 mV overdrive 50 ps
250 mV overdrive 300 ps
250 mV overdrive 150 ps
250 mV overdrive 90 ps

PECL 50 Ω to −2.0 V VDD − 1.1 VDD − 0.81 V
PECL 50 Ω to −2.0 V VDD − 1.95 VDD − 1.54 V
20% to 80% 175 ps
20% to 80% 140 ps

1 V overdrive 250 ps
20 mV overdrive 300 ps

0 V to 1 V swing,

50 ps
20% to 80%,
50 ps and 600 ps

1 V swing,

−1.5 V to 2.5 V

CM

5 ps

Rev. 0 | Page 3 of 16

ADCMP567

Parameter Symbol Condition Min Typ Max Unit

AC PERFORMANCE (continued)

Equivalent Input Rise Time Bandwidth BW

0 V to 1 V swing,

3500 5000 MHz

20% to 80%,

, t

50 ps t

R

F

Toggle Rate >50% output swing 5 Gbps
Minimum Pulsewidth PW

from 10 ns to

∆t

PD

200 ps

200 ps < ±25 ps

Unit to Unit Propagation Delay Skew ±10 ps

POWER SUPPLY

Positive Supply Current I

Negative Supply Current I

Logic Supply Current I

Logic Supply Current I

Positive Supply Voltage V
Negative Supply Voltage V
Logic Supply Voltage V

V

CC

V

EE

V

DD

V

DD

CC

EE

DD

@ +5.0 V 7 13 20 mA

@ −5.2 V 60 78 95 mA

@ 3.3 V, without load 8 13 18 mA

@ 3.3 V, with load 50 65 80 mA

Dual 4.75 5.0 5.25 V
Dual −4.96 −5.2 −5.45 V

Dual 2.5 3.3 5.0 V
Power Dissipation Dual, without load 415 515 615 mW
Power Dissipation Dual, with load 575 675 mW
Power Supply Sensitivity—V

Power Supply Sensitivity—V

Power Supply Sensitivity—V

CC

EE

DD

PSS

PSS

PSS

V

CC

V

EE

V

DD

69 dB

85 dB

70 dB

NOTE: Under no circumstances should the input voltages exceed the supply voltages.

Rev. 0 | Page 4 of 16

ADCMP567

ABSOLUTE MAXIMUM RATINGS

Table 2. ADCMP567 Absolute Maximum Ratings

Parameter Rating
Supply

Voltages

Input
Voltages

Output
Temperature

Positive Supply Voltage

to GND)

(V

CC

Negative Supply Voltage

to GND)

(V

EE

Logic Supply Voltage

to GND)

(V

DD

Ground Voltage Differential −0.5 V to +0.5 V
Input Common-Mode

Voltage
Differential Input Voltage −7.0 V to +7.0 V
Input Voltage,

Latch Controls
Output Current 30 mA
Operating Temperature,

Ambient
Operating Temperature,

Junction
Storage Temperature Range −65°C to +150°C

−0.5 V to +6.0 V

−6.0 V to +0.5 V

−0.5 V to +6.0 V

−3.0 V to +4.0 V

−0.5 V to +5.5 V

−40°C to +85°C

125°C

Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

THERMAL CONSIDERATIONS

The ADCMP567 LFCSP 32-lead package option has a θJA
(junction-to-ambient thermal resistance) of 27.2°C/W in
still air.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 5 of 16

ADCMP567

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DD

DD

LEA30LEA

NC

V

V

32 GND

31

29

27QA26QA25

28

GND

1
–INA
+INA

V

CC

V

CC

+INB
–INB
GND

Figure 2. ADCMP567 Pin Configuration

Table 3. ADCMP567 Pin Descriptions

Pin No. Mnemonic Function

1 GND Analog Ground
2 −INA

Inverting analog input of the differential input stage for Channel A. The inverting A input must be driven
in conjunction with the noninverting A input.

3 +INA

Noninverting analog input of the differential input stage for Channel A. The noninverting A input must

be driven in conjunction with the inverting A input.
4 V
5 V

CC

CC

6 +INB

Positive Supply Terminal

Positive Supply Terminal

Noninverting analog input of the differential input stage for Channel B. The noninverting B input must

be driven in conjunction with the inverting B input.
7 −INB

Inverting analog input of the differential input stage for Channel B. The inverting B input must be driven

in conjunction with the noninverting B input.
8 GND Analog Ground
9 GND Analog Ground
10

LEB One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic low), the

output will track changes at the input of the comparator. In the latch mode (logic high), the output will

reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven

LEB

11 LEB

in conjunction with

One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic high), the

output will track changes at the input of the comparator. In the latch mode (logic low), the output will

reflect the input state just prior to the comparator’s being placed in the latch mode.

in conjunction with LEB.
12 NC No Connect. Leave pin unconnected.
13 V
14

DD

QB

Logic Supply Terminal

One of two complementary outputs for Channel B. QB will be at logic low if the analog voltage at the

noninverting input is greater than the analog voltage at the inverting input (provided the comparator is

in the compare mode). See the LEB description (
15 QB

One of two complementary outputs for Channel B. QB will be at logic high if the analog voltage at the

noninverting input is greater than the analog voltage at the inverting input (provided the comparator is

in the compare mode). See the LEB description (
16 V
17 V

DD

EE

Logic Supply Terminal

Negative Supply Terminal
18 NC No Connect. Leave pin unconnected.
19 V
20 V
21 V

EE

CC

CC

Negative Supply Terminal

Positive Supply Terminal

Positive Supply Terminal

PIN 1

2

INDICATOR

3
4

ADCMP567

5

TOP VIEW

6

(Not to Scale)

7
8

LEB10LEB

GND 9

NC = NO CONNECT

.

11NC12

23 NC
22 V
21 V
20 V
19 V
18 NC
17 V

13

14

16

DD

DD

QB 15

QB

V

V

03632-0-002

VEE24

EE
CC
CC
EE

EE

Pin 11) for more information.

Pin 11) for more information.

LEB

must be driven

Rev. 0 | Page 6 of 16