Analog Devices ADCMP561 2 a Datasheet

A

Dual High Speed PECL Comparators

FEATURES

Differential PECL compatible outputs
700 ps propagation delay input to output
75 ps propagation delay dispersion
Input common-mode range: –2.0 V to +3.0 V
Robust input protection
Differential latch control
Internal latch pull-up resistors
Power supply rejection greater than 85 dB
700 ps minimum pulse width

1.5 GHz equivalent input rise time bandwidth
Typical output rise/fall time of 500 ps
ESD protection > 4kV HBM, >200V MM
Programmable hysteresis

APPLICATIONS

Automatic test equipment
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Disk drive read channel detection
Hand-held test instruments
Zero-crossing detectors
Line receivers and signal restoration
Clock drivers

GENERAL DESCRIPTION

The ADCMP561/ADCMP562 are high speed comparators
fabricated on Analog Devices’ proprietary XFCB process. The
devices feature a 700 ps propagation delay with less than 75 ps
overdrive dispersion. Dispersion, a measure of the difference in
propagation delay under differing overdrive conditions, is a
particularly important characteristic of comparators. A separate
programmable hysteresis pin is available on the ADCMP562.

ADCMP561/ADCMP562

FUNCTIONAL BLOCK DIAGRAM

NONINVERTING

INPUT

INVERTING

INPUT

LATCH ENABLE
INPUT

1

QA

2

QA

3

V

DD

ADCMP561

4

LEA
LEA

V
–INA
+INA

EE

TOP VIEW

5

(Not to Scale)

6

7

8

Figure 2. ADCMP561 16-Lead QSOP Figure 3. ADCMP562 20-Lead QSOP

are fully compatible with PECL 10 K and 10 KH logic families.
The outputs provide sufficient drive current to directly drive
transmission lines terminated in 50 Ω to V
input, which is included, permits tracking, track-and-hold, or
sample-and-hold modes of operation. The latch input pins
contain internal pull-ups that set the latch in tracking mode
when left open.

16

QB

15

QB

14

GND

13

LEB

12

LEB

11

V

CC

10

–INB
+INB

9

HYS*

ADCMP561/

ADCMP562

LATCH ENABLE
INPUT

*ADCMP562 ONLY

Figure 1.

V

DD

QA
QA

V

DD

LEA
LEA

V

EE

–INA
+INA

HYS

04687-0-002

1

2

3

ADCMP562

4

TOP VIEW

5

(Not to Scale)

6

7

8

9

10

DD

Q OUTPUT

Q OUTPUT

04687-0-001

V

20

QB

19

QB

18

GND

17

LEB

16

LEB

15

V

14

–INB

13

+INB

12

HYSB

11

− 2 V. A latch

DD

CC

04687-0-003

A differential input stage permits consistent propagation delay
with a wide variety of signals in the common-mode range from

The ADCMP561/ADCMP562 are specified over the industrial
temperature range (−40°C to +85°C).

−2.0 V to +3.0 V. Outputs are complementary digital signals that

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

ADCMP561/ADCMP562

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Considerations.............................................................. 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 8

Timing Information ....................................................................... 10

Application Information................................................................ 11

REVISION HISTORY

7/04—Data Sheet Changed from Rev. 0 to Rev. A

Changes to Specification Table ....................................................... 4

Changes to Figure 14........................................................................ 9

Changes to Figure 21...................................................................... 12

Changes to Figure 23...................................................................... 13

4/04—Revision 0: Initial Version

Clock Timing Recovery............................................................. 11

Optimizing High Speed Performance ..................................... 11

Comparator Propagation Delay Dispersion ........................... 11

Comparator Hysteresis .............................................................. 12

Minimum Input Slew Rate Requirement ................................ 12

Typical Application Circuits .......................................................... 13

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. A | Page 2 of 16

ADCMP561/ADCMP562

SPECIFICATIONS

VCC = +5.0 V, VEE = −5.2 V, VDD = +3.3 V, TA = −40°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.

Table 1. Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Unit

DC INPUT CHARACTERISTICS

Input Voltage Range −2.0 3.0 V
Input Differential Voltage −5 +5 V
Input Offset Voltage V

OS

Input Offset Voltage Channel Matching ±2.0 mV
Offset Voltage Tempco ∆VOS/d
Input Bias Current I

IN

Input Bias Current Tempco 0.5 nA/°C
Input Offset Current ±1.0 µA
Input Capacitance C

IN

Input Resistance, Differential Mode 750 kΩ
Input Resistance, Common Mode 1800 kΩ
Active Gain A

V

Common-Mode Rejection Ratio CMRR VCM = −2.0 V to +3.0 V 80 dB
Hysteresis R

LATCH ENABLE CHARACTERISTICS

Latch Enable Voltage Range VDD − 2.0 V
Latch Enable Differential Voltage Range 0.4 2.0 V
Latch Enable Input High Current @ V
Latch Enable Input Low Current @ VDD −2.0 V −300 +300 µA
LE Voltage, Open Latch inputs not connected VDD − 0.2 V
LE Voltage, Open
Latch Setup Time t
Latch Hold Time t
Latch-to-Output Delay t
Latch Minimum Pulse Width t

Latch inputs not connected V

S

H

, t

PLOH

PL

DC OUTPUT CHARACTERISTICS

Output Voltage—High Level V
Output Voltage—Low Level V
Rise Time t
Fall Time t

OH

OL

R

F

AC PERFORMANCE

Propagation Delay t

PD

V
Propagation Delay Tempco ∆tPD /d
Prop Delay Skew—Rising Transition to

Falling Transition

Within Device Propagation Delay Skew—

Channel-to-Channel
Overdrive Dispersion 20 mV ≤ VOD ≤ 100 mV 75 ps
Overdrive Dispersion 100 mV ≤ VOD ≤ 1.5 V 75 ps
Slew Rate Dispersion 0.4 V/ns ≤ SR ≤ 1.33 V/ns 50 ps
Pulse Width Dispersion 700 ps ≤ PW ≤ 10 ns 25 ps
Duty Cycle Dispersion 33 MHz, 1 V/ns, 0.5 V 15 ps
Common-Mode Voltage Dispersion 1 V swing, −1.5 V ≤ VCM ≤ +2.5 V 10 ps

VCM = 0 V −10.0 ±2.0 +10.0 mV

2.0 µV/°C

T

−IN = −2 V, +IN = +3 V −10.0 ±3 +10.0 µA

0.75 pF

63 dB

= ∞ ±1.0 mV

HYS

DD

DD

−300 +300 µA

VDD + 0.1 V

DD

/2 − 0.2 VDD/2 VDD/2 + 0.2 V

DD

V

VOD = 250 mV 250 ps
VOD = 250 mV 250 ps

PLOLVOD

= 250 mV 600 ps

VOD = 250 mV 500 ps

PECL 50 Ω to VDD − 2.0 V VDD − 1.15 VDD − 0.81 V
PECL 50 Ω to VDD − 2.0 V VDD − 1.95 VDD − 1.54 V
10% to 90% 550 ps
10% to 90% 470 ps

VOD = 1 V 700 ps

= 20 mV 830 ps

OD

VOD = 1 V 0.25 ps/°C

T

= 1 V 50 ps

V

OD

V

= 1 V 50 ps

OD

Rev. A | Page 3 of 16

ADCMP561/ADCMP562

Parameter Symbol Conditions Min Typ Max Unit

AC PERFORMANCE (continued)

Equivalent Input Rise Time Bandwidth1 BW

EQ

Maximum Toggle Rate >50% output swing 800 MHz
Minimum Pulse Width PW

MIN

RMS Random Jitter

Unit-to-Unit Propagation Delay Skew 100 ps

POWER SUPPLY

Positive Supply Current I
Negative Supply Current I
Logic Supply Current I

VCC

VEE

VDD

Logic Supply Current @ 3.3 V with load 45 60 70 mA
Positive Supply Voltage V
Negative Supply Voltage V
Logic Supply Voltage V
Power Dissipation P

CC

EE

DD

D

Power Dissipation Dual, with load 180 220 250 mW
DC Power Supply Rejection Ratio—V
DC Power Supply Rejection Ratio—V
DC Power Supply Rejection Ratio—V

CC

EE

DD

PSRR
PSRR
PSRR

HYSTERESIS (ADCMP562 Only)

Hysteresis R
R

0 V to 1 V swing, 2 V/ns 1500 MHz

∆tPD < 25 ps 700 ps

= 400 mV, 1.3 V/ns, 312 MHz,

V

OD

1.0 ps

50% duty cycle

@ +5.0 V 2 3.2 5 mA
@ −5.2 V 10 22 28 mA
@ 3.3 V without load 6 9 13 mA

Dual 4.75 5.0 5.25 V
Dual −4.96 −5.2 −5.45 V
Dual 2.5 3.3 5.0 V
Dual, without load 130 160 190 mW

85 dB

VCC

85 dB

VEE

85 dB

VDD

= 19.5 kΩ 20 mV

HYS

= 8.0 kΩ 70 mV

HYS

1

Equivalent input rise time bandwidth assumes a first-order input response and is calculated by the following formula: BWEQ = 0.22/√ (tr

20/80 input transition time applied to the comparator and tr

is the effective transition time as digitized by the comparator input.

COMP

COMP

2

2

– tr

), where trIN is the

IN

Rev. A | Page 4 of 16

ADCMP561/ADCMP562

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltages

Positive Supply Voltage (VCC to GND) −0.5 V to +6.0 V
Negative Supply Voltage (VEE to GND) −6.0 V to +0.5 V
Logic Supply Voltage (VDD to GND) −0.5 V to +6.0 V
Ground Voltage Differential −0.5 V to +0.5 V

Input Voltages

Input Common-Mode Voltage −3.0 V to +4.0 V
Differential Input Voltage −7.0 V to +7.0 V
Input Voltage, Latch Controls −0.5 V to +5.5 V

Output

Output Current 30 mA

Temperature

Operating Temperature, Ambient −40°C to +85°C
Operating Temperature, Junction 125°C
Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.

THERMAL CONSIDERATIONS

The ADCMP561 QSOP 16-lead package option has a θJA
(junction-to-ambient thermal resistance) of 104°C/W in
still air.

The ADCMP562 QSOP 20-lead package option has a θ
(junction-to-ambient thermal resistance) of 80°C/W in
still air.

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 5 of 16