Datasheet ADCMP551, ADCMP552, ADCMP553 Datasheet (ANALOG DEVICES)

Single Supply High Speed PECL Comparators

Preliminary Technical Data

FEATURES

Single power supply 750 ps propagation delay input to output 100 ps propagation delay dispersion Differential PECL compatible outputs Differential latch control Internal latch pull-up resistors Power supply rejection greater than 70 dB 750 ps minimum pulse width Equivalent input rise time bandwidth > 750 MHz Typical output rise/fall of 500 ps Programmable Hysteresis

APPLICATIONS

Automatic test equipment High speed instrumentation Scope and logic analyzer front ends Window comparators High speed line receivers Threshold detection Peak detection High speed triggers Patient diagnostics Disk drive read channel detection Hand-held test instruments Zero crossing detectors Line receivers and signal restoration Clock drivers

ADCMP551/ADCMP552/ADCMP553

FUNCTIONAL BLOCK DIAGRAM

NONINVERTING

INPUT

INVERTING

INPUT

LATCH ENABLE INPUT

ADCMP551/ ADCMP552/

ADCMP553

LATCH ENABLE INPUT

Figure 1.

GENERAL DESCRIPTION

The ADCMP551/ADCMP552/ADCMP553 are single supply, high speed comparators fabricated on Analog Devices’ proprietary XFCB process. The devices feature a 750 ps propagation delay with less than 150 ps overdrive dispersion. Dispersion, a measure of the difference in propagation delay under differing overdrive conditions, is a particularly important characteristic of high speed comparators. A separate programmable hysteresis pin is available on the ADCMP552.

A differential input stage permits consistent propagation delay with a common-mode range from –0.2 V to VCCI – 2.0 V. Outputs are complementary digital signals are fully compatible with PECL 10 K and 10 KH logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 Ω to VCCO − 2 V. A latch input is included and permits tracking, track-and-hold, or sample-and-hold modes of operation. The latch input pins contain internal pullups that set the latch in tracking mode when left open.

Q OUTPUT

4722-0-001

Rev. PrB

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

The ADCMP551/ADCMP552/ADCMP553 are specified over the –40°C to +85°C industrial temperature range. The ADCMP551 is available in a 16-lead QSOP package; the ADCMP552 is available in a 20-lead QSOP package; and the ADCMP553 is available in an 8-lead MSOP package.

ADCMP551/ADCMP552/ADCMP553 Preliminary Technical Data

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Considerations.............................................................. 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 8

Timing Information ....................................................................... 10

Application Information ................................................................ 11

REVISION HISTORY

Revision PrA: Preliminary Version

Clock Timing Recovery............................................................. 11

Optimizing High Speed Performance ..................................... 11

Comparator Propagation Delay Dispersion ........................... 11

Comparator Hysteresis .............................................................. 12

Minimum Input Slew Rate Requirement................................ 12

Typical Application Ci rc u it s ......................................................... 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. PrB | Page 2 of 14

Preliminary Technical Data ADCMP551/ADCMP552/ADCMP553

SPECIFICATIONS

= 3.3 V, V

CCI

Table 1. ADCMP551/ADCMP552/ADCMP553 Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Unit

DC INPUT CHARACTERISTICS

Input Voltage Range −0.2 V Input Differential Voltage Range −3 +3 V Input Offset Voltage V Input Offset Voltage Channel Matching ±3.0 mV Offset Voltage Tempco ∆VOS/d Input Bias Current I Input Bias Current Tempco 0.5 nA/°C Input Offset Current −3.0 ±1.0 +3.0 µA Input Capacitance C Input Resistance, Differential Mode 100 kΩ Input Resistance, Common Mode 600 kΩ Active Gain A Common-Mode Rejection Ratio CMRR VCM = −0.2 V to +1.3 V 70 dB Hysteresis R

LATCH ENABLE CHARACTERISTICS

Latch Enable Voltage Range Latch Enable Differential Voltage Range 0.4 1.0 V Latch Enable Input High Current @ V Latch Enable Input Low Current @ V LE Voltage, Open Latch inputs not connected V LE

Voltage, Open Latch Setup Time t Latch Hold Time t Latch to Output Delay t Latch Minimum Pulse Width t

DC OUTPUT CHARACTERISTICS

Output Voltage—High Level V Output Voltage—Low Level V Rise Time t Fall Time t

AC PERFORMANCE

Propagation Delay t V Propagation Delay Tempco ∆tPD/d Prop Delay Skew—Rising Transition to

Falling Transition Within Device Propagation Delay

Skew—Channel-to-Channel Overdrive Dispersion 50 mV ≤ VOD ≤ 100 mV 100 ps Overdrive Dispersion 100 mV ≤ VOD ≤ 1.5 V 100 ps Slew Rate Dispersion 0.4 V/ns ≤ SR ≤ 1.33 V/ns 100 ps Pulse Width Dispersion 750 ps ≤ PW ≤ 10 ns 50 ps Duty Cycle Dispersion 33 MHz, 1 V/ns, VCM = 0.5 V 50 ps Common-Mode Voltage Dispersion 1 V swing, 0.3 V ≤ VCM ≤ 0.8 V 100 ps

= 3.3 V, TA = 25°C, unless otherwise noted.

CCO

Latch inputs not connected V

, t

PLOH

PLOL

– 2.0 V

CCI

−IN = 0 V, +IN = 0 V −10.0 ±3.0 +10.0 mV

10.0 µV/°C

−IN = −0.2 V, +IN = +1.3 V −10.0 ±7 +10.0 µA

1.0 pF

60 dB

= ∞ ±0.5 mV

HYS

– 0.8 V −150 +150 µA

CCI

– 1.8 V −150 +150 µA

CCI

– 1.8 V

CCI

– 0.15 V

CCI

/2 – 0.075 V

CCI

– 0.8 V

CCI

/2 + 0.075 V

CCI

VOD = 250 mV 500 ps VOD = 250 mV 500 ps VOD = 250 mV 750 ps VOD = 250 mV 750 ps

PECL 50 Ω to VDD − 2.0 V V PECL 50 Ω to VDD − 2.0 V V

− 1.05 V

CCO

− 1.95 V

CCO

− 0.81 V

CCO

− 1.54 V

CCO

10% to 90% 500 ps 10% to 90% 500 ps

VOD = 1 V 750 ps

= 20 mV 850 ps

VOD = 1 V 0.5 ps/°C

= 1 V 100 ps

Rev. PrB | Page 3 of 14

ADCMP551/ADCMP552/ADCMP553 Preliminary Technical Data

Parameter Symbol Conditions Min Typ Max Unit

AC PERFORMANCE (continued)

Equivalent Input Rise Time Bandwidth1 BW

Maximum Toggle Rate >50% output swing 650 MHz Minimum Pulse Width PW

MIN

Unit-to-Unit Propagation Delay Skew 100 ps

POWER SUPPLY (ADCMP551/ADCMP552)

Input Supply Current I Output Supply Current I

VCCI

VCCO

Output Supply Current @ 3.3 V with load 62 70 mA Input Supply Voltage V Output Supply Voltage V Positive Supply Differential V Power Dissipation P

CCI

CCO

− V

Power Dissipation Dual, with load 115 140 mW DC Power Supply Rejection Ratio—V DC Power Supply Rejection Ratio—V

CCI

CCO

PSRR PSRR

VCCI

VCCO

POWER SUPPLY (ADCMP553)

Positive Supply Current I

VCC

Positive Supply Current @ 3.3 V with load 35 42 mA Positive Supply Voltage V Power Dissipation P

Power Dissipation Dual, with load 60 75 mW DC Power Supply Rejection Ratio — V

PSRR

VCC

HYSTERESIS (ADCMP552 Only)

Programmable Hysteresis 0 40 mV

0 V to 1 V swing, 2 V/ns 750 MHz

∆tPD < 50 ps 750 ps

@ 3.3 V 12.5 16 mA @ 3.3 V without load 6 9 mA

Dual 3.135 3.3 5.25 V Dual 3.135 3.3 5.25 V –0.2 +2.3 V

CCI

Dual, without load 55 70 mW

70 dB 70 dB

@ 3.3 V without load 9 11 mA

Dual 3.135 3.3 5.25 V Dual, without load 30 40 mW

70 dB

Equivalent input rise time bandwidth assumes a first order input response and is calculated by the following formula: BWEQ = .22/√(tr

input transition time applied to the comparator and tr

is the effective transition time as digitized by the comparator input.

COMP

Rev. PrB | Page 4 of 14

-tr

), where trIN is the 20/80

COMP

Preliminary Technical Data ADCMP551/ADCMP552/ADCMP553

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltages

Input Supply Voltage (V Output Supply Voltage (V Ground Voltage Differential −0.5 V to +0.5 V

Input Voltages

Input Common-Mode Voltage −0.5 V to +3.5 V Differential Input Voltage −4.0 V to +4.0 V Input Voltage, Latch Controls −0.5 V to +5.5 V

Output

Output Current 30 mA

Temperature

Operating Temperature, Ambient −40°C to +85°C Operating Temperature, Junction 125°C Storage Temperature Range −65°C to +150°C

to GND) −0.5 V to +6.0 V

CCI

to GND) −0.5 V to +6.0 V

CCO

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CONSIDERATIONS

The ADCMP551 16-lead QSOP package has a θJA (junction-toambient thermal resistance) of TBD°C/W in still air.

The ADCMP552 20-lead QSOP package has a θ ambient thermal resistance) of TBD°C/W in still air.

The ADCMP553 8-lead MSOP package has a θ ambient thermal resistance) of TBD°C/W in still air.

(junction-to-

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. PrB | Page 5 of 14

ADCMP551/ADCMP552/ADCMP553 Preliminary Technical Data

AGND

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CCO

QB QB V

CCO

LEB LEB AGND –INB +INB HYSB

04722-0-003

Figure 4. ADCMP553 8-Lead MSOP Pin Configuration

QA QA

CCO

LEA LEA V

CCI

–INA +INA

ADCMP551

TOP VIEW

(Not to Scale)

QB QB V

CCO

LEB LEB AGND –INB +INB

04722-0-002

Figure 2. ADCMP551 16-Lead QSOP Pin

Configuration

CCO

ADCMP552

–INA +INA

HYS

CCO

LEA LEA

CCI

TOP VIEW

(Not to Scale)

Figure 3. ADCMP552 20-Lead QSOP Pin

Configuration

Table 3. ADCMP551/ADCMP552/ADCMP553 Pin Function Descriptions

Pin No.

ADCMP551 ADCMP552 ADCMP553

3, 14 1, 4, 17, 20 V 1 2 6 QA

Mnemonic Function

CCO

Logic Supply Terminal. One of Two Complementary Outputs for Channel A. QA is logic high if the

analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the description of Pin LEA for more information.

2 3 5

One of Two Complementary Outputs for Channel A. QA is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the description of Pin LEA for more information.

4 5 2 LEA

One of Two Complementary Outputs for Channel A Latch Enable. In the compare mode (logic high), the output tracks changes at the input of the comparator. In the latch mode (logic low), the output reflects the input state just

prior to the comparator’s being placed in the latch mode. conjunction with LEA.

5 6 1

LEA One of Two Complementary Outputs for Channel A Latch Enable. In the

compare mode (logic high), the output tracks changes at the input of the comparator. In the latch mode (logic low), the output reflects the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in

LEA

conjunction with

6 7 V

CCI

7 8 4 −INA

Input Supply Terminal. Inverting Analog Input of the Differential Input Stage for Channel A. The

inverting A input must be driven in conjunction with the noninverting A input.

8 9 3 +INA

Noninverting Analog Input of the Differential Input Stage for Channel A. The

noninverting A input must be driven in conjunction with the inverting A input. 10 HYSA Programmable Hysteresis. 11 HYSB Programmable Hysteresis. 9 12 +INB

Noninverting Analog Input of the Differential Input Stage for Channel B. The

noninverting B input must be driven in conjunction with the inverting B input. 10 13 −INB

Inverting Analog Input of the Differential Input Stage for Channel B. The

inverting B input must be driven in conjunction with the noninverting B input. 11 14 8 AGND Analog Ground.

LEA

LEA +INA –INA

ADCMP553

TOP VIEW

(Not to Scale)

LEA

must be driven in

04722-0-004

Rev. PrB | Page 6 of 14

Preliminary Technical Data ADCMP551/ADCMP552/ADCMP553

Pin No.

ADCMP551 ADCMP552 ADCMP553

12 15

13 16 LEB

15 18

16 19 QB

7 VCCPositive Supply Terminal.

Mnemonic Function

LEB One of Two Complementary Inputs for Channel B Latch Enable. In the compare

mode (logic low), the output tracks changes at the input of the comparator. In the latch mode (logic high), the output reflects the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven in conjunction

LEB

with One of Two Complementary Inputs for Channel B Latch Enable. In the compare

with One of Two Complementary Outputs for Channel B. QB is logic low if the analog

voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the description of Pin LEB for more information.

One of Two Complementary Outputs for Channel B. voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the description of Pin LEB for more information.

LEB

is logic low if the analog

Rev. PrB | Page 7 of 14

ADCMP551/ADCMP552/ADCMP553 Preliminary Technical Data

TYPICAL PERFORMANCE CHARACTERISTICS

= 3.3 V, V

CCI

–000

= 3.3 V, TA = 25°C, unless otherwise noted.

CCO

–000

TBD

ALL CAPS (Initial caps)

–000

–000 –000 –000 –000 –000

Figure 5. Input Bias Current vs. Input Voltage

–000

ALL CAPS (Initial caps)

TBD

ALL CAPS (Initial caps)

–000

TBD

ALL CAPS (Initial caps)

–000

–000 –000 –000 –000 –000

Figure 8. Input Bias Current vs. Temperature

–000

ALL CAPS (Initial caps)

TBD

ALL CAPS (Initial caps)

–000

–000 –000 –000 –000 –000

Figure 6. Input Offset Voltage vs. Temperature

–000

ALL CAPS (Initial caps)

TBD

ALL CAPS (Initial caps)

–000

–000 –000 –000 –000 –000

Figure 7. Rise Time v s. Temperature

ALL CAPS (Initial caps)

Rev. PrB | Page 8 of 14

–000

–000 –000 –000 –000 –000

–000

ALL CAPS (Initial caps)

Figure 9. Hysteresis vs. ∆Latch

TBD

ALL CAPS (Initial caps)

–000

–000 –000 –000 –000 –000

Figure 10. Fall Time vs. Temperature

ALL CAPS (Initial caps)

Preliminary Technical Data ADCMP551/ADCMP552/ADCMP553

–000

TBD

ALL CAPS (Initial caps)

–000

–000 –000 –000 –000 –000

Figure 11. Propagation Delay vs. Temperature

–000

ALL CAPS (Initial caps)

TBD

–000

TBD

ALL CAPS (Initial caps)

–000

–000 –000 –000 –000 –000

Figure 14. Propagation Delay vs. Common-Mode Voltage

–000

ALL CAPS (Initial caps)

TBD

ALL CAPS (Initial caps)

–000

–000 –000 –000 –000 –000

Figure 12. Propagation Delay vs. Overdrive Voltage

–000

ALL CAPS (Initial caps)

TBD

ALL CAPS (Initial caps)

–000

–000 –000 –000 –000 –000

Figure 13. Rise and Fall of Outputs vs. Time

ALL CAPS (Initial caps)

–000

–000 –000 –000 –000 –000

Figure 15. Propagation Delay Error vs. Pulse Width

ALL CAPS (Initial caps)

Rev. PrB | Page 9 of 14

ADCMP551/ADCMP552/ADCMP553 Preliminary Technical Data

TIMING INFORMATION

LATCH ENABLE

50%

LATCH ENABLE

DIFFERENTIAL

INPUT VOLTAGE

± V

REF

Q OUTPUT

PDL

PDH

PLOH

PLOL

50%

Figure 16. System Timing Diagram

Figure 16 shows the compare and latch features of the ADCMP55x family. Table 4 describes the terms in the diagram.

Table 4. Timing Descriptions

Symbol Timing Description

PDH

Input to Output High Delay

Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output low-to-high transition

PDL

Input to Output Low Delay

Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output high-to-low transition

PLOH

Latch Enable to Output High Delay

Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition

PLOL

Latch Enable to Output Low Delay

Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition

Minimum Hold Time

Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs

Minimum Latch Enable Pulse Width Minimum time the latch enable signal must be high to acquire an input signal change Minimum Setup Time

Minimum time before the negative transition of the latch enable signal that an input signal change must be present to be acquired and held at the outputs

Output Rise Time

Amount of time required to transition from a low to a high output as measured at the 20% and 80% points

Output Fall Time

Amount of time required to transition from a high to a low output as measured at the 20% and 80% points

Voltage Overdrive Difference between the differential input and reference input voltages

04687-0-004

Rev. PrB | Page 10 of 14

Preliminary Technical Data ADCMP551/ADCMP552/ADCMP553

APPLICATION INFORMATION

The ADCMP55x series of comparators are very high speed devices. Consequently, high speed design techniques must be employed to achieve the best performance. The most critical aspect of any ADCMP55x design is the use of a low impedance ground plane. A ground plane, as part of a multilayer board, is recommended for proper high speed performance. Using a continuous conductive plane over the surface of the circuit board can create this, allowing breaks in the plane only for necessary signal paths. The ground plane provides a low inductance ground, eliminating any potential differences at different ground points throughout the circuit board caused by ground bounce. A proper ground plane also minimizes the effects of stray capacitance on the circuit board.

It is also important to provide bypass capacitors for the power supply in a high speed application. A 1 µF electrolytic bypass capacitor should be placed within 0.5 inches of each power supply pin to ground. These capacitors reduce any potential voltage ripples from the power supply. In addition, a 10 nF ceramic capacitor should be placed as close to the power supply pins as possible on the ADCMP55x to ground. These capacitors act as a charge reservoir for the device during high frequency switching.

The LATCH ENABLE input is active low (latched). If the latching function is not used, the LATCH ENABLE input pins may be left open. The internal pull-ups on the latch pins set the latch to transparent mode. If the latch is to be used, valid PECL voltages are required on the inputs for proper operation. The PECL voltages should be referenced to V

Occasionally, one of the two comparator stages within the ADCMP551/ADCMP552 is not used. The inputs of the unused comparator should not be allowed to float. The high internal gain may cause the output to oscillate (possibly affecting the comparator that is being used) unless the output is forced into a fixed state. This is easily accomplished by ensuring that the two inputs are at least one diode drop apart, while also appropriately connecting the LATCH ENABLE and as described previously.

The best performance is achieved with the use of proper PECL terminations. The open-emitter outputs of the ADCMP55x are designed to be terminated through 50 Ω resistors to

− 2.0 V or any other equivalent PECL termination. If high

CCO

speed PECL signals must be routed more than a centimeter, microstrip or stripline techniques may be required to ensure proper transition times and prevent output ringing.

CCI

LATCH ENABLE

inputs

CLOCK TIMING RECOVERY

Comparators are often used in digital systems to recover clock timing signals. High speed square waves transmitted over a distance, even tens of centimeters, can become distorted due to stray capacitance and inductance. Poor layout or improper termination can also cause reflections on the transmission line, further distorting the signal waveform. A high speed comparator can be used to recover the distorted waveform while maintaining a minimum of delay.

OPTIMIZING HIGH SPEED PERFORMANCE

As with any high speed comparator amplifier, proper design and layout techniques should be used to ensure optimal performance from the ADCMP55x. The performance limits of high speed circuitry can easily be a result of stray capacitance, improper ground impedance, or other layout issues.

Minimizing resistance from source to the input is an important consideration in maximizing the high speed operation of the ADCMP55x. Source resistance in combination with equivalent input capacitance can cause a lagged response at the input, thus delaying the output. The input capacitance of the ADCMP55x, in combination with stray capacitance from an input pin to ground, could result in several picofarads of equivalent capacitance. A combination of 3 kΩ source resistance and 5 pF input capacitance yields a time constant of 15 ns, which is significantly slower than the 750 ps capability of the ADCMP55x. Source impedances should be significantly less than 100 Ω for best performance.

Sockets should be avoided due to stray capacitance and inductance. If proper high speed techniques are used, the ADCMP55x should be free from oscillation when the comparator input signal passes through the switching threshold.

COMPARATOR PROPAGATION DELAY DISPERSION

The ADCMP55x has been specifically designed to reduce propagation delay dispersion over an input overdrive range of 100 mV to 1 V. Propagation delay overdrive dispersion is the change in propagation delay that results from a change in the degree of overdrive (how far the switching point is exceeded by the input). The overall result is a higher degree of timing accuracy since the ADCMP55x is far less sensitive to input variations than most comparator designs.

Rev. PrB | Page 11 of 14

ADCMP551/ADCMP552/ADCMP553 Preliminary Technical Data

Propagation delay dispersion is an important specification in critical timing applications such as ATE, bench instruments, and nuclear instrumentation. Overdrive dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (Figure 17). For the ADCMP55x, overdrive dispersion is typically 100 ps as the overdrive is changed from 100 mV to 1 V. This specification applies for both positive and negative overdrive since the ADCMP55x has equal delays for positive- and negative-going inputs.

1.5V OVERDRIVE

LATCH ENABLE

and

. inputs (Figure 23).

–V

ABLE introducing a differential voltage between the LATCH EN

INPUT

INPUT VOLTAGE

20mV OVERDRIVE

± V

REF

DISPERSION

Q OUTPUT

Figure 17. Propagation Delay Dispersion

04687-0-005

COMPARATOR HYSTERESIS

The addition of hysteresis to a comparator is often useful in a noisy environment, or where it is not desirable for the comparator to toggle between states when the input signal is at the switching threshold. The transfer function for a comparator with hysteresis is shown in Figure 18. If the input voltage approaches the threshold from the negative direction, the comparator switches from a 0 to a 1 when the input crosses

/2. The new switching threshold becomes −VH/2. The

comparator remains in a 1 state until the −V crossed coming from the positive direction. In this manner, noise centered on 0 V input does not cause the comparator to switch states unless it exceeds the region bounded by ±V

Positive feedback from the output to the input is often used to produce hysteresis in a comparator (Figure 22). The major problem with this approach is that the amount of hysteresis varies with the output logic levels, resulting in a hysteresis that is not symmetrical around zero.

In the ADCMP552, hysteresis is generated through the programmable hysteresis pin. A resistor from the HYS pin to

creates a current into the part that is used to generate

CCI

hysteresis. Hysteresis generated in this manner is independent of output swing and is symmetrical around the trip point. The hysteresis versus resistance curve is shown in Figure 19.

/2 threshold is

/2.

OUTPUT

04687-0-006

Figure 18. Comparator Hysteresis Transfer Function

–000

TBD

ALL CAPS (Initial caps)

–000

–000 –000 –000 –000 –000

Figure 19. Comparator Hysteresis Transfer Function

MINIMUM INPUT SLEW RATE REQUIREMENT

As for all high speed comparators, a minimum slew rate m be met to ensure that the device does not oscillate when the input crosses the threshold. This oscillation is due in part to t high input bandwidth of the comparator and the parasitics of the package. Analog Devices recommends a slew rate of 1 V/µs or faster to ensure a clean output transition. If slew rates less than 1 V/µs are used, hysteresis should be added to reduce the oscillation.

ALL CAPS (Initial caps)

ust

Another method to implement hysteresis is generated by

Rev. PrB | Page 12 of 14

Preliminary Technical Data ADCMP551/ADCMP552/ADCMP553

TYPICAL APPLICATION CIRCUITS

REF

+ ADCMP551/ ADCMP552/

ADCMP553

–

LATCH

ENABLE

INPUTS

ALL RESISTORS 50Ω

Figure 20. High Speed Sampling Circuits

REF

–V

REF

+ ADCMP551/ ADCMP552/

ADCMP553

–

+ ADCMP551/ ADCMP552/

ADCMP553

–

LATCH

ENABLE

INPUTS

ALL RESISTORS 50Ω

Figure 21. High Speed Window Comparator

CCO

– 2V

OUTPUTS

04722-0-009

04722-0-010

REF

+ ADCMP551/ ADCMP552/ ADCMP553

–

R1 R2

ALL RESISTORS 50Ω

– 2V

CCO

Figure 22. Hysteresis Using Positive Feedback

HYSTERESIS VOLTAGE

ALL RESISTORS 50Ω UNLESS OTHERWISE NOTED

+ ADCMP551/ ADCMP552/

ADCMP553

–

450Ω

– 2V

CCO

Figure 23. Hysteresis Using Latch Enable Input

+ ADCMP551/

ADCMP552/

ADCMP553

–

50Ω

100Ω100Ω

OUTPUTS

50Ω

04722-0-011

04722-0-012

CCO

– 2V)× 2

04722-0-013

Figure 24. How to Interface a PECL Output to an

Instrument with a 50 Ω to Ground Input

Rev. PrB | Page 13 of 14

ADCMP551/ADCMP552/ADCMP553 Preliminary Technical Data

OUTLINE DIMENSIONS

0.341 BSC

0.065

0.049

0.010

0.004

COPLANARITY

0.004

Figure 26. 16-Lead Shrink Small Outline Package[QSOP]

PIN 1

0.010

0.004

OPLANARIT

0.004

0.193 BSC

0.012

0.008

0.154 BSC

0.069

0.053

SEATING PLANE

0.236 BSC

0.010

0.006

PIN 1

0.025 BSC

COMPLIANT TO JEDEC STANDARDS MO-137AB

(RQ-16)

Dimensions shown in inches

20 11

0.065

0.049

BSC

0.012

0.008

0.025

COMPLIANT TO JEDEC STANDARDS MO-137AD

0.069

0.053

SEATING PLANE

0.154 BSC

0.236 BSC

0.010

0.006

8° 0°

Figure 25. 20-Lead Shrink Small Outline Package [QSOP]

(RQ-20)

Dimensions shown in inches

BSC

3.00

BSC

PIN 1

0.65 BSC

0.15

0.00

8° 0°

0.050

0.016

0.38

0.22

COPLANARITY

0.10 COMPLIANT TO JEDEC STANDARDS MO-187AA

Figure 27. 8-Lead Mini Small Outline Package [MSOP]

0.050

0.016

3.00

4.90 BSC

1.10 MAX

0.23

SEATING PLANE

0.08

(RM-8)

Dimensions shown in millimeters

8° 0°

0.80

0.60

0.40

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADCMP551BRQ −40°C to +85°C 16-Lead QSOP RQ-16 ADCMP552BRQ −40°C to +85°C 20-Lead QSOP RQ-20 ADCMP553BRM −40°C to +85°C 8-Lead MSOP RM-8

PR04687–0–7/04(PrB)

Rev. PrB | Page 14 of 14

Datasheet ADCMP551, ADCMP552, ADCMP553 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL CONSIDERATIONS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TIMING INFORMATION

APPLICATION INFORMATION

CLOCK TIMING RECOVERY

OPTIMIZING HIGH SPEED PERFORMANCE

COMPARATOR PROPAGATION DELAY DISPERSION

COMPARATOR HYSTERESIS

MINIMUM INPUT SLEW RATE REQUIREMENT

TYPICAL APPLICATION CIRCUITS

OUTLINE DIMENSIONS

ORDERING GUIDE