Datasheet ADCMP341, ADCMP343 Datasheet (ANALOG DEVICES)

Dual 0.275% Comparators and Reference
V
V
VINA
V
V
VINA
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FEATURES

400 mV ± 0.275% threshold User programmable hysteresis via resistor string Supply range: 1.7 V to 5.5 V Low quiescent current: 6.5 μA typical Input range includes ground Low input bias current: ±5 nA maximum Open-drain outputs Supports wired-AND connections Input polarities:
ADCMP341 noninverting ADCMP343 inverting
Small SOT-23 package

APPLICATIONS

Portable applications Li-Ion monitoring Handheld instruments LED/relay driving Optoisolator driving Control systems

GENERAL DESCRIPTION

The ADCMP341/ADCMP343 consist of two low power, high accuracy comparators with a 400 mV reference in an 8-lead SOT-23 package. Operating within a supply range of 1.7 V to
5.5 V, the devices only draw 6.5 μA (typical), making them ideal for low voltage system monitoring and portable applications.
Hysteresis is determined using three resistors in a string configura­t
ion with the upper and lower tap points connected to the ±INA_U and ±INA_L pins of each comparator, respectively. The state of the outputs of the comparators selects which pin is internally connected to the comparators input. Therefore, a change of state in the comparators output results in one of the inputs being switched in to the comparator and the other being switched out. This provides the user with a fully flexible and accurate method of setting the hysteresis. One input of each comparator is internally connected to the reference. The other input is available externally, via an internal mux, through pins ±INA_U or ±INA_L. The state of the output determines which of these pins is connected at any one time.
The comparator outputs are open-drain with the output stage sinkin
g capability guaranteed greater than 5 mA over temperature. The ADCMP341 has noninverting inputs and the ADCMP343 has inverting inputs. The devices are suitable for portable, commercial, industrial, and automotive applications.
with Programmable Hysteresis
ADCMP341/ADCMP343

FUNCTIONAL BLOCK DIAGRAMS

DD
ADCMP341
R1
+INA_U
+INA_L
R2
R3
INB
+INB_U
+INB_L
R1
–INA_U
–INA_L
R2
R3
INB
–INB_U
–INB_L
OUTA
1
V
IN
2
CH1 2.00V CH2 500mV
Figure 3. Hysteresis prog
MUXMUX
400mV
GND
Figure 1. ADCMP341
DD
ADCMP343
MUXMUX
400mV
GND
Figure 2. ADCMP343
M100ms
rammed to 513 mV @ V
OUTA
OUTB
06500-001
OUTA
OUTB
06500-002
R1 = 22k R2 = 2.2k R3 = 6.2k
on ADCMP341
IN
6500-029
Rev. 0
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
ADCMP341/ADCMP343
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Characteristics .............................................................. 4
ESD Caution.................................................................................. 4
Pin Configurations and Function Descriptions ........................... 5

REVISION HISTORY

2/07—Revision 0: Initial Version
Typical Performance Characteristics..............................................6
Application Information................................................................ 10
Comparators and Internal Reference ...................................... 10
Power Supply............................................................................... 10
Inputs........................................................................................... 10
Outputs........................................................................................ 10
Programming Hysteresis ........................................................... 10
Layout Recommendations ........................................................ 10
Outline Dimensions....................................................................... 11
Ordering Guide .......................................................................... 11
Rev. 0 | Page 2 of 12
ADCMP341/ADCMP343
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SPECIFICATIONS

VDD = 1.7 V to 5.5 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
THRESHOLDD
Threshold Voltage 396.6 400.4 404.3 mV VDD = 1.7 V, TA = 25°C
399.3 400.4 401.5 mV VDD = 3.3 V, TA = 25°C
398.5 400.4 402.2 mV VDD = 5.5 V, TA = 25°C
395.0 400.4 405.8 mV VDD = 1.7 V, 0°C ≤ TA ≤ 70°C
397.4 400.4 403.4 mV VDD = 3.3 V, 0°C ≤ TA ≤ 70°C
396.9 400.4 403.7 mV VDD = 5.5 V, 0°C ≤ TA ≤ 70°C
391.2 400.4 407.7 mV VDD = 1.7 V, −40°C ≤ TA ≤ +125°C
393.4 400.4 405.6 mV VDD = 3.3 V, −40°C ≤ TA ≤ +125°C
393.2 400.4 405.8 mV VDD = 5.5 V, −40°C ≤ TA ≤ +125°C Threshold Voltage Accuracy ±0.275 % TA = 25°C, VDD = 3.3 V Threshold Voltage Temperature Coefficient 16 ppm/°C
POWER SUPPLY
Supply Current 6.5 9 μA VDD = 1.7 V
7.0 10 μA VDD = 5.5 V INPUT CHARACTERISTICS
Input Bias Current 0.01 5 nA VDD = 1.7 V, VIN = VDD
0.01 5 nA VDD = 1.7 V, VIN = 0.1 V
OPEN-DRAIN OUTPUTS
Output Low Voltage 140 220 mV VDD = 5.5 V, I Output Leakage Current
0.01 1 μA VDD = 1.7 V, V
DYNAMIC PERFORMANCE
High-to-Low Propagation Delay 10 μs VDD = 5 V, VOL = 400 mV Low-to-High Propagation Delay 8 μs VDD = 5 V, VOH = 0.9 × VDD Output Rise Time 0.5 μs VDD = 5 V, VO = (0.1 to 0.9) × VDD Output Fall Time 0.07 μs VDD = 5 V, VO = (0.1 to 0.9) × VDD
1
RL = 100 kΩ, VO = 2 V swing.
2
10 mV input overdrive.
3
VIN = 40 mV overdrive.
4
RL = 10 kΩ.
1
2
3
2, 4
140 220 mV VDD = 1.7 V, I
0.01 1 μA VDD = 1.7 V, V
= 3 mA
OUT
= 5 mA
OUT
OUT
OUT
= VDD
= 5.5 V
Rev. 0 | Page 3 of 12
ADCMP341/ADCMP343
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ABSOLUTE MAXIMUM RATINGS

Table 2.
Parameter Rating
VDD −0.3 V to +6 V ±INA_U, ±INA_L, ±INB_U, ±INB_L −0.3 V to +6 V OUTA, OUTB −0.3 V to +6 V Operating Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C Lead Temperature
Soldering (10 sec) 300°C Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA Unit
8-Lead SOT-23 211.5 °C/W

ESD CAUTION

Rev. 0 | Page 4 of 12
ADCMP341/ADCMP343
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

OUTA
+INA_U
+INA_L
GND
1
2
ADCMP341
TOP VIEW
(Not to Scale)
3
4
8
7
6
5
OUTB
V
DD
+INB_U
+INB_L
6500-003
Figure 4. ADCMP341 Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 OUTA Open-Drain Output for Comparator A. 2 ±INA_U
Monitors Analog Input Voltage on Comparator A. Connect to the upper tap point of the resistor string. Connect internally to the noninverting input on the ADCMP341 or the inverting pin on the ADCMP343 via a mux controlled by the output level on Comparator A. The other input of Comparator A is connected to a 400 mV reference.
3 ±INA_L
Monitors Analog Input Voltage on Comparator A. Connect to the lower tap point of the resistor string. Connect internally to the noninverting input on the ADCMP341 or the inverting pin on the ADCMP343 via a mux controlled
by the output level on Comparator A. The other input of Comparator A is connected to a 400 mV reference. 4 GND 5 ±INB_L
Ground.
Monitors Analog Input Voltage on Comparator B. Connect to the lower tap point of the resistor string. Connect
internally to the noninverting input on the ADCMP341 or the inverting pin on the ADCMP343 via a mux controlled
by the output level on Comparator B. The other input of Comparator B is connected to a 400 mV reference. 6 ±INB_U
Monitors Analog Input Voltage on Comparator B. Connect to the upper tap point of the resistor string. Connect
internally to the noninverting input on the ADCMP341 or the inverting pin on the ADCMP343 via a mux controlled
by the output level on Comparator B. The other input of Comparator B is connected to a 400 mV reference. 7 V
Power Supply Pin.
DD
8 OUTB Open-Drain Output for Comparator B.
OUTA
–INA_U
–INA_L
GND
1
2
ADCMP343
TOP VIEW
(Not to Scale)
3
4
8
7
6
5
OUTB
V
DD
–INB_U
–INB_L
Figure 5. ADCMP343 Pin Configuration
6500-004
Rev. 0 | Page 5 of 12
ADCMP341/ADCMP343
www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

60
50
40
VDD = 5V
= 25°C
T
A
404
402
1 2 3 4
FOUR TYPI CAL PARTS V
= 5V
DD
30
20
PERCENT OF UNI TS (%)
10
0
394 395 396 397 398 399 400 401 402 403 404 405 406
RISING INPUT THRESHOL D VOLTAG E (mV)
Figure 6. Distribution of Rising Input Threshold Voltage
401
TA = –40°C
400
T
= +25°C
A
T
= +85°C
A
T
= +125°C
A
SUPPLY VOLTAGE (V)
RISING INPUT THRESHOL D VOLTAG E (mV)
399
398
397
396
395
1.7 5.75.24.74.23.73.22.72.2
Figure 7. Rising Input Threshold Voltage vs. Supply Voltage
400
398
RISING INPUT THRESHOLD VOLTAGE (mV)
396
–40 –20 1200 20406080100
06500-005
TEMPERATURE (° C)
6500-006
Figure 9. Rising Input Threshold Voltage vs. Temperature
1
0
–1
–2
–3
THRESHOLD SHIFT (mV)
–4
–5
1.5 2.52.42.32.22.12. 01.91.81.71.6
06500-007
SUPPLY VOLTAGE (V)
TA = –40°C TA = +25°C TA = +85°C TA = +125°C
06500-009
Figure 10. Minimum Supply Voltage
10
NO LOAD CURRENT
9
8
T
= +85°C
A
7
6
SUPPLY CURRENT (mA)
5
4
1.72.22.73.23.74.24.7
= –40°C
T
A
SUPPLY VOLTAGE (V)
TA = +125°C
= +25°C
T
A
5.2
06500-008
Figure 8. Quiescent Supply Current vs. Supply Voltage
Rev. 0 | Page 6 of 12
50
40
30
20
SUPPLY CURRENT (µA)
10
0
00.51.0
T
TA = +125°C
SUPPLY VOLTAGE (V)
= +85°C
A
T
= +25°C
A
Figure 11. Start-Up Supply Current
T
= –40°C
A
1.5
06500-010
ADCMP341/ADCMP343
www.BDTIC.com/ADI
1000
TA = –40°C
100
10
SUPPLY CURRENT (µA)
1
0.001 1001010.10.01
OUTPUT SI NK CURRENT (mA)
Figure 12. Supply Current vs. Output Sink Current
1000
TA = 85°C
100
10
SUPPLY CURRENT (µA)
VDD = 5.0V VDD = 3.3V VDD = 2.5V VDD = 1.7V
VDD = 5.0V VDD = 3.3V VDD = 2.5V VDD = 1.7V
6500-011
1000
TA = 25°C
100
10
SUPPLY CURRENT (µ A)
1
0.001 1001010.10.01
OUTPUT SI NK CURRENT (mA)
Figure 15. Supply Current vs. Output Sink Current
10k
TA = +125°C
1k
100
= +85°C
T
= –40°C
T
A
A
T
= +25°C
A
10
INPUT BIAS CURRENT (nA)
1
VDD = 5.0V VDD = 3.3V VDD = 2.5V VDD = 1.7V
CURRENT IS GOING OUT OF THE DEVICE. V
= 5V
DD
IB
< 0V
–0.3V < V
06500-012
1
0.001 1001010.10.01
OUTPUT SI NK CURRENT (mA)
Figure 13. Supply Current vs. Output Sink Current
3
1
–1
–3
INPUT BIAS CURRENT (nA)
–5
CURRENT IS POSITIVE GOING INTO THE DEVICE.
V
= 5V
DD
0V < V
< 1V
–7
IB
00.2 0.6
0.4 0.8
INPUT VOLTAGE (V)
Figure 14. Low Level Inpu t Bias Cur rent
TA = +125°C TA = +85°C TA = +25°C TA = –40°C
1.0
0.1 –0.3 –0.2 –0.1
06500-013
INPUT VOLTAGE (V)
0
06500-014
Figure 16. Below Ground Input Bias Current
10
TA = +125°C
1
TA = +85°C
= 5V
> 1V
TA = +25°C
INPUT VOLTAGE (V)
0.1
INPUT BIAS CURRENT (nA)
CURRENT IS GO ING INTO THE DEVICE V
DD
V
IB
0.01 12 4
06500-015
TA = –40°C
3
5
06500-016
Figure 17. High Level Input Bias Current
Rev. 0 | Page 7 of 12
ADCMP341/ADCMP343
www.BDTIC.com/ADI
1000
100
TA = 25°C
VDD = 5.0V VDD = 3.3V VDD = 2.5V VDD = 1.8V
1000
100
= –40°C
T
A
VDD = 5.0V VDD = 3.3V VDD = 2.5V VDD = 1.8V
10
OUTPUT SATURATION VOLTAGE (mV)
1
0.001 0.10.01
OUTPUT SI NK CURRENT (mA)
101
Figure 18. Output Saturation Voltage vs. Output Sink Current
1000
TA = 85°C
VDD = 5.0V VDD = 3.3V VDD = 2.5V VDD = 1.8V
100
10
OUTPUT SATURATION VOLTAGE (mV)
1
0.001 0.1
OUTPUT SI NK CURRENT (mA)
100.01 1
Figure 19. Output Saturation Voltage vs. Output Sink Current
10
OUTPUT SATURATION VOLTAGE (mV)
1
0.001 0.1
06500-017
OUTPUT SI NK CURRENT (mA)
100.01 1
06500-018
Figure 21. Output Saturation Voltage vs. Output Sink Current
= 5V
V
DD
70
60
50
40
30
20
SHORT-CIRCUIT CURRENT (mA)
10
0
6500-019
02804
T
= +25°C
A
T
OUTPUT VO LTAGE (V )
= +85°C
A
T
= –40°C
A
TA = +125°C
06500-020
Figure 22. Short-Circuit Current vs. Output Voltage
TA = 25°C
60
50
40
30
20
SHORT-CIRCUIT CURRENT (mA)
10
0
02704
OUTPUT VO LTAGE (V )
VDD = 5.0V
V
V
V
Figure 20. Short-Circuit Current vs. Output Voltage
DD
DD
DD
= 3.3V
= 2.5V
= 1.8V
06500-021
VDD = 5V
TA = +125°C
1
T
= +85°C
A
T
= +25°C
0.1
0.01
OUTPUT LEAKAGE CURRENT (nA)
0.001 01231045
OUTPUT VO LTAGE (V )
A
T
= –40°C
A
Figure 23. Output Leakage Current vs. Output Voltage
6500-022
Rev. 0 | Page 8 of 12
ADCMP341/ADCMP343
www.BDTIC.com/ADI
60
TA = 25°C
50
40
30
20
PROPAGATI ON DELAY (µ s)
10
0
0 204060
INPUT OVERDRIVE (mV)
Figure 24. Propagation Delay vs. Input Overdrive
NON INV (OUTA)
2
INV (OUTB)
3
VIN (+INA, –INB)
LH NON INV LH INV HL NON INV HL INV
80 100
6500-023
100
VDD = 5V
= 20pF
C
L
= 25°C
T
A
10
RISE
1
0.1
RISE AND FALL TIMES (µs)
FALL
0.01
0.1 1
OUTPUT PULL-UP RESISTOR (kΩ)
10
100 1000
Figure 26. Rise and Fall Times vs. Output Pull-Up Resistor
OUTA
1
R1 = 22k R2 = 2.2k R3 = 6.2k
06500-025
1
CH1 50.0mV
CH3 5.00V
CH2 5.00V M 20.0µs CH1 7mV
Figure 25. Noninverting and Inverting Comparators Propagation Delay
V
IN
2
06500-024
CH1 2.00V CH2 500mV
M100ms
6500-026
Figure 27. Hysteresis Programmed to ~513 mV at Top of Input String
ysteresis at ADCMP341 Pins ≈ 104 mV)
(H
Rev. 0 | Page 9 of 12
ADCMP341/ADCMP343
V
(
)
V
VINA
V
www.BDTIC.com/ADI

APPLICATION INFORMATION

II >>
The ADCMP341/ADCMP343 are dual, low power comparators with a built-in 400 mV reference that operates from 1.7 V to 5.5 V. The comparators are 0.275% accurate with fully programmable hysteresis, implemented using a new technique of a three-resistor string on the input. These open-drain outputs are capable of sinking up to 40 mA.

COMPARATORS AND INTERNAL REFERENCE

Each of the comparators has one input available externally; the other comparator inputs are connected internally to the 400 mV reference. The ADCMP341 has two noninverting comparators and the ADCMP343 has two inverting comparators.
There are two input pins available to each comparator. However, th
ese two input pins (±INx_U, ±INx_L) connect to the same input leg of the comparator via a muxing system. This is to provide fully programmable rising and falling trip points. The output of the comparator determines which pin is connected to the input of the same comparator. Using
mple, when OUTA is high, +INA_U is connected to the
exa
Figure 28 as an
comparator input. When the input voltage drops and passes below the 400 mV reference, the output goes low. This in turn disconnects +INA_U from the comparator and connects +INA_L. This leg of the string is at a lower voltage and thus instantaneously the effect of hysteresis is applied. Therefore, using a resistor string on the input as shown in
oltages for the rising and falling trip points can be programmed
v
Figure 28, the
by selecting the appropriate resistors in the string.

POWER SUPPLY

The ADCMP341/ADCMP343 are designed to operate from 1.7 V to 5.5 V. A 0.1 μF decoupling capacitor is recommended between
and GND.
V
DD

INPUTS

The comparator inputs are limited to the maximum VDD voltage range. The voltage on these inputs can be above V above the maximum allowed V
voltage.
DD
but never
DD

OUTPUTS

The open-drain comparator outputs are limited to the maximum specified V
voltage range, regardless of the VDD voltage. These
DD
outputs are capable of sinking up to 40 mA. Outputs can be tied together to provide a common output signal.

PROGRAMMING HYSTERESIS

When choosing the resistor values, the input bias current must be considered as a potential source of error. Begin by choosing a resistor value for R3, which takes into account the acceptable error introduced by the maximum specified input bias current. To reduce this error, the current flowing through the Resistor R3 should be considerably greater than the input bias current.
R3
R3 is therefore
R =
Now R2 can be calculated from the following:
=32
R
R1 can then be calculated using the following equation:
where:
is the specified on chip reference.
V
REF
is the maximum specified input bias current.
I
BIAS
R1, R2, and R3 are the three resistors as shown in Figure 28. I
is the current flowing through R3.
R3
V
is the desired falling trip voltage and lower of the two.
FALLING
is the desired rising trip voltage and higher of the two.
V
RISING

LAYOUT RECOMMENDATIONS

Correct layout is very important to increase noise immunity. Long tracks from the input resistors to the device can lead to noise being coupled onto the inputs. To avoid this, it is best to place the input resistors as close as possible to the device. It is also recommended that a GND plane is used under this layout. The combination of small hysteresis and the use of a large R3 resistor further increases susceptibility to noise. In this case, a decoupling capacitor (CA, CB) may be required on the ±INx_U node to help reduce any noise. A recommended layout example can be seen in
BIAS
REF
I
33R
VVR
FALLINGRISING
V
FALLING
V
⎜ ⎜
RISING
RR
⎜ ⎝
R1
R2
R3
Figure 28. Programming Hysteresis Example
V
REF
+INA_U
+INA_L
×=
2131 R
DD
ADCMP341
MUX
400mV
Figure 29.
GND
OUTA
INA
R1A
R2A
R3A
CA CB
Figure 29. Recommended Layout Example
DD
C1
U1
OUTA
OUTB
INB
R1B
R2B
R3B
6500-027
6500-028
Rev. 0 | Page 10 of 12
ADCMP341/ADCMP343
www.BDTIC.com/ADI

OUTLINE DIMENSIONS

2.90 BSC
2
1.95 BSC
56
0.65 BSC
2.80 BSC
1.45 MAX
SEATING PLANE
0.22
0.08
8° 4° 0°
0.60
0.45
0.30
1.60 BSC
PIN 1
INDICATOR
1.30
1.15
0.90
0.15 MAX
847
13
0.38
0.22
COMPLIANT TO JEDEC STANDARDS MO-178-B A
Figure 30. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dim
ensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding
ADCMP341YRJZ-REEL7 ADCMP343YRJZ-REEL7
1
Z = Pb-free part.
1
1
–40°C to +125°C 8-Lead SOT-23 RJ-8 M8Y –40°C to +125°C 8-Lead SOT-23 RJ-8 M91
Rev. 0 | Page 11 of 12
ADCMP341/ADCMP343
www.BDTIC.com/ADI
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06500-0-2/07(0)
Rev. 0 | Page 12 of 12
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