ANALOG DEVICES ADCLK854 Service Manual

1.8 V, 12-LVDS/24-CMOS Output,

FEATURES

2 selectable differential inputs Selectable LVDS/CMOS outputs Up to 12 LVDS (1.2 GHz) or 24 CMOS (250 MHz) outputs <12 mW per channel (100 MHz operation) 54 fs rms integrated jitter (12 kHz to 20 MHz) 100 fs rms additive broadband jitter

2.0 ns propagation delay (LVDS) 135 ps output rise/fall (LVDS) 70 ps output-to-output skew (LVDS) Sleep mode Pin programmable control

1.8 V power supply

APPLICATIONS

Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation

Low Power Clock Fanout Buffer

ADCLK854

FUNCTIONAL BLOCK DIAGRAM

ADCLK854

LVDS/

VS/2

V

REF

CLK0

CLK1

IN_SEL

CTRL_A

CTRL_B

CMOS

LVDS/ CMOS

OUT0 (OUT0A)

OUT0 (OUT0B)

OUT1 (OUT1A)

OUT1 (OUT1B)

OUT2 (OUT2A)

OUT2 (OUT2B)

OUT3 (OUT3A)

OUT3 (OUT3B)

OUT4 (OUT4A)

OUT4 (OUT4B)

OUT5 (OUT5A)

OUT5 (OUT5B)

OUT6 (OUT6A)

OUT6 (OUT6B)

OUT7 (OUT7A)

OUT7 (OUT7B)

GENERAL DESCRIPTION

The ADCLK854 is a 1.2 GHz/250 MHz LVDS/CMOS fanout buffer optimized for low jitter and low power operation. Possible configurations range from 12 LVDS to 24 CMOS outputs, including combinations of LVDS and CMOS outputs. Three control lines are used to determine whether fixed blocks of outputs (three banks of four) are LVDS or CMOS outputs.

The ADCLK854 offers two selectable inputs and a sleep mode feature. The IN_SEL pin state determines which input is fanned out to all the outputs. The SLEEP pin enables a sleep mode to power down the device.

The inputs accept various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS. Tabl e 8 provides interface options for each type of connection.

This device is available in a 48-pin LFCSP package. It is specified for operation over the standard industrial temperature range of

−40°C to +85°C.

CTRL_C

SLEEP

LVDS/ CMOS

Figure 1.

OUT8 (OUT8A)

OUT8 (OUT8B)

OUT9 (OUT9A)

OUT9 (OUT9B)

OUT10 (OUT10A)

OUT10 (OUT10B)

OUT11 (OUT11A)

OUT11 (OUT11B)

07218-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infrin gements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADCLK854

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics ............................................................. 3

Timing Characteristics ................................................................ 4

Clock Characteristics ................................................................... 5

Logic and Power Characteristics ................................................ 5

Absolute Maximum Ratings ............................................................ 6

Determining Junction Temperature .......................................... 6

ESD Caution .................................................................................. 6

Thermal Performance .................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ..............................................9

Functional Description .................................................................. 12

Clock Inputs ................................................................................ 12

AC-Coupled Input Applications ............................................... 12

Clock Outputs ............................................................................. 12

Control and Function Pins ........................................................ 13

Power Supply ............................................................................... 13

Applications Information .............................................................. 14

Using the ADCLK854 Outputs for ADC Clock Applications

....................................................................................................... 14

LVDS Clock Distribution .......................................................... 14

CMOS Clock Distribution ........................................................ 14

Input Termination Options ....................................................... 15

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 16



REVISION HISTORY

4/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 16

ADCLK854

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Typical (Typ) values are given for VS = 1.8 V and TA = 25°C, unless otherwise noted. Minimum (Min) and maximum (Max) values are given over the full V

Table 1. Clock Inputs and Outputs

Parameter Symbol Min Typ Max Unit Conditions

CLOCK INPUTS Differential input

Input Sensitivity, Single-Ended 150 mV p-p

LVDS CLOCK OUTPUTS

CMOS CLOCK OUTPUTS Single-ended; termination = open; OUTx and

= 1.8 V ± 5% and TA = −40°C to +85°C variation, unless otherwise noted. Input slew rate > 1 V/ns, unless otherwise noted.

S

Input Frequency 0 1200 MHz Input Sensitivity, Differential 150 mV p-p Jitter performance improves with higher slew

rates (greater voltage swing)

Input Level 1.8 V p-p Larger voltage swings can turn on the protection

diodes and degrade jitter performance Input Common-Mode Voltage VCM V Input Common-Mode Range V

0.4 VS − 0.4 V Inputs dc-coupled with 200 mV p-p signal applied

CMR

/2 − 0.1 VS/2 + 0.5 V Inputs are self-biased; enables ac coupling

S

Input Voltage Offset 30 mV

CLKx ac-coupled;

ac bypassed to ground

CLKx

Input Resistance (Differential) 7 kΩ Input Capacitance CIN 2 pF Input Bias Current (Each Pin) −350 +350 µA Full input swing

Termination = 100 Ω; differential (OUTx,

OUTx

)

Output Frequency 1200 MHz See Figure 9 for swing vs. frequency Output Voltage Differential VOD 247 344 454 mV

Delta VOD VOD 50 mV

Offset Voltage VOS 1.125 1.25 1.375 V

Delta VOS VOS 50 mV

Short-Circuit Current ISA, ISB 3 6 mA Each pin (output shorted to GND)

in phase

OUTx

Output Frequency 250 MHz With 10 pF load per output; see Figure 16 for

swing vs. frequency Output Voltage High VOH V

− 0.1 V @ 1 mA load

S

Output Voltage Low VOL 0.1 V @ 1 mA load Output Voltage High VOH V

− 0.35 V @ 10 mA load

S

Output Voltage Low VOL 0.35 V @ 10 mA load Reference Voltage V

REF

Output Voltage VS/2 − 0.1 VS/2 VS/2 + 0.1 V ±500 µA Output Resistance 60 Ω Output Current 500 µA

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ADCLK854

TIMING CHARACTERISTICS

Table 2. Timing Characteristics

Parameter Symbol Min Typ Max Unit Conditions

LVDS OUTPUTS Termination = 100  differential; 3.5 mA

Output Rise/Fall Time tR , tF 135 235 ps 20% to 80% measured differentially Propagation Delay, Clock-to-LVDS Output tPD 1.5 2.0 2.7 ns V

Temperature Coefficient 2.0 ps/°C

Output Skew

1

LVDS Outputs in the Same Bank 50 ps All LVDS Outputs

On the Same Part 65 ps Across Multiple Parts 390 ps

Additive Time Jitter

Integrated Random Jitter 54 fs rms BW = 12 kHz to 20 MHz; clock = 1000 MHz 74 fs rms BW = 50 kHz to 80 MHz; clock = 1000 MHz 86 fs rms BW = 10Hz to 100 MHz; clock = 1000 MHz Broadband Random Jitter

2

150 fs rms Input slew = 1 V/ns, see Figure 11

Crosstalk Induced Jitter 260 fs rms Calculated from spur energy with an

CMOS OUTPUTS

Output Rise/Fall Time tR, tF 525 950 ps 20% to 80%; C Propagation Delay, Clock-to-CMOS Output tPD 2.5 3.2 4.2 ns 10 pF load

Temperature Coefficient 2.2 ps/°C

Output Skew

1

CMOS Outputs in the Same Bank 155 ps All CMOS Outputs

On the Same Part 175 ps Across Multiple Parts 640 ps

Additive Time Jitter

Integrated Random Jitter 56 fs rms BW = 12 kHz to 20 MHz; clock = 200 MHz

Broadband Random Jitter

2

100 fs rms Input slew = 2 V/ns, see Figure 11

Crosstalk Induced Jitter 260 fs rms Calculated from spur energy with an

LVDS-TO-CMOS OUTPUT SKEW

LVDS Output(s) and CMOS Output(s) on the

3

0.8 1.6 ns CMOS load = 10 pF and LVDS load = 100 Ω

Same Part

1

This is the difference between any two similar delay paths while operating at the same voltage and temperature.

2

Calculated from the SNR of the ADC method.

3

Measured at the rising edge of the clock signal.

= V

ICM

, VID = 0.5 V

REF

interferer 10 MHz offset from the carrier

= 10 pF

LOAD

interferer 10 MHz offset from the carrier

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ADCLK854

CLOCK CHARACTERISTICS

Table 3. Clock Output Phase Noise

Parameter Min Typ Max Unit Conditions

CLOCK-TO-LVDS ABSOLUTE PHASE NOISE Input slew rate > 1 V/ns

1000 MHz −90 dBc/Hz @ 10 Hz offset

−108 dBc/Hz @ 100 Hz offset

−117 dBc/Hz @ 1 kHz offset

−126 dBc/Hz @ 10 kHz offset

−135 dBc/Hz @ 100 kHz offset

−141 dBc/Hz @ 1 MHz offset

−146 dBc/Hz @ 10 MHz offset

CLOCK-TO-CMOS ABSOLUTE PHASE NOISE Input slew rate > 1 V/ns

200 MHz −101 dBc/Hz @ 10 Hz offset

−119 dBc/Hz @ 100 Hz offset

−127 dBc/Hz @ 1 kHz offset

−138 dBc/Hz @ 10 kHz offset

−147 dBc/Hz @ 100 kHz offset

−153 dBc/Hz @ 1 MHz offset

−156 dBc/Hz @ 10 MHz offset

LOGIC AND POWER CHARACTERISTICS

Table 4. Control Pin Characteristics

Parameter Symbol Min Typ Max Unit Conditions

CONTROL PINS (IN_SEL, CTRL_x, SLEEP)1

Logic 1 Voltage VIH V Logic 0 Voltage VIL 0.4 V Logic 1 Current IIH 5 8 20 A Logic 0 Current IIL −5 +5 A Capacitance 2 pF

POWER

Supply Voltage Requirement VS 1.71 1.8 1.89 V VS = 1.8 V ± 5% LVDS Outputs Full operation

LVDS @ 100 MHz 84 100 mA All outputs enabled as LVDS and loaded, RL = 100  LVDS @ 1200 MHz 175 215 mA All outputs enabled as LVDS and loaded, RL = 100 

CMOS Outputs

Full operation

CMOS @ 100 MHz 115 140 mA All outputs enabled as CMOS and loaded, CL = 10 pF CMOS @ 250 MHz 265 325 mA All outputs enabled as CMOS and loaded, CL = 10 pF

SLEEP

Power Supply Rejection

2

LVDS

CMOS

1

These pins each have a 200 kΩ internal pull-down resistor.

2

Change in t

per change in VS.

PD

3 mA SLEEP pin pulled high; does not include power dissipated

PSR

− 0.4 V

S

0.9 ps/mV

t

PD

1.2 ps/mV

t

PD

in the external resistors

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