ANALOG DEVICES ADCLK846 Service Manual

1.8 V, 6 LVDS/12 CMOS Outputs

FEATURES

Selectable LVDS/CMOS outputs Up to 6 LVDS (1.2 GHz) or 12 CMOS (250 MHz) outputs <16 mW per channel (100 MHz operation) 54 fs integrated jitter (12 kHz to 20 MHz) 100 fs additive broadband jitter

2.0 ns propagation delay (LVDS) 135 ps output rise/fall (LVDS) 65 ps output-to-output skew (LVDS) Sleep mode Pin-programmable control

1.8 V power supply

APPLICATIONS

Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation

Low Power Clock Fanout Buffer

ADCLK846

FUNCTIONAL BLOCK DIAGRAM

LVDS/CMOS

Figure 1.

OUT0 (OUT0A)

OUT0 (OUT0B)

OUT1 (OUT1A)

OUT1 (OUT1B)

OUT2 (OUT2A)

OUT2 (OUT2B)

OUT3 (OUT3A)

OUT3 (OUT3B)

OUT4 (OUT4A)

OUT4 (OUT4B)

OUT5 (OUT5A)

OUT5 (OUT5B)

7226-001

V

REF

CLK

CTRL_A

CTRL_B

SLEEP

ADCLK846

GENERAL DESCRIPTION

The ADCLK846 is a 1.2 GHz/250 MHz, LVDS/CMOS, fanout buffer optimized for low jitter and low power operation. Possible configurations range from 6 LVDS to 12 CMOS outputs, including combinations of LVDS and CMOS outputs. Two control lines are used to determine whether fixed blocks of outputs are LVDS or CMOS outputs.

The clock input accepts various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS.

Tabl e 8 provides interface options for each type of connection. The SLEEP pin enables a sleep mode to power down the device.

This device is available in a 24-pin LFCSP package. It is specified for operation over the standard industrial temperature range of

−40°C to +85°C.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADCLK846

REVISION HISTORY

5/10—Rev. A to Rev. B

Changes to Integrated Random Jitter Conditions ........................ 4

6/09—Rev. 0 to Rev. A

No Content Updates ...................................................... Throughout

4/09—Revision 0: Initial Version

Rev. B | Page 2 of 16

ADCLK846

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Typical values are given for VS = 1.8 V and TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full V

= 1.8 V ± 5% and TA = −40°C to +85°C variations, unless otherwise noted. Input slew rate > 1 V/ns, unless otherwise noted.

S

Table 1.

Parameter Symbol Min Typ Max Unit Conditions

CLOCK INPUTS Differential input

Input Frequency 0 1200 MHz Input Sensitivity, Differential 150 mV p-p

Input Level 1.8 V p-p

Input Common-Mode Voltage VCM V Input Common-Mode Range V

0.4 VS − 0.4 V

CMR

/2 − 0.1 VS/2 + 0.05 V Inputs are self-biased; enables ac coupling

S

Input Voltage Offset 30 mV Input Sensitivity, Single-Ended 150 mV p-p

Input Resistance (Differential) 7 kΩ Input Capacitance CIN 2 pF Input Bias Current (Each Pin) −350 +350 µA Full input swing

LVDS CLOCK OUTPUTS

Output Frequency 1200 MHz See Figure 9 for a swing vs. frequency plot Differential Output Voltage VOD 247 344 454 mV ∆VOD 50 mV Offset Voltage VOS 1.125 1.25 1.375 V ∆VOS 50 mV Short-Circuit Current ISA, ISB 3 6 mA Each pin (output shorted to GND )

CMOS CLOCK OUTPUTS

Output Frequency 250 MHz

Output Voltage High VOH V V

− 0.1 V At 1 mA load

S

− 0.35 V At 10 mA load

S

Output Voltage Low VOL 0.1 V At 1 mA load

0.35 V At 10 mA load Reference Voltage V

REF

Output Voltage VS/2 − 0.1 VS/2 VS/2 + 0.1 V ±500 µA Output Resistance 60 Ω Output Current 500 µA

Jitter performance is improved with higher slew rates (greater voltage swing)

Larger voltage swings can turn on the protection diodes and can degrade jitter performance

Inputs are dc-coupled with 200 mV p-p signal applied

CLK ac-coupled; CLK

Termination = 100 Ω; differential (OUTx, OUTx

ac-bypassed to ground

)

Single-ended; termination = open OUTx and OUTx

in phase

With 10 pF load each output; see Figure 16 for swing vs. frequency

Rev. B | Page 3 of 16

ADCLK846

TIMING CHARACTERISTICS

Table 2.

Parameter Symbol Min Typ Max Unit Conditions

LVDS OUTPUTS Termination = 100 Ω differential; 3.5 mA

Output Rise/Fall Time tR, tF 135 235 ps 20% to 80% measured differentially Propagation Delay, CLK-to-LVDS Output tPD 1.5 2.0 2.7 ns V

Temperature Coefficient 2.0 ps/°C

Output Skew1

All LVDS Outputs on the Same Part 65 ps All LVDS Outputs Across Multiple Parts 390 ps

Additive Time Jitter

Integrated Random Jitter 54 fs rms BW = 12 kHz to 20 MHz, CLK = 1000 MHz 74 fs rms BW = 50 kHz to 80 MHz, CLK = 1000 MHz 86 fs rms BW = 10 Hz to 100 MHz, CLK = 1000 MHz Broadband Random Jitter2 150 fs rms Input slew rate = 1 V/ns Crosstalk-Induced Jitter 260 fs rms

CMOS OUTPUTS Termination = open

Output Rise/Fall Time tR, tF 525 950 ps 20% to 80%; CMOS load = 10 pF Propagation Delay, CLK-to-CMOS Output tPD 2.5 3.2 4.2 ns 10 pF load

Temperature Coefficient 2.2 ps/°C

Output Skew2

All CMOS Outputs on the Same Part 175 ps All CMOS Outputs Across Multiple Parts 640 ps

Additive Time Jitter

Integrated Random Jitter 56 fs rms BW = 12 kHz to 20 MHz, CLK = 200 MHz Broadband Random Jitter3 100 fs rms Input slew = 2 V/ns; see Figure 11 Crosstalk-Induced Jitter 260 fs rms

LVDS-TO-CMOS OUTPUT SKEW2

LVDS Output(s) and CMOS Output(s)

0.8 1.6 ns CMOS load = 10 pF and LVDS load = 100 Ω

on the Same Part

1

This is the difference between any two similar delay paths while operating at the same voltage and temperature.

2

Measured at rising edge of clock signal.

3

Calculated from SNR of ADC method.

= V

ICM

, VID = 0.5 V

REF

Calculated from spur energy with an interferer 10 MHz offset from carrier

Rev. B | Page 4 of 16

ADCLK846

CLOCK CHARACTERISTICS

Table 3. Clock Output Phase Noise

Parameter Min Typ Max Unit Conditions

CLK-TO-LVDS ABSOLUTE PHASE NOISE Input slew rate > 1 V/ns

1000 MHz −90 dBc/Hz At 10 Hz offset

−108 dBc/Hz At 100 Hz offset

−117 dBc/Hz At 1 kHz offset

−126 dBc/Hz At 10 kHz offset

−134 dBc/Hz At 100 kHz offset

−141 dBc/Hz At 1 MHz offset

−146 dBc/Hz At 10 MHz offset

CLK-TO-CMOS ABSOLUTE PHASE NOISE Input slew rate > 1 V/ns

200 MHz −100 dBc/Hz At 10 Hz offset

−117 dBc/Hz At 100 Hz offset

−128 dBc/Hz At 1 kHz offset

−138 dBc/Hz At 10 kHz offset

−147 dBc/Hz At 100 kHz offset

−153 dBc/Hz At 1 MHz offset

−156 dBc/Hz At 10 MHz offset

LOGIC AND POWER CHARACTERISTICS

Table 4. Control Pin Characteristics

Parameter Symbol Min Typ Max Unit Conditions

CONTROL PINS

(CTRL_A, CTRL_B, SLEEP)

1

Logic 1 Voltage VIH V Logic 0 Voltage VIL 0.4 V Logic 1 Current IIH 5 8 20 A Logic 0 Current IIL −5 +5 A Capacitance 2 pF

POWER

Supply Voltage Requirement VS 1.71 1.8 1.89 V VS = 1.8 V ± 5% LVDS Outputs, Full Operation

LVDS at 100 MHz 55 70 mA All outputs enabled as LVDS and loaded, RL = 100 Ω LVDS at 1200 MHz 110 130 mA All outputs enabled as LVDS and loaded, RL = 100 Ω

CMOS Outputs, Full Operation

CMOS at 100 MHz 75 95 mA

CMOS at 250 MHz 155 190 mA

Sleep 3 mA

Power Supply Rejection2

LVDS PSR CMOS PSR

1

These pins each have a 200 kΩ internal pull-down resistor.

2

Change in T

per change in VS.

PD

− 0.4 V

S

All outputs enabled as CMOS and loaded, CMOS load = 10 pF

SLEEP pin pulled high; does not include power dissipated in external resistors

0.9 ps/mV

TPD

1.2 ps/mV

TPD

Rev. B | Page 5 of 16

ANALOG DEVICES ADCLK846 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

TIMING CHARACTERISTICS

CLOCK CHARACTERISTICS

LOGIC AND POWER CHARACTERISTICS