Datasheet ADC912AFS, ADC912AFP Datasheet (Analog Devices)

CMOS Microprocessor-Compatible

a

FEATURES
Low Cost
Low Transition Noise between Code
12-Bit Accurate

ⴞ1/2 LSB Nonlinearity Error over Temperature

No Missing Codes at All Temperatures
10 ␮s Conversion Time
Internal or External Clock
8- or 16-Bit Data Bus Compatible
Improved ESD Resistant Design
Latchup Resistant Epi-CMOS Processing
Low 95 mW Power Consumption
Space-Saving 24-Lead 0.3" DIP, or 24-Lead SOIC

APPLICATIONS
Data Acquisition Systems
DSP System Front End
Process Control Systems
Portable Instrumentation

GENERAL DESCRIPTION

The ADC912A is a monolithic 12-bit accurate CMOS A/D
converter. It contains a complete successive-approximation A/D
converter built with a high-accuracy D/A converter, a precision
bipolar transistor high-speed comparator, and successive­approximation logic including three-state bus interface for logic
compatibility. The accuracy of the ADC912A results from the
addition of precision bipolar transistors to Analog Devices’
advanced-oxide isolated silicon-gate CMOS process. Particular
attention was paid to the reduction of transition noise between
adjacent codes achieving a 1/6 LSB uncertainty. The low noise
design produces the same digital output for dc analog inputs

12-Bit A/D Converter

ADC912A

FUNCTIONAL BLOCK DIAGRAM

V

AGND

REFIN

12-BIT DAC

ADC912A

MULTIPLEXER

THREE-STATE

OUTPUT

DRIVERS

D

D

11

12-BIT LATCH

8

SUCCESSIVE

APPROXIMATION

REGISTER

48

8

THREE-STATE

OUTPUT

DRIVERS

D

D4DGND D

7

3/11D0/8

not located at a transition voltage, see Figures 1 and 2. NPN
digital output transistors provide excellent bus interface timing,
125 ns access and bus disconnect time which results in faster
data transfer without the need for wait states. An external

1.25 MHz clock provides a 10 µs conversion time.

In stand-alone applications an internal clock can be used with
external crystal.

An external negative five-volt reference sets the 0 V to 10 V
input range. Plus 5 V and minus 12 V power supplies result in
95 mW of total power consumption.

A

IN

5k⍀

CONTROL

LOGIC

CLOCK

OSCILLATOR

V

DD

V

SS

BUSY

CS

RD

HBEN

CLK OUT

CLK IN

256

256 SUCCESSIVE

CONVERSIONS

192

128

64

NUMBER OF OCCURRENCES

0

2045 2049204820472046

OUTPUT CODE – Decimal

= 4.99756V

A

IN

WITH

Figure 1. Code Repetition

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

100

90

DIGITAL OUTPUT

10

0%

TRANSITION NOISE

ANALOG INPUT

Figure 2. Transition Noise Cross Plot

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

ADC912A–SPECIFICATIONS

10 V; External f

= 1.25 MHz; –40ⴗC to +85ⴗC applies to ADC912A/F unless otherwise noted.)

CLK

(VDD = +5 V ⴞ 5%, VSS = –11.4 V to –15.75 V, V

= –5 V, Analog Input O V to

REFIN

Parameter Symbol Conditions Min Typ Max Unit

STATIC ACCURACY

Integral Nonlinearity INL –1 +1 LSB
Differential Nonlinearity DNL –1 +1 LSB
Offset Error V
Gain Error G
Full-Scale Tempco

1

ZSE

FSE

TCG

FS

VDD = +5 V, VSS = –12 V –5 +5 LSB
VDD = +5 V, VSS = –12 V –6 +6 LSB

5 15 ppm/°C

ANALOG INPUT

Input Voltage Range V
Input Current Range I

IN

IN

POWER SUPPLIES

Positive Supply Current I
Negative Supply Current I
Power Consumption P

DD

SS

DISS

Power Supply Rejection Ratio PSRR+ ∆V

VDD = +5 V
VSS = –12 V
VDD = +5 V2, VSS = –12 V

DD

2

2

2

= ± 5%, AIN = 10 V 1/2 4 LSB

010V
03mA

57mA
35mA
70 95 mW

PSRR– ∆VSS = ± 5%, AIN = 10 V 1/2 4 LSB

DIGITAL INPUTS

Logic Input High Voltage V
Logic Input Low Voltage V
Logic Input Current I
Digital Input Capacitance C

INH

INL

IN

IN

CS, RD, HBEN 2.4 V
CS, RD, HBEN 0.8 V
CS, RD, HBEN ± 1 µA

Digital Inputs, CS, RD, HBEN, CLKIN 7 10 pF

DIGITAL OUTPUTS

Logic Input High Voltage V
Logic Input Low Voltage V
Three-State Output Leakage I
Digital Input Capacitance C

OH

OL

OZ

OUT

DYNAMIC PERFORMANCE

Conversion Time TC f

I

= 0.2 mA 4 V

SOURCE

I

= 1.6 mA 0.4 V

SINK

D11–D

0/8

D11–D

CLK

1

0/8

= 1.25 MHz

815pF

3

10 µA

Synchronous Clock 10.4 µs
Asynchronous Clock 10.4 11.2 µs

NOTES

1

Guaranteed by design.

2

Converter inactive; CS, RD = High, AIN = 10 V.

3

See Synchronizing Start Conversion information in Converter Operation Details. Typicals (typ) are median values measured at 25 °C. See Typical Performance
Characteristics for additional information.

Specifications subject to change without notice.

5V

OH

TO V

3k⍀

C

L

DGND

OL

OL

(t3)

(t6)

DBN

A. HIGH-Z TO V

AND V

3k⍀

DGND

OL

TO V

OH

OH

C

(t3)

L

(t6)

DBN

B. HIGH-Z TO V

AND V

Figure 3. Load Circuits for Access Time

–2–

5V

TO HIGH-Z

OL

3k⍀

10pF

DGND

DBN

A. V

3k⍀

DGND

TO HIGH-Z

OH

10pF

DBN

B. V

Figure 4. Load Circuits for Output Float Delay

REV. B

ADC912A

CS

RD

BUSY

DATA

t

1

t

2

t

3

t

7

t

3

t

7

t

CONV

t

5

t

1

t

2

t

CONV

t

5

t

4

NEW DATA
DB

11

– DB0

OLD DATA

DB

11

– DB

0

DATA

OUTPUTS

D

11D10D9D8D7D6D5D4D3/11D2/10D1/9D0/8

DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB

0

FIRST READ

(OLD DATA)

SECOND

READ

DB

11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0

t

4

DATA

OUTPUTS

D

7D6D5D4D3/11D2/10D1/9D0/8

FIRST READ

(OLD DATA)

DB

7DB6DB5

DB4DB3DB2DB1DB

0

SECOND READ

LOW

LOW LOW

LOW

DB

11

DB10DB

9DB8

THIRD READ

DB

7DB6DB5

DB4DB3DB2DB1DB

0

t

8

t

1

t

2

t

3

t

7

t

4

t

9

t

5

t

8

t

1

t

3

t

4

t

9

t

10

t

3

t

7

t

2

t

4

t

1

t

5

t

8

t

9

t

7

t

5

CS

RD

BUSY

DATA

HBEN

NEW DATA
DB

7

– DB0

NEW DATA

DB

11

– DB8

OLD DATA
DB

7

– DB0

t

CONV

1, 2

TIMING CHARACTERISTICS

External f

= 1.25 MHz; –40ⴗC to +85ⴗC applies to ADC912A/F unless otherwise noted. See Figures 5 to 8.)

CLK

(VDD = +5 V ⴞ 5%, VSS = –11.4 V to –15.75 V, V

Parameter Symbol Conditions Min Typ Max Unit

CS to RD Setup Time t
RD to BUSY Propagation Delay t

Data Access Time after READ t
Read Pulsewidth t
CS to RD Hold Time t
New Data Valid after BUSY t
Bus Disconnect Time t
HBEN to RD Setup Time t
HBEN to RD Hold Time t
Delay between Successive Read Operations t

NOTES

1

Guaranteed by design.

2

All input control signals are specified with tR = tF = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

3

t3, t4, and t6 are measured with the load circuits of Figure 3 and timed for and output to cross 0.8 V or 2.4 V.

4

t7 is the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 4.

Specifications subject to change without notice.

1

2

3

3

3

4

5

3

6

7

8

9

10

CL = 100 pF 65 125 ns

CL = 100 pF –30 0 ns

TIMING DIAGRAMS

CS

t

1

0

RD

BUSY

DATA

OUTPUTS

t

1

t

2

t

CONV

t

3

OLD DATA

DB

DATA

D

11D10D9D8D7D6D5D4D3/11D2/10D1/9D0/8

DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB

READ

t

6

– DB

11

0

NEW DATA

DB

– DB

11

t

5

t

10

t

7

0

= –5 V, Analog Input 0 V to 10 V;

REFIN

0ns

150 ns

90 ns
0ns

20 60 90 ns
20 ns
20 ns
350 250 ns

Figure 5. Parallel Read Timing Diagram, Slow-Memory
Mode (HBEN = LOW)

HBEN

t

t

10

11

8

t

1

DB10DB

t

3

NEW DATA
DB

t

8

CS

t

1

DATA

OUTPUTS

t

2

t

3

t

CONV

OLD DATA

– DB0

DB

7

LOW LOW

D

7D6D5D4D3/11D2/10D1/9D0/8

DB7DB6DB5DB4DB3DB2DB1DB

LOW

RD

BUSY

DATA

FIRST READ

SECOND READ

Figure 6. Two-Byte Read Timing Diagram, Slow-Memory
Mode

REV. B

t

6

NEW DATA
DB7 – DB0

LOW

t

9

t

5

t

7

DB

t

4

– DB8

11

9DB8

Figure 7. Parallel Read Timing Diagram, ROM Mode
(HBEN = LOW)

t

9

t

5

t

7

0

Figure 8. Two-Byte Read Timing Diagram, ROM Mode

–3–

ADC912A

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted)

VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V

V

SS

V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to V

REFIN

DD

AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V

A

IN

Digital Input Voltage to DGND,

Pins 17, 19–21 . . . . . . . . . . . . . . . . . –0.3 V to V

+ 0.3 V

DD

Operating Temperature Range

Extended Industrial: ADC912A/F . . . . . . . –40°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

Maximum Junction Temperature (TJ max) . . . . . . . . . . 150°C

Package Power Dissipation . . . . . . . . . . . . . . (T

Thermal Resistance θ

JA

max–TA)/θ

J

Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W

SOIC-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C

Digital Output Voltage to DGND,

Pins 4–11, 13–16, 18, 22 . . . . . . . . . –0.3 V to V

+ 0.3 V

DD

ORDERING GUIDE

Temperature INL Package

Model Range (LSB) Package Description Option

ADC912AFP –40°C to +85°C ±1 24-Lead Narrow-Body Plastic N-24
ADC912AFS –40°C to +85°C ± 1 24-Lead Wide-Body SOIC R-24

Table I. Analog Input to Digital Output Code Conversion

Analog Input Voltage Output Code*
0 V to 10 V –10 V to +10 V DB11 (MSB) DB0 (LSB)

+FS – 1 LSB 9.9976 9.99951 1111 1111 1111
+FS – 1 1/2 LSB 9.9964 9.9927 1111 1111 1111φ

Midscale + 1/2 LSB 5.0012 0.0024 1000 0000 000φ
Midscale 5.0000 0.0000 1000 0000 0000

–FS + 1/2 LSB 0.0012 –9.9976 0000 0000 000φ
–FS 0.0000 –10.000 0000 0000 0000

*The symbol”φ” indicates a 0 or 1 with equal probability.

JA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADC912A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–4–

REV. B

ADC912A

WAFER TEST LIMITS

(@ VDD = +5 V, VSS = –12 V or –15 V, V

= –5 V, AIN = 0 V to 10 V, and TA = 25ⴗC, unless otherwise noted.)

REF

ADC912AG

Parameter Symbol Conditions Limit Unit

Integral Nonlinearity INL ± 1 LSB max
Differential Nonlinearity DNL ± 1 LSB max
Offset Error V
Gain Error G
Analog Input Resistance R
Logic Input High Voltage V
Logic Input Low Voltage V
Logic Input Current I
Logic Output High Voltage V
Logic Output Low Voltage V
Positive Supply Current I
Negative Supply Current I

ZSE

FSE

AIN

INH

INL

IN

OH

OL

DD

SS

NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

R = 10⍀
C1 = 0.01␮F
C2 = 4.7␮F
NC = NO CONNECT

POWER SUPPLY SEQUENCE:
+5V, –15V, –5V, +10V

Guaranteed by Design ± 8 LSB max

± 8 LSB max
4/6 kΩ min/max

CS, RD, HBEN 2.4 V min
CS, RD, HBEN 0.8 V max
CS, RD, HBEN ± 1 µA max

I

= 0.2 mA 4 V min

SOURCE

I

= 1.6 mA 0.4 V max

SINK

VDD = +5 V, CS = RD = VDD, AIN = +10 V 7 mA max
VSS = –12 V, CS = RD = VDD, AIN = +10 V 5 mA max

10V

–5V

R

+

C1

C1

C2

1

R

2

C2

3

+

4

5

ADC912A

TOP VIEW

6

(Not to Scale)

7

NC

8

9

10

11

12

R

C1

24

R

23

C1

22

NC

21

R

20

R

19

18

NC

R

17

16

NC

15

NC

14

NC

13

NC

+5V

+

C2

–15V

C2

+

REV. B

Figure 9. Burn-In Circuit

–5–

ADC912A

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

l AIN Analog Input. 0 V to 10 V.
2 VREFIN Voltage Reference Input. Requires external –5 V reference.

3 AGND Analog Ground.

4...11 D

13...16 D

1

2 DGND Digital Ground.

...D

11

3/11

... D

17 CLK IN Clock Input Pin. An external TTL-compatible clock may be applied to this pin. Alternatively a crystal or

18 CLK OUT Clock Output Pin. An inverted CLK IN signal appears at CLK OUT when an external clock is used. See

19 HBEN High Byte Enable Input. Its primary function is to multiplex the 12 bits of conversion data onto the lower

20 RD READ Input. This active LOW signal, in conjunction with CS, is used to enable the output data three

21 CS Chip Select Input. This active LOW signal, in conjunction with RD, is used to enable the output data

22 BUSY BUSY output indicates converter status. BUSY is LOW during conversion.

23 V
24 V

SS

DD

Three-state data outputs become active when CS and RD are brought low.

4

Individual pin function is dependent upon High Byte Enable (HBEN) input.

0/8

DATA BUS OUTPUT, CS and RD = LOW

Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16

Mnemonic* D

D

D

D

D

D

D

D

11

10

9

8

7

6

5

D

4

3/11D2/10D1/9D0/8

HBEN = LOW DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB

HBEN = HIGH DB11DB10DB9DB8Low Low Low Low DB11DB10DB9DB

*D11 . . . D

DB

are the ADC data output pins.

0/8

. . . DB0 are the 12-bit conversion results. DB11 is the MSB.

11

ceramic resonator may be connected between CLK IN (Pin 17) and CLK OUT (Pin 18).

CLK IN (Pin 17) description for crystal (resonator).

D

. . . D

7

outputs (4 MSBs or 8 LSBs). See pin description 4 . . . 11 and 13 . . . 16. Also disables

0/8

conversion start when HBEN is high.

state drivers and initiates a conversion if CS and HBEN are low.

three-state drivers and initiates a conversion if RD and HBEN are low.

Negative Supply, –12 V or –15 V.
Positive Supply, +5 V.

0

8

PIN CONFIGURATION

V

REFIN

AGND

DGND

A

IN

D

11

D

10

D

D

D

D

D

D

1

2

3

4

5

9

6

7

8

7

8

9

6

5

10

11

4

12

ADC912A

TOP VIEW

(Not to Scale)

24

23

22

21

20

19

18

17

16

15

14

13

V

V

BUSY

CS

RD

HBEN

CLK OUT

CLK IN

D

D

D

D

DD

SS

0/8

1/9

2/10

3/11

–6–

0V TO 10V

ANALOG INPUT

–5V

REFERENCE

C1

SOURCE

XTAL = 1MHz, C1 = 0.1 ␮F, C3 = 10 ␮F
C3, C4

= 30pF TO 100pF DEPENDING ON XTAL CHOSEN

A

1

IN

V

2

REFIN

C2

+

3

AGND

D

4

11

ADC912A

D

5

10

D

6

9

D

7

8

D

8

7

9

D

6

D

10

5

11

D

4

12

DGND

8-BIT OR 16-BIT ␮P DATA BUS

BUSY

HBEN

CLK OUT

CLK IN

Figure 10. Basic Connection Diagram

V

24

23

22

21

20

19

18

17

16

15

14

13

+5V

–12V TO –15V
STATUS

OUTPUT

␮P
CONTROL
INPUTS

C3

XTAL

C4

DD

V

SS

CS

RD

D

0/8

D

1/9

D

2/10

D

3/11

REV. B

Typical Performance Characteristics–ADC912A

0.4

0.2

0

–0.2

INL–NONLINEARITY ERROR – LSB

–0.4

0

DIGITAL OUTPUT CODE

20481024 3072

4096

TPC 1. Nonlinearity Error vs. Digital
Output Code

6

V

5

4

3

CS, RD = LOGIC HIGH

2

A

IN

1

CLK = 1MHz XTAL

0

–1

SUPPLY CURRENT – mA

–2

–3

–4

–50

–75

= 10V

ISS @ VSS = –15.75V

0

TEMPERATURE – C

@ 5.25V

DD

125

10025 50–25

75

5

4

3

2

1

0

–1

–2

OFFSET ERROR – LSB

–3

–4

–5

–50

–75

TEMPERATURE – C

125

10025 50–25 0 75

TPC 2. Offset Error vs. Temperature

80

P

= IDD ⴛ 5 + ISS ⴛ 12

DISS

C

= 20pF

OUT

f

= 1/13 f

– mW

DISS

P

60

40

0

1k

CONV

TA = 25 C

EXT CLK IN

CLK IN

10k

CLK IN FREQUENCY – Hz

100k

1M

6

5

4

3

2

1

0

–1

GAIN ERROR – LSB

–2

–3

–4

–50

–75

0

TEMPERATURE – C

125

10025 50–25

75

TPC 3. Gain Error vs. Temperature

50

40

30

I

SINK

0

I

SOURCE

0

1

VO OUTPUT VOLTAGE – Volts

DIGITAL OUTPUT CURRENT – mA

20

10

–10

–20

–30

–40

–50

5432

TPC 4. Supply Current vs.
Temperature

256

256 SUCCESSIVE

192

128

64

NUMBER OF OCCURRENCES

0

2045 2049204820472046

OUTPUT CODE – Decimal

CONVERSIONS

A

IN

TPC 7. Code Repetition

WITH

= 4.99756V

TPC 5. Power Dissipation vs. CLK IN
Frequency

100

90

DIGITAL OUTPUT

10

0%

TRANSITION NOISE

ANALOG INPUT

TPC 8. Transition Noise Cross Plot

TPC 6. Digital Output Current vs.
Output Voltage

VDD = +5V

4

V

= –12V

SS

T

= 25ⴗC

A

2

0

–2

LINEARITY ERROR – LSB

–4

20

15

CONVERSION TIME – ␮s

10

5

0

TPC 9. Linearity Error vs. Conversion
Time

REV. B

–7–

ADC912A

CIRCUIT CHARACTERISTICS

The characteristic curves provide more complete static and
dynamic accuracy information necessary for repetitive sampling
applications often used in DSP processing. One of the impor­tant characteristic curves provided displays integral nonlinearity
error (INL) versus output code with a typical value of ±1/4 LSB.
Another very important characteristic associated with INL is the
transition noise shown in the transition noise cross plot. The
ADC912A offers extremely small, ±1/6 LSB, transition noise
which maintains the system signal-to-noise ratio in DSP processing
applications. Code repetition plots show the precision internal
comparator of the ADC912A making the same decision every
time for dc input voltages. Code repetition along with no miss­ing codes assures proper performance when the ADC912A is
used in servo-control systems.

CONVERTER OPERATION DETAILS

The CS, RD, and HBEN digital inputs control the start of
conversion. A high-to-low on both CS and RD initiate a conver­sion sequence. The HBEN high-byte-enable input must be low
or coincident with the read RD input edge. The start of conver­sion resets the internal successive approximation register (SAR)
and enables the three-state outputs. See Figure 11. The busy
line is active low during the conversion process.

0V TO 10V

A

IN

V

REFIN

AGND

5k⍀

2.5k⍀

–

0 TO

+

–V

REF

12

COMPARATOR

SAR

12-BIT LATCH

Figure 11. Simplified Analog Input Circuitry of ADC912A

During conversion, the SAR sequences the internal voltage
output DAC from the most significant bit (MSB) to the least
significant bit (LSB). The analog input connects to the
comparator via a 5 kΩ resistor. The DAC, which has a 2.5 kΩ
output resistance, connects to the same comparator input.
The comparator, performing a zero crossing detection, tests the
addition of successively weighted bits from the DAC output
versus the analog input signal. The MSB decision occurs 200 ns
after the second positive edge of the CLK IN following conver­sion initiation. The remaining 11-bit trials occur after the next
11 positive CLK IN edges. Once a conversion cycle is started it
cannot be stopped or restarted, without upsetting the remaining
bit decisions. Every conversion cycle must have 13 negative and
positive CLK IN edges. At the end of conversion the compara­tor input voltage is zero. The SAR contains the 12-bit data
word representing the analog input voltage. The BUSY line
returns to logic high, signaling end of conversion. The SAR
transfers the new data to the 12-bit latch.

SYNCHRONIZING START CONVERSION

Aligning the negative edge of RD with the rising edge of CLK
IN provides synchronization of the internal start conversion
signal to other system devices for sampling applications.

When the negative edge of RD is aligned with the positive edge
of CLK IN, the conversion will take 10.4 microseconds. The
minimum setup time between the negative edge of CLK IN and
the negative edge of RD is 180 ns. Without synchronization the
conversion time will vary from 12.5 to 13.5 clock cycles. See
Figure 12.

RD

CS

,

BUSY

180ns MIN

CLK IN

DB

11

(MSB)

BIT DECISION

MADE

DB10DB

9

DB

0

Figure 12. External Clock Input Synchronization

POWER ON INITIALIZATION

During system power-up the ADC912A comes up in a random
state. Once the clock is operating or an external clock is applied,
the first valid conversion begins with the application of a high­to-low transition on both CS and RD. The next 13 negative
clock edges complete the first conversion, producing valid data
at the digital outputs. This is important in battery-operated
systems where power supplies are shut down between measure­ment times.

DRIVING THE ANALOG INPUT

During conversion, the internal DAC output current modulates
the analog input current at the CLK IN frequency of 1.25 MHz.
The analog input to the ADC912A must not change during the
conversion process. This requires an external buffer with low
output impedance at 1.25 MHz. Suitable devices meeting this
requirement include the OP27, OP42, and the SMP-11.

CLK

ADC912A

OUT

C1

*

INTERNAL

C2

CLK

IN

*CRYSTAL OR CERAMIC RESONATOR

1M⍀

CLOCK

Figure 13. ADC912A Simplified Internal Clock Circuit

–8–

REV. B

ADC912A

INTERNAL CLOCK OSCILLATOR

Figure 13 shows the ADC912A internal clock circuit. The clock
oscillates at the external crystal or ceramic resonator frequency.
The 1.25 MHz crystal or ceramic resonator connects between
the CLK IN (Pin 17) and the CLK OUT (Pin 18). Capacitance
values (C1, C2) depend on the crystal or ceramic resonator
manufacturer. The crystal vendors should be qualified due to
variations in C1 and C2 values required from vendor to vendor.
Typical values range from 30 pF to 100 pF.

EXTERNAL CLOCK INPUT

A TTL compatible signal connected to CLK IN provides proper
converter clock operation. No connection is necessary to the
CLK OUT pin. The duty cycle of the external clock input can
vary from 45% to 55%. Figure 12 shows the important waveforms.

EXTERNAL REFERENCE

A low output resistance, negative five volt reference is necessary.
The external reference should be able to supply 3 mA of refer­ence current. A bypass capacitor is necessary on the reference
input lead to minimize system noise as the internal DAC switches.
The reference input to the internal DAC is code dependent requir­ing anywhere from zero to 3 mA. The reference voltage tolerance
has a direct influence on A/D converter full-scale voltage, and
the maximum input full-scale voltage equals 2 × –V

REF

. The
ADC912A is designed for ratiometric operation, but operation
using reference voltages between –5.00 V and 0 V will result in
degraded linearity performance. Integral linearity is fully tested and
guaranteed for references of –5 V. Figure 14 provides a good
–5 V reference that does not require precision resistors.

+5V TO +15V

100⍀

10k⍀

0.01␮F

2

V+

OP77

OP77

3

V–

–12V TO –15V

2

INPUT

6

V

OUT

REF02

5

TRIM

GND

4

TRIM IS OPTIONAL, ONLY NECESSARY
FOR ABSOLUTE ACCURACY CIRCUITS

100⍀

+

10␮F//0.01␮F

–5V
OUTPUT

Figure 14. –5 V Reference

UNIPOLAR ANALOG INPUT OPERATION

Figure 15 shows the ideal input/output characteristic for the 0 V
to 10 V input range of the ADC912A. The designed output
code transitions occur midway between successive integer LSB
values (i.e., 0.5 LSB, 1.5 LSBs, 2.5 LSBs . . . FS – 1.5 LSBs).
The output code is natural binary with 1 LSB = FS/4096 =
(10/4096) V = 2.44 mV. The maximum full-scale input voltage
is (10 × 4095/4096) V = 9.9976 V.

4095

4094

FULL-SCALE
TRANSITION

2

Decimal Equivalent

1

DIGITAL OUTPUT CODE –

2

1

0

0.5

AIN – ANALOG INPUT IN LSB

AT FS – 1.5 LSB

FS

FS-1FS-2

Figure 15. Ideal ADC912A Input/Output Transfer
Characteristic

OFFSET AND FULL-SCALE ERROR ADJUSTMENT, UNIPOLAR OPERATION

For applications where absolute accuracy is important, offset
and full-scale errors can be adjusted to zero. Figure 16 shows
the extra components required for full-scale error adjustment.
Zero offset is achieved by adjusting the null offset of the op amp
driving A

.

IN

+12V

3

2

4

–12V

A1

10k⍀

1

7

ZERO
ADJUST

10⍀

6

5

FULL
SCALE
ADJUST

200⍀

20k⍀

V

IN

0V TO 10V

A1: OP27 – LOWEST NOISE (TRIMMER CONNECTS
BETWEEN PINS 1 & 8, WIPER TO 12V)
OP42 – BEST BANDWIDTH

*EXTRA PINS OMITTED FOR CLARITY

1

A

IN

ADC912A*

3

AGND

Figure 16. Unipolar 0 V to 10 V Operation

Adjust the zero scale first by applying 1.22 mV (equivalent to

0.5 LSB input) to V

. Adjust the op amp offset control until

IN

the digital output toggles between 0000 0000 0000 and 0000
0000 0001. The next step is adjustment of full scale. Apply

9.9963 V (equivalent to FS – 1.5 LSB) to V

and adjust R1

IN

until the digital output toggles between 1111 1111 1110 and
1111 1111 1111.

REV. B

–9–

ADC912A

BIPOLAR ANALOG INPUT OPERATION

Bipolar analog input operation is achieved with an external
amplifier providing an analog offset. Figures 17 and 18 show
two circuit topologies that result in different digital-output cod­ing. In Figure 17, offset binary coding is produced when the
external amplifier is connected in the inverting mode. Figure 19
shows the ideal transfer characteristics for both the inverting
and noninverting configurations given in Figures 17 and 18.

ⴞV

R3

IN

R

FS

R4

R1 = R2 = 20k⍀
SEE TABLE II FOR VALUES OF R3, R4, R

A1: OP27 LOWEST NOISE, OP42 BEST BANDWIDTH
*EXTRA PINS OMITTED FOR CLARITY

A1

–5V

0.1␮F

R2

R

R1

10␮F

1

Z

2

3

A

IN

ADC912A*

V

REFIN

AGND

, AND R

Z

FS

Figure 17. Noninverting Bipolar Analog Input Operation

The scaling resistors chosen in bipolar input applications should
be from the same manufacturer to obtain good resistor tracking
performance over temperature. When potentiometers are used
for absolute adjustment, 0.1% tolerance resistors should still be
used as shown in Figures 17 and 18 to minimize temperature
coefficient errors.

R2

R

FS

–5V

R1

A1

R

Z

R3

0.1␮F
+

10␮F

1

A

IN

ADC912A*

2

V

REFIN

3

AGND

FS

ⴞV

IN

SEE TABLE III FOR VALUES OF R1, R2, R3, R4, RZ, AND R
A1: OP27 LOWEST NOISE, OP42 BEST BANDWIDTH

*EXTRA PINS OMITTED FOR CLARITY

Figure 18. Inverting Bipolar Analog Input

Calibration of the bipolar analog input circuits (Figures 17 and

18) should begin with zero adjustment first. Apply a +1/2 LSB
analog input to A

, (see Tables II and III) and adjust RZ until the

IN

successive digital output codes flicker between the following codes:

For noninverting, Figure 17 1000 0000 0000

1000 0000 0001

For inverting, Figure 18 0111 1111 1111

0111 1111 1110

Next, adjust full scale by applying a FS–3/2 LSB analog input to
A

, (see Tables II and III) and adjust RFS until the successive

IN

digital output codes flicker between the following codes:

For Noninverting, Figure 17 1111 1111 1110

1111 1111 1111

For Inverting, Figure 18 0000 0000 0001

0000 0000 0000

Table II. Resistor and Potentiometer Values Required for
Figure 17

V

Range R3 R4 RZRFS1/2 LSB FS/2–3/2 LSB

IN

Vk⍀ k⍀ k⍀ k⍀ mV V

± 2.5 0 40.2 0.5 0.5 0.61 2.49817
± 5.0 20.0 19.8 0.5 1.0 1.22 4.99634
± 10.0 29.8 10.0 0.5 0.5 2.44 9.99268

Table III. Resistor and Potentiometer Values Required for
Figure 18

VIN Range R1 R2 R3 RZRFS1/2 LSB FS/2–3/2 LSB
Vk⍀ k⍀ k⍀ k⍀ k⍀ mV V

± 2.5 20.0 41.2 40.2 2 1 0.61 2.49817
± 5.0 20.0 20.5 20.0 1 1 1.22 4.99634
± 10.0 20.0 10.5 10.2 0.5 1 2.44 9.99268

DIGITAL OUTPUT

111...111

111...110

100...001

100...000

011...111

011...110

INVERTING
FIGURE 18

NON­INVERTING
FIGURE 17

FS

+

2

– 1LSB

000...001

000...000

–

2

0VFS

VIN – Input Voltage

+

Figure 19. Ideal Input/Output Transfer Characteristics for
Bipolar Input Circuits

–10–

FS

2

REV. B

ADC912A

MICROPROCESSOR INTERFACING

The ADC912A has self-contained logic for both 8-bit and 16-bit
data bus interfacing. The output data can be formatted into
either a 12-bit parallel word for a 16-bit data bus or an 8-bit
data word pair for an 8-bit data bus. Data is always right justi­fied, i.e., LSB is the most right-hand bit in a 16-bit word. For a
two-byte read, only data outputs D

7

. . . D

are used. Byte

0/8

selection is governed by the HBEN input which controls an
internal digital multiplexer. This multiplexes the 12 bits of
conversion data onto the lower D

7

. . . D

outputs (4 MSBs or

0/8

8 LSBs) where it can be read in two read cycles. The 4 MSBs
always appear on D

. . . D8 whenever the three-state output

11

drivers are turned on. See Figure 20.

Two A/D conversion modes of operation are available for both
data bus sizes: the ROM mode and the Slow-Memory mode.

ADC912A

HBEN

CS

RD

"1"

DQ

BUSY

ACTIVE HIGH

(HBEN = "0")

ACTIVE HIGH

(HBEN = "1")

CONVERSION START
(POSITIVE EDGE
TRIGGER)

CLR

ENABLE THREE-STATE
OUTPUTS
PINS: D11 ... D

DATA BITS: DB11 ... DB

ENABLE THREE-STATE
OUTPUTS
PINS: D

DATA BITS: DB11 ... DB

PINS: D7 ... D
DATA BITS: LOGIC LOW
PINS: D
DATA BITS: DB11 ... DB

11

3/11

... D

... D

0/8

0

8

8

4

0/8

8

Figure 20. Internal Logic for Control Inputs CS, RD, and
HBEN

In the ROM mode each READ instruction obtains new, valid
data, assuming the minimum timing requirements are satisfied.
However, since the data output from a current READ instruc­tion was generated from a conversion initiated by a previous
READ operation, the current data may be out-of-date. To be
sure of obtaining up-to-date data, READ instructions may be
coded in pairs (with some NOPs between them); use only the
data from the second READ in each pair. The first READ starts
the conversion, the second READ gets the results.

The Slow-Memory mode is the simplest. It is the method of
choice where compact coding is essential, or where software
bugs are a hazard. In this mode, a single READ instruction will
initiate a data conversion, interrupt the microprocessor until
completion (WAIT states are introduced), then read the results.
If the system throughput tolerates WAIT states, and the hardware

is correct, then the Slow-Memory mode is virtually immune to
subsequent software modifications. Placing the microprocessor
in the WAIT state has an additional advantage of quieting the
digital system to reduce noise pickup in the analog conversion
circuitry. The 12-bit parallel Slow-Memory mode provides the
fastest analog sampling rate combined with digital data transfer
rate for sampled-data systems.

PARALLEL READ, SLOW-MEMORY MODE (HBEN = LOW)

Figure 5 shows the timing diagram and data bus status for Par­allel Read, Slow-Memory Mode. CS and RD going low triggers
a conversion and the ADC912A acknowledges by taking BUSY
low. Data from the previous conversion appears on the three­state data outputs. BUSY returns high at the end of conversion,
when the output latches have been updated, and the conversion
result is placed on data outputs D

11

. . . D

0/8

.

TWO-BYTE READ, SLOW-MEMORY MODE

For a two-byte read only the eight data outputs D7 . . . D

0/8

are used. Conversion start procedure and data output status for
the first read operation is identical to Parallel Read, Slow-Memory
Mode. See Figure 6, Timing Diagram and Data Bus Status. At
the end of conversion, the low data byte (DB

... DB0) is read

7

from the A/D converter. A second READ operation with HBEN
high places the high byte on data outputs D

3/11

. . . D

0/8

and
disables conversion start. Note the 4 MSBs also appear on data
outputs D

. . . D8 during these two READ operations.

11

PARALLEL READ, ROM MODE (HBEN = LOW)

A conversion is started with a READ operation. The 12 bits of
data from the previous conversion are available on data outputs
D

. . . D

11

(see Figure 7). This data may be disregarded if

0/8

not required. A second READ operation reads the new data

. . . DB0) and starts another conversion. A delay at least

(DB

11

as long as the ADC912A conversion time must be allowed be­tween READ operations. If a READ takes place prior to the end
of 13 CLKS of the ADC conversion, the remaining bits not yet
tested will be invalid.

TWO-BYTE READ, ROM MODE

For a two-byte read only the data outputs D7 . . . D

are used.

0/8

Conversion is started in the same way with a READ operation
and the data output status is the same as the Parallel Read,
ROM Mode. See Figure 8, Two-Byte Read Timing Diagram,
ROM Mode. Two more READ operations are required to obtain
the new conversion result. A delay equal to the ADC912A con­version time must be allowed between conversion start and
places the high byte (4 MSBs) on data outputs D

3/11

third READ operation accesses the low data byte (DB

. . . D

. . . DB0)

7

0/8

. A

and starts another conversion. The 4 MSBs also appear on data
outputs D

. . . D8 during all three read operations above.

11

REV. B

–11–

ADC912A

CIRCUIT LAYOUT GUIDELINES

As with any high-speed A/D converters, good circuit layout
practice is essential. Wire-wrap boards are not recommended
due to stray pickup of the high-frequency digital noise. A PC
board offers the best results. Digital and analog grounds
should be separated even if they are ground planes instead of
ground traces. Do not lay digital traces adjacent to high­impedance analog traces. Avoid digital layouts that radiate
high-frequency clock signals; i.e., do not lay out digital signal
lines and ground returns in the shape of a loop antenna. Shield
the analog input if it comes from a different PC board source.
Set up a single point ground at AGND (Pin 3) of the ADC912A;
tie all other analog grounds to this point. Also tie the logic
power supply ground, but no other digital grounds, to this point
(see Figure 21). Low impedance analog and digital power sup­ply common returns are essential to low noise operation of the
ADC. Their trace widths should be as wide as possible. Good
power supply bypass capacitors located near the ADC package
ensure quiet operation. Place a 10 µF capacitor in parallel with a

0.01 µF ceramic capacitor across V

to ground and VSS to

DD

ground (near Pin 3).

ANALOG

SUPPLY

+15V GND –15V

COMMON
GROUND

ANALOG

CIRCUITS

AGND V

ADC912A

DGND V

SS

DIGITAL

SUPPLY

RETURN+5V

DD

DIGITAL

CIRCUITS

Figure 21. Power Supply Grounding

In applications where the ADC912A data outputs and control
signals are connected to a continuously active microprocessor
bus, it is possible to get LSB level errors in conversion results.
These errors are due to a feedthrough from the microprocessor
to the internal comparator. The problem can be minimized by
forcing the microprocessor into a WAIT state during conversion
(see Slow-Memory microprocessor interfacing). An alternate
method is isolation of the data bus with three-state buffers, such
as the 74HC541.

INTERFACING TO THE TMS32010 DSP PROCESSOR

Figure 22 shows an ADC912A to TMS32010 interface. The
ADC912A is operating in the ROM mode. The interface
is designed for the maximum TMS32010 clock frequency
of 20 MHz.

ADDRESS BUS

PA

0PA2

CS

RD

ADC912A*

D

11

D

0/8

HBEN

*ESSENTIAL INTERFACE CIRCUITRY SHOWN FOR CLARITY

ADDRESS

DECODE

DATA BUS

EN

DEN

TMS32010*

D

15

D

0

Figure 22. ADC912A to TMS32010 DSP Processor Interface

The ADC912A is mapped at a user-selected port address (PA).
The following I/O instruction starts a conversion and reads the
previous conversion into the data memory:

IN DATA, PA PA = Port Address

DATA = Data Memory Location

When conversion is complete, a second I/O instruction reads the
new data into the data memory and starts another conversion.
Sufficient A/D conversion time must be allowed between I/O
instructions. The very first data read after system power-up
should be discarded.

USING WAIT STATES

The TMS32020 DSP processor has the added capability of
WAIT states. This feature simplifies the hardware required for
slow memory devices by extending the microprocessor bus
access time. Figure 23 shows an ADC912A to TMS32020
interface using one WAIT state to guarantee data interface at
the full 20 MHz clock frequency. This WAIT state extends the
bus access time by 200 ns. In this circuit the ADC912A operated
in the ROM mode where each input instruction (IN DATA, PA)
takes the previous conversion result and stores it in memory. The
next input instruction must be delayed for the length of the A/D
conversion time so that a new conversion result can be read.

–12–

REV. B

SLOW-MEMORY MODE OPERATION USING WAIT

ADDRESS

DECODE

EN

ADDRESS BUS

DATA BUS

D

15

D

0

D

11

D

0/8

A0A

15

HBEN

ADC912A*

TMS32020

CS

RD

IS

*ESSENTIAL INTERFACE CIRCUITRY SHOWN FOR CLARITY

READY

R/W

BUSY

CK

7474

DQ

CLR

CLK OUT

1

20MHz ⴛ2/CLK IN

"1"

SLOW-MEMORY

MODE

ROM MODE

(ONE WAIT STATE)

STATES

The WAIT state feature of the TMS32020 can also be used to
operate the ADC912A in the Slow-Memory mode. This is
accomplished by driving the clock input of the 7474 flip-flop in
Figure 23, from the BUSY output of the ADC912A, instead of
the CLK OUT 1 of the TMS32020. Once a conversion has
started the READY input of the TMS32020 is not released until
the ADC912A completes its 12-bit A/D conversion. This stops
the TMS32020 during the conversion process reducing micro­processor system noise generation. Another advantage for the
system software is the single instruction IN MEM, PA used to
start, process, and read the results of the A/D conversion. This
makes the software code more transportable between systems
operating at different clock speeds. The disadvantage is some
loss in instruction processing time.

ADC912A

Figure 23. ADC912A to TMS32020 Interface Using Wait
States

REV. B

–13–

ADC912A

PIN 1

0.210
(5.33)

MAX

0.200 (5.05)

0.125 (3.18)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

24-Lead Narrow Body Plastic DIP Package

(N-24)

1.275 (32.30)

1.125 (28.60)

24

112

0.022 (0.558)

0.014 (0.356)

0.100

(2.54)

BSC

13

0.070 (1.77)

0.045 (1.15)

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MIN

SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

24-Lead Wide Body SOIC Package

(R-24)

0.6141 (15.60)

0.5985 (15.20)

24 13

1

PIN 1

0.0118 (0.30)

0.0040 (0.10)

0.0500
(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.2992 (7.60)

0.2914 (7.40)

12

0.1043 (2.65)

0.0926 (2.35)

SEATING
PLANE

0.4193 (10.65)

0.3937 (10.00)

0.0125 (0.32)

0.0091 (0.23)

0.0291 (0.74)

0.0098 (0.25)

8ⴗ
0ⴗ

ⴛ 45ⴗ

0.0500 (1.27)

0.0157 (0.40)

–14–

REV. B

Revision History–ADC912A

Location Page

Data Sheet changed from REV. A to REV. B.

Changes to General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to Static Accuracy section of Specification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

REV. B

–15–

C00384–0–6/01(B)

–16–

PRINTED IN U.S.A.