Analog Devices ADAV804 prg Datasheet

Audio Codec

Preliminary Technical Data

FEATURES

Stereo Analog to Digital Converter (ADC)

Supports 48/96 kHz Sample Rates 102 dB Dynamic Range Single-Ended Input Automatic Level Control

Stereo Digital to Analog Converter (DAC)

Supports 32/44.1/48/96/192 kHz Sample Rates 103 dB Dynamic Range

Differential Output Asynchronous operation of ADC and DAC Stereo Sample Rate Converter (SRC)

Input/Output Range - 8 - 96 kHz

140 dB Dynamic Range Digital Interfaces

Record

Playback

Aux Record

Aux Playback S/PDIF (IEC60958) Input & Output

Digital Interface Receiver (DIR)

Digital Interface Transmitter (DIT) PLL based Audio MCLK Generators Generates Required DVDR System MCLKs Device Control via I 64-Lead LQFP Package

C compatible serial port

APPLICATIONS

DVD-Recordable All Formats CD-R/W

PRODUCT OVERVIEW

The ADAV804 is a stereo audio codec intended for applications, such as DVD or CD recorders, requiring high performance, flexible and cost effective playback and record functionality. The ADAV804 features Analog Devices proprietary, high performance converter cores to provide record (ADC), playback (DAC) and format conversion (SRC) in a single chip. The ADAV804's record channel features variable input gain to allow for adjustment of recorded input levels, followed by a high performance stereo ADC whose digital output is sent to the record interface. The record channel also features Level Detectors which can be used in feedback loops to adjust input levels for optimum recording. The playback channel features a high performance stereo DAC with independent digital volume control.

The Sample Rate Converter (SRC) provides high performance sample-rate conversion to allow inputs and outputs requiring different sample rates to be matched. The SRC input can be selected from Playback, Auxiliary, DIR or ADC (record). The SRC output can be applied to the Playback DAC, both main and Auxiliary record channels and a DIT. (continued on Page 12)

FUNCTIONAL BLOCK DIAGRAM

I K

O K L C M

For Recordable DVD

ADAV804

VINL

VINR

VREF

VOUTLN VOUTLP VOUTRN VOUTRP

FILTD

Rev. Pr G

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademar ks are the property of their respective orners.

Analog to Digital

Converter

Reference SRC

Digital to Analog

Converter

ADAV804

Playback

Data Input

K L C R L

PLL

Switching Matrix

Figure 1.

Control

Registers

Record

Data

Digital

Input/Output

(Datapath)

Aux Data

Input

K L

Output

Aux Data

Output

DIT

DIR

S X U A

OLRCLK OBCLK OSDATA

OAUXLRCLK OAUXBCLK OAUXSDATA

DITOUT

ZEROL/INT ZEROR

804-0001

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ADAV804 Preliminary Technical Data

TABLE OF CONTENTS

Specifications..................................................................................... 3

Conceptual High Interpolation Model.................................... 16

Timing Specifications....................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Functional Description.................................................................. 12

ADC Section ............................................................................... 12

DAC Section.................................................................................... 15

SRC Functional Overview ............................................................. 16

Theory of Operation ..................................................................16

REVISION HISTORY

Hardware Model......................................................................... 17

The Sample Rate Converter Architecture............................... 17

PLL Section ................................................................................. 18

SPDIF Transmitter AND Receiver........................................... 20

Serial Data Ports......................................................................... 25

Clocking Scheme........................................................................ 25

Interface Control........................................................................ 26

Outline Dimensions....................................................................... 54

Ordering Guide .......................................................................... 54

Rev. Pr G | Page 2 of 54

Preliminary Technical Data ADAV804

SPECIFICATIONS

Table 1. Test Conditions Unless Otherwise Noted

Supply Voltage

Analog +3.3 V

Digital +3.3 V Ambient Temperature 25°C Master Clock (XIN) 12.288 MHz Measurement Bandwidth 20 Hz to 20 kHz Word Width (All Converters) 24-bits Load Capacitance on Digital Outputs 100 pF ADC Input Frequency 997Hz at −1 dBFS DAC Output Frequency 997Hz at −1 dBFS Digital Input: Slave Mode, I2S Justified Format Digital Output: Master Mode, I2S Justified Forma

Table 2. P G A S ec ti on

Min Typ Max Unit Conditions

Input Impedance 4

kΩ Minimum Gain 0 dB Maximum Gain 24 dB Gain Step 0.5 dB Gain Step Error TBD dB

Table 3. Reference Section

Min Typ Max Unit Conditions

Absolute Voltage, V V

Temperature Coefficient

REF

1.5 V

REF

TBD

ppm/

°C

Table 4. AD C S ection

Min Typ Max Unit Conditions

Number of Channels 2 Resolution 24 Bits Dynamic Range −60 dB Input

Unweighted 98 100 dB

A-Weighted 99 102 dB Total Harmonic Distorton + Noise −85 dB Input = −1.0 dBFS Analog Input Input Range (± Full Scale) 1.0 V V

1.5 V

REF

RMS

DC Accuracy

Gain Error −1 dB Interchannel Gain Mismatch 0.01 dB Gain Drift 100 ppm/°C

Offset TBD mV Crosstalk (EIAJ Method) 100 dB Volume Control Step Size (256 Steps) 0.39 % per step Maximum Volume Attenuation -48 dB Group Delay TBD µS

The figures quoted are target specifications and subject to change before release

Rev. Pr G | Page 3 of 54

ADAV804 Preliminary Technical Data

Table 5. ADC Low-Pass Digital Decmation Filter Characteristics1

Sample Rate Pass Band Stop Band Stop Band Pass Band (kHz) Frequency (kHz) Frequency (kHz) Attenuation (dB) Ripple (dB)

48 0.45314 × fS 0.54648 × fS 120 ±0.01 96 TBD × fS TBD × fS TBD ±TBD

Guaranteed by Design

Table 6. ADC High-Pass Digital Filter Characteristics (f

Min Typ Max Units

Cutoff Frequency 0.9 Hz

Table 7 . SRC Se c tion

Min Typ Max Unit Conditions

Resolution 24 Bits Sample Rate 8 96 kHz XIN = 27MHz Maximum Sample Rate Ratios Minimum SRC MCLK 138 × f

Upsampling 1:8 Downsampling 7.75:1

Dynamic Range 20 Hz to fS/2, 1 kHz, –60 dBFS Input

Unweighted 120 dB Worst Case - 96 kHz:8 kHz A-Weighted 125 dB Worst Case - 96 kHz:8 kHz

Total Harmonic Distortion + Noise −110 dB 20 Hz to fS/2, 1 kHz, 0 dBFS Input

Table 8 . DAC S e ct i o n

Min Typ Max Unit Conditions

Number of Channels 2 Resolution 24 Bits Dynamic Range (20 Hz to 20 kHz, −60 dB Input)

Unweighted 100 dB A-Weighted TBD 103 dB

A-Weighted TBD dB fS = 96 KHz Total Harmonic Distorton + Noise −96 dB Digital Input = −1.0 dBFS Total Harmonic Distorton + Noise TBD dB Digital Input = −1.0 dBFS, fS = 96 KHz Analog Outputs

Output Range (± Full Scale) 1.0 Vrms

Output Resistance TBD

Common Mode Output Voltage 1.5 V DC Accuracy

Gain Error −1 dB Interchannel Gain Mismatch 0.01 dB

Gain Drift 25 ppm/°C Crosstalk (EIAJ Method) 125 dB Phase Deviation TBD Degrees Mute Attenuation −63 dB Volume Control Step Size (128 Steps) 0.5 dB Group Delay TBD µs

The figures quoted are target specifications and subject to change before release

= 48 kHz)

S-MAX

Ω

S-MAX

output sample rate

is the greater of the input or

Rev. Pr G | Page 4 of 54

Preliminary Technical Data ADAV804

Table 9. DAC Low-Pass Digital Interpolation Filter Characteristics

Sample Rate Pass Band Stop Band Stop Band Pass Band

(kHz) Frequency (kHz) Frequency (kHz) Attenuation (dB) Ripple (dB)

44.1 0.4535 × fS 0.5464 × fS 70 ±0.002

48 0.4541 × fS 0.5464 × fS 70 ±0.002

96 0.4161 × fS 0.5927 × fS 70 ±0.005

Table 10. PLL Section

Min Typ Max Unit Conditions

Master Clock Input Frequency 27/54 MHz

Generated System Clocks

MCLKO 27/54 MHz SYSCLK1 256 768 × fS

SYSCLK2 256 768 × fS

SYSCLK3 256 512 × fS 256/512 × 32/44.1/48 kHz1

Jitter

SYSCLK1 TBD ps rms SYSCLK2 TBD ps rms SYSCLK3 TBD ps rms

Sample Frequency can be doubled

Table 11. DIR Section

Min Typ Max Unit Condition

Input Sample Frequency 27.2 220 kHz

DIR-MCLK Frequency TBD MHz

DIR-MCLK Jitter TBD ps

Differential Input Voltage TBD mV

Table 12. DIT Section

Min Typ Max Unit Condition

Output Sample Frequency 27.2 220 kHz

Table 13. Digital I/O

Min Typ Max Unit Condition

Input Voltage HI (VIH) 2.0 DVDD V

Input Voltage LO (VIL) 0.8 V

Input Leakage (IIH@ VIH = 3.3 V) 10 µA

Input Leakage (IIL@ VIL = 0 V) 10 µA

Output Voltage HI (VOH @ IOH = 1 mA) 2.4 V

Output Voltage LO (VOL @ IOL = -1 mA) 0.4 V

Input Capacitance 15 pF

256/384/512/768 × 32/44.1/48 kHz

Rev. Pr G | Page 5 of 54

ADAV804 Preliminary Technical Data

Table 1 4 . Po wer

Min Typ Max Unit Condition

Supplies

Voltage, AVDD 3.0 3.3 3.6 V Voltage, DVDD 3.0 3.3 3.6 V Voltage, ODVDD 3.0 3.3 3.6 V Analog Current 45 mA All Supplies at 3.6V Digital Current, DVDD 56 mA All Supplies at 3.6V Digital Interface Current, ODVDD 12 mA All Supplies at 3.6V Analog Current—Power Down TBD µA

Digital Current - Power Down TBD µA Digital Interface Current - Power Down TBD µA

Power Supply Rejection

1 kHz 300 mV 20 kHz 300 mV

Signal at Analog Supply Pins TBD dB

P-P

Signal at Analog Supply

P-P

TBD dB

Pins Stopband (>0.55 × FS)—any 300 mV

Signal TBD dB

P-P

RESET

Low, No MCLK

RESET

Low, No MCLK

RESET

Low, No MCLK

Rev. Pr G | Page 6 of 54

Preliminary Technical Data ADAV804

TIMING SPECIFICATIONS

Table 15.

Parameter Min Max Unit Comments

MASTER CLOCK AND RESET

MCLKI Frequency 24.576 MHz

MCLK

XIN Frequency 54 MHz

XIN

RESET

Low

I2C PORT

SCL Clock Frequency 400 kHz

SCL

SCL High 0.6 µS

SCLH

SCL Low 1.3 µS

SCLL

Start Condition -

Setup Time 0.6 µS

SCS

Hold Time 0.6 µS

SCH

tDS Data Setup Time 100 ns t

SCL Rise Time 300 ns

SCR

SCL Fall Time 300 ns

SCF

SDA Rise Time 300 ns

SDR

SDA Fall Time 300 ns

SDF

Stop Condition

Setup Time 0.6 µS

SCS

SERIAL PORTS1

Slave Mode

xBCLK High 40 ns

SBH

xBCLK Low 40 ns

SBL

xBCLK Frequency 64 × fS

SBF

xLRCLK Setup 10 ns To xBCLK Rising Edge

SLS

xLRCLK Hold 10 ns From xBCLK Rising Edge

SLH

xSDATA Setup 10 ns To xBCLK Rising Edge

SDS

xSDATA Hold 10 ns From xBCLK Rising Edge

SDH

xSDATA Delay 10 ns From xBCLK Falling Edge

SDD

Master Mode

xLRCLK Delay 5 ns From xBCLK Falling Edge

MLD

xSDATA Delay 10 ns From xBCLK Falling Edge

MDD

xSDATA Setup 10 ns From xBCLK Rising Edge

MDS

xSDATA Hold 10 ns From xBCLK Rising Edge

MDH

The prefix x refers to I-, O-, IAUX- or OAUX- for the full pin name

Table 16. Temperature Range

Min Typ Max Units

Specifications Guaranteed 25 °C

Functionality Guaranteed −40 85 °C

Storage −65 150 °C

Specifications subject to change without notice.

20 ns

Relevant for Repeated Start Condition

After this period the 1st clock is generated

Rev. Pr G | Page 7 of 54

ADAV804 Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

Table 1 7 .

Parameter Rating

DVDD to DGND and ODVDD to DGND

AVDD to AGND 0 V to 4.6 V Digital Inputs DGND − 0.3 V to DVDD + 0.3 V Analog Inputs AGND − 0.3 V to AVDD + 0.3 V AGND to DGND −0.3 V to +0.3 V Reference Voltage

Soldering (10 s) +300°C

0 V to 4.6 V

Indefinite short circuit to ground

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. Pr G | Page 8 of 54

Preliminary Technical Data ADAV804

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VINR

VINL

AGND

AVDD

DIR_LF

DIR_GND

DIR_VDD

RESET

AD0

SDA

SCL AD1

ZEROL/INT

ZEROR

DVDD

DGND

N L P A C

64 63 62 61 60 59 58

PIN 1

IDENTIFIER 3 4

5 6 7 8 9

10 11 12

14 15 16

17 18 19 20 21 22 23 24

K L C R L

P A

R P A C

K L C R L O

R P A C

K L C B

D D V A

(Not to Scale)

A T A D S O

57 56 55 54 53 52 51 50 49

ADAV803

TOP VIEW

25 26

Figure 2. 64-Lead Plastic Quad Flatpack [LQFP] (ST-520)

ADVDD

ADGND

PLL_LF2

PLL_LF1

PLL_GND

PLL_VDD

DGND

SYSCLK1

SYSCLK2

SYSCLK3

XIN

XOUT

MCLKO

MCLKI

DVDD

DGND

5 4 0 0

3 0 8

Table 18. ADAV804 Pin Function Descriptions

Pin Number Input/Output Mnemonic Description

1 INPUT VINR Analog Audio Input - Right Channel 2 INPUT VINL Analog Audio Input - Left Channel 3 AGND Analog Ground 4 AVDD Analog Voltage Supply 5 DIR_LF DIR Phase Locked Loop (PLL) Loop Filter Pin 6 DIR_GND Supply Ground for DIR Analog Section. This pin should be connected to AGND 7 DIR_VDD Supply for DIR Analog Section. This pin should be connected to AVDD 8 INPUT

RESET

Reset input (Active Low) 9 INPUT AD0 I2C Address LSB 10 INPUT/OUTPUT SDA Data Input/Output of I2C compatible control interface

11 INPUT SCL Clock Input of I2C compatible control interface 12 INPUT AD1 I2C Address MSB 13 OUTPUT ZEROL/INT

Left Channel (Output) Zero Flag or Interrupt (Output) Flag. The function of this

pin is determined by the INTRPT bin in DAC Control Register 4 14 OUTPUT ZEROR Right Channel (Output) Zero Flag 15 DVDD Digital Voltage Supply 16 DGND Digital Ground 17 INPUT/OUTPUT ILRCLK Sampling Clock (LRCLK) of Playback Digital Input Port 18 INPUT/OUTPUT IBCLK Serial Clock (BCLK) of Playback Digital Input Port 19 INPUT ISDATA Data Input of Playback Digital Input Port 20 INPUT/OUTPUT OLRCLK Sampling Clock (LRCLK) of Record Digital Output Port 21 INPUT/OUTPUT OBCLK Serial Clock (BCLK) of Record Digital Output Port 22 OUTPUT OSDATA Data Output of Record Digital Output Port

Rev. Pr G | Page 9 of 54

ADAV804 Preliminary Technical Data

Pin Number Input/Output Mnemonic Description

23 INPUT DIRIN Input to Digital Input Receiver (S/PDIF) 24 ODVDD Interface Digital Voltage Supply 25 ODGND Interface Digital Ground 26 OUTPUT DITOUT S/PDIF Output from DIT 27 INPUT/OUTPUT OAUXLRCLK Sampling Clock (LRCLK) of Auxiliary Digital Output Port 28 INPUT/OUTPUT OAUXBCLK Serial Clock (BCLK) of Auxiliary Digital Output Port 29 OUTPUT OAUXSDATA Data Output of Auxiliary Digital Output Port 30 INPUT/OUTPUT IAUXLRCLK Sampling Clock (LRCLK) of Auxiliary Digital Input Port 31 INPUT/OUTPUT IAUXBCLK Serial (BCLK) of Auxiliary Digital Input Port 32 INPUT IAUXSDATA Data Input of Auxiliary Digital Input Port 33 DGND Digital Ground 34 DVDD Digital Supply Voltage 35 INPUT MCLKI External MCLK Input 36 OUTPUT MCLKO Oscillator Output 37 INPUT XOUT Crystal Input 38 INPUT XIN Crystal or External MCLK Input 39 OUTPUT SYSCLK3 System Clock 3 (from PLL 2) 40 OUTPUT SYSCLK2 System Clock 2 (from PLL 2) 41 OUTPUT SYSCLK1 System Clock 1 (from PLL 1) 42 DGND Digital Ground 43 PLL_VDD Supply for PLL Analog Section. This pin should be connected to AVDD 44 PLL_GND Ground for PLL Analog Section. This pin should be connected to AGND 45 PLL_LF1 Loop Filter for PLL1 46 PLL_LF2 Loop Filter for PLL2 47 ADGND Analog Ground (Mixed Signal) 48 ADVDD Analog Voltage Supply (Mixed Signal). This pin should be connected to AVDD 49 OUTPUT VOUTR Right Channel Analog Output 50 NC No Connect 51 OUTPUT VOUTL Left Channel Analog Output 52 NC No Connect 53 AVDD Analog Voltage Supply 54 AGND Analog Ground 55 FILTD Output DAC Reference Decoupling 56 AGND Analog Ground 57 VREF Voltage Reference Voltage 58 AGND Analog Ground 59 AVDD Analog Voltage Supply 60 CAPRN ADC Modulator Input Filter Capacitor (Right Channel - Negative) 61 CAPRP ADC Modulator Input Filter Capacitor (Right Channel - Positive) 62 AGND Analog Ground 63 CAPLP ADC Modulator Input Filter Capacitor (Left Channel - Positive) 64 CAPLN ADC Modulator Input Filter Capacitor (Left Channel - Negative)

Rev. Pr G | Page 10 of 54

Preliminary Technical Data ADAV804

(continued from Page 1)

Operation of the ADAV804 is controlled via an I interface, which allows individual Control Register settings to be programmed. The ADAV804 operates from a single analog +3.3 V power supply - and a digital power supply of +3.3 V with optional digital interface range of 3.0 V to +3.6 V. It is housed in

C serial

a 64-lead LQFP package and is characterized for operation over the commercial temperature range −40°C to 85°C.

Rev. Pr G | Page 11 of 54

ADAV804 Preliminary Technical Data

FUNCTIONAL DESCRIPTION

ADC SECTION

The ADAV804's ADC section is implemented using a 2nd order multi-bit (5-bits) Sigma-Delta modulator. The modulator is sampled at either half the ADC MCLK rate (Modulator Clock = 128 × f

) or a quarter of the ADC MCLK rate (Modulator Clock

= 64 × f followed by a cascade of 3 half-band FIR filters. The Sinc decimates by a factor of 16 at 48 kHz and by 8 at 96 kHz. Each of the half-band filters decimates by a factor of 2. Figure 3 below shows the detail of the ADC section. The ADC can be clocked by a number of different clock sources to control the sample rate. MCLK selection for the ADC is set by Internal Clocking Control Register 1 (address = 0x76). The ADC provides an output word of up to 24 bits in resolution in 2s complement format. The output word can be routed to the output ports, to the sample rate converter or to the SPDIF digital transmitter.

). The digital decimator consists of a Sinc^5 filter

DIR PLL(512 × f

DIR PLL(256 × f

)

PLL2 INTERNAL

)

ADC MCLK

DIVIDER

PLL1 INTERNAL

MCLKI

XIN

REG:0x6F BITS 1-0

REG: 0x76 BITS4-2

Programmable Gain Amplifier (PGA)

The input of the record channel features a PGA which converts the single-ended signal to a differential signal which is applied to the analog sigma-delta modulator of the ADC. The PGA can be programmed to amplify a signal by up to 24dB in 0.5dB increments. Figure 4 details the structure of the PGA circuit.

4-64kΩ

External

Capacitor

4kΩ

VREF

8kΩ

(1nFNPO)

125Ω

External

Capacitor

(1nF NPO)

CAPxN

External

Capacitor

(1nF NPO)

CAPxP

Modulator

5 0 0 0

1 0 8

Figure 4. PGA Block Diagram

Analog Sigma Delta Modulator

The ADC features a 2nd order, multi-bit, Sigma-Delta modulator. The input features two integrators in cascade followed by a flash converter. This multi-bit output is directed to a scrambler, followed by a DAC for loop feedback. The Flash ADC output is also converted from "thermometer" coding to "binary" coding for input as a 5-bit word to the decimator. Figure 5 shows the ADC block diagram.

ADC

MCLK

ADC

Figure 3. Clock Path Control on the ADC

MULTI-BI T

SIGMA-DELTA

MODULATOR

ADC M ODCLK

ADC M CLK/2

(TYP 6.144MHz)

CONTROL

HALFBAND

FILTER

VOLUM E

SINC^5

DECIMATOR

384kHz 768kHz

Figure 5. ADC Block Diagram

The ADC also features independent digital volume control for the left and right channels. The volume control consists of 256 linear steps with each step reducing the digital output codes by

0.39%. Each channel also has a peak detector which records the peak level of the input signal. The peak detector register is cleared by reading it.

PEAK

DETECT

HALFBAND

FILTER

801-0003

48kHz 96kHz

192kHz 384kHz

HPF

SINC

COMPENSATION

96kHz

192kHz

Rev. Pr G | Page 12 of 54

Preliminary Technical Data ADAV804

Selecting A Sample Rate

The sample rate of the ADC is always 256 × f

. To facilitate

different MCLKs the ADC block has a programmable divider which allows the MCLK to be divided by 1, 2 or 3 before being applied to the ADC. This allows for MCLKs of 256 × f

, 512 × f

or 768 × fS to be applied to the ADC. To synchronize the data output port with the ADC the same divider setting should be applied to the Internal Clock (ICLK1 or ICLK2) which is controlling the output port. The Internal Clock dividers are shown in Figure 34. By default the ∑∆ modulator runs at ADC MCLK/2. The modulator is designed to run with a maximum clock rate of 6.144MHz,. For cases where higher sample rates would run the modulator at speeds higher than this the user can select divide the ADC MCLK by 4 before it is applied to the modulator. To compensate for this the modulator uses an alternate filter configuration. The divide setting is selected by the AMC bit in ADC Control Register 1.Automatic Level Control (ALC)

The ADC record channel features a programmable automatic level control block. This block monitors the level of the ADC output signal and will automatically reduce the gain if the signal at the input pins causes the ADC output to exceed a preset limit. This function can be useful to maximize the signal dynamic range when the input level is not well-defined. The PGA can be used to amplify the unknown signal and the ALC will reduce the gain until the ADC output is within the preset limits. This results in maximum front-end gain. Since the ALC block monitors the output of the ADC the volume control function should not be used. The ADC volume control scales the results from the ADC and any distortion caused by the input signal exceeding the input range of the ADC will still be present at the output of the ADC but scaled by a value determined by the volume control register. The ALC block consists of two functions, Attack Mode and Recovery Mode. The Recovery Mode consists of three settings, namely, No Recovery, Normal Recovery and Limited Recovery. Each of these modes in discussed in detail below. Figure 6 shows an overall flow diagram of the ALC block.

Attack Mode

When the absolute value of the ADC output exceeds the level set by the Attack Threshold bits in the ALC Control Register 2, Attack Mode is initiated. The PGA gain for both channels is reduced by one step (0.5dB). The ALC will then wait for a time determined by the Attack Timer bits before sampling the ADC output value again. If the ADC output is still above the threshold the PGA gain is reduced by a further step. This procedure continues until the ADC output is below the limit set by the Attack Threshold bits. The initial gains of the PGAs are defined by ADC Left PGA Gain Register and ADC Right PGA Gain Register and may be different values. The ALC simply adds or subtracts a common gain offset to these values. The

ALC will preserve any gain difference in dB as defined by those registers. At no time will the PGA gains exceed their initial values. Therefore, the initial gain setting also serves as a maximum value.

The Limit Detection Mode bit in ALC Control Register 1 determines how the ALC should respond to an ADC output which exceeds the set limits. If this bit is a one then both channels must exceed the threshold before the gain is reduced. This mode can be used to prevent unnecessary gain reduction due to spurious noise on a single channel. If the Limit Detection Mode bit is a zero the gain will be reduced when either channel exceeds the threshold.

No Recovery Mode

By default there is no gain recovery. Once the gain has been reduced it will not be recovered until the ALC has been reset, by toggling the ALCEN bit in ALC Control Register 1 or by writing any value to ALC Control Register 3. The latter option is more efficient as it requires only one write operation to reset the ALC function. No Recovery Mode prevents volume modulation of the signal, caused by adjusting the gain, which can create undesirable artifacts in the signal. Since the gain can be reduced but not recovered, care should be taken that spurious signals do not interfere with the input signal as these may trigger a gain reduction unnecessarily.

Normal Recovery

This mode allows for the PGA gain to be recovered providing that the input signal meets certain criteria. Firstly, the ALC must not be in Attack Mo de, i.e., the PGA gain has been reduced sufficiently such that the input signal is below the level set by the Attack Threshold bits. Secondly, the output result from the ADC must be below the level set by the Recovery Threshold bits in ALC Control Register. If both of these criteria are met the gain is recovered by one step (0.5dB). The gain is incrementally restored to its original value assuming the ADC output level is below the Recovery Threshold at intervals determined by the Recovery Time bits. Should the ADC output level exceed the Recovery Threshold while the PGA gain is being restored the PGA gain value will be held and will not continue restoration until the ADC output level is again below the Recovery Threshold. Once the PGA gain is restored to its original value it will not be changed again unless the ADC output value exceeds the Attack Threshold and the ALC then enters Attack Mode. Care should be exercised when using this mode to choose values for the Attack and Recovery thresholds to prevent excessive volume modulation caused by continuous gain adjustments.

Limited Recovery

Limited Recovery Mode offers a compromise between No Recovery and Normal Recovery Modes. If the output level of the ADC exceeds the Attack Threshold then Attack Mode is

Rev. Pr G | Page 13 of 54

ADAV804 Preliminary Technical Data

initiated. When Attack Mode has reduced the PGA gain to suitable levels the ALC will attempt to recovery the gain to its original level. If the ADC output level exceeds the level set by the Recovery Threshold bits a counter is incremented (GAINCNTR). This counter is incremented, at intervals equal to the Recovery Time selection, if the ADC has any excursion

ATTACK MODE

above the Recovery Threshold. If the counter reaches its maximum value, determined by the GAINCNTR bits in ALC Control Register 1, the PGA gain is deemed suitable and no further gain recovery is attempted. If, at any time, the ADC output level exceeds the Attack Threshold, Attack Mode is reinitiated and the counter is reset

WAIT FOR S AMPLE

LIMITED RECOVERY

WAIT FOR SAMPLE

IS SAMPLE

ABOVE A TTACK

THRESHOLD?

YES

IS SAMPLE

BELOW RECOVERY

THRESHOLD?

IS A RECOVERY MODE ENABLED?

YES

WAIT

RECOVERY

TIME

IS SAMPLE

GREATER THAN ATTACK

THRESHOLD?

YES

DECREASE GAIN BY 0 .5dB

AND WAIT ATTACK TIME

NORMAL RECOVE RY

WAIT FOR SAMPL E

IS SAMPLE

ABOVE A TTACK

THRESHOLD?

IS SAMPLE

BELOW RECOVERY

THRESHOLD?

YES

WAIT

RECOVERY

TIME

INCREASE GAIN BY 0.5dB

WAIT RECOVERY TIME

HAS GAIN BEEN

FULLY RESTORED?

YES

INCREMENT

GAINCNTR

IS GAINCNTR

AT MAXIMUM?

NOYES

INCREASE GAIN BY 0.5dB

WAIT RECOVERY TIME

HAS GAIN BEEN

FULLY RESTORED?

YES

7 2 1 0

1 0 8

Figure 6. ALC Flow Diagram

Rev. Pr G | Page 14 of 54

Preliminary Technical Data ADAV804

DAC SECTION

The ADAV804 has two DAC channels arranged as a stereo pair with differential outputs. Each channel has its own independently programmable attenuator, adjustable in 128 steps of 0.375dB per step. The DAC can receive data from the playback or auxiliary input ports, the SRC, the ADC or the DIR. Each analog output pin sits at a dc level of VREF, and swings 1.0 Vrms for a 0dB digital input signal. A single op-amp third-order external low-pass filter is recommended to remove highfrequency noise present on the output pins. Note that the use of op amps with low slew rate or low bandwidth may cause high frequency noise and tones to fold down into the audio band; care should be exercised in selecting these components. The FILTD and FILTR pins should be bypassed by external capacitors to AGND. The FILTD pin is used to reduce the noise of the internal DAC bias circuitry, thereby reducing the DAC output noise. The voltage at the VREF pin, FILTR can be used to bias external op amps used to filter the output signals. For applications where the FILTR is required to drive external op amps which may draw more than 50µA or may have dynamic load changes extra buffering should be used to preserve the quality of the ADAV804 reference. The digital input data source for the DAC can be selected from a number of available sources. by programming the appropriate bits in the Datapath Control register. Figure 7 shows how the digital data source and MCLK source for the DAC are selected. Each DAC has an independent volume register giving 256 steps of control with each step giving approximately 0.375dB of attenuation. Each DAC also has a peak level register which records the peak value of the digital audio data. Reading the register clears the peak .

DAC

ANALOG

OUTPUT

DAC

MULTI-BI T

SIGMA-DELTA

MODULATO R

TO ZERO FLAG PINS

Figure 8. DAC Block Diagram

TO CONTROL

INTERPOLATOR

Selecting a Sample Rate

Correct operation of the DAC is dependant upon the data rate provided to the DAC, the master clock applied to the DAC and the selected interpolation rate. By default the DAC assumes that the MCLK rate is 256 times the sample rate which requires an 8 times oversampling rate. This combination is suitable for sample rates up to 48kHz. For the case of a 96kHz data rate which has a 24.576MHz MCLK (256 × f

) associated with it the

DAC MCLK divider should be set to divide the MCLK by 2. This will prevent the DAC engine being run too fast. To compensate for the reduced MCLK rate the interpolator should be selected to operate in 4 × (DAC MCLK = 128 × f combinations can be selected for different sample rates.

DIR PLL(256 × f

DIR PLL(512 × f

PLL1 INTERNAL

PLL2 INTERNAL

MCLKI

XIN

REG: 0x76 BITS 7-5

REG:0x65 BITS 3-2

DAC

INPUT

FROM DAC DATAPATH MULTIPLEXER

REG: 0x63 BITS 5-3

AUXILIARY IN PLAYBACK DIR ADC

REGISTERS

)

MCLK

DIVIDER

DAC

MCLK

DAC

801-0007

Figure 7. Clock and data Path Control on the DAC

PEAK

DETECTOR

VOLUME/MUTE

CONTROL

ZERO DETECT

801-0006

). Similar

Rev. Pr G | Page 15 of 54

ADAV804 Preliminary Technical Data

S_OUT

0 0

1 0

S_IN

= 192

OUT

× 220.

SRC FUNCTIONAL OVERVIEW

THEORY OF OPERATION

Asynchronous sample rate conversion is converting data from at the same or different sample rate. The simplest approach to an asynchronous sample rate conversion is the use of a zeroorder hold between the two samplers shown in Figure 9 In an asynchronous system, T2 is never equal to T1 nor is the ratio between T2 and T1 rational. As a result, samples at fS_OUT will be repeated or dropped producing an error in the re-sampling process. The frequency domain shows the wide side lobes that result from this error when the sampling of fS_OUT is convolved with the attenuated images from the sin(x)/x nature of the zero-order hold. The images at fS_IN, dc signal images, of the zero-order holdare infinitely attenuated. Since the ratio of T2 to T1 is an irrational number, the error resulting from the resampling at fS_OUT can never be eliminated. However, the error can be significantly reduced through interpolation of the input data at fS_IN. The sample rate converter in the ADAV804/ is conceptually interpolated by a factor of 2

=1/T1

S_IN

SPECTRUM OF ZERO-ORDER HOLD OUTPUT

ZERO-ORDER

HOLD

ORIGINAL SIGNAL

SAMPLED AT f

SIN(X)/X OF ZER0-ORDER HOLD

S_IN

S_OUT

OUT

=1/T2

INTERPOLATE

BY N

S_IN

TIME DOMAIN OF f

TIME D OMAIN OUTPUT OF THE LOW-PASS FILTER

TIME D OMAIN OF f

TIME DOMAIN OF THE ZERO-ORDER HOLD OUTPUT

LOW-P ASS

S_IN

S_OUT

FILTER

SAMPLES

RESAMPLING

ZERO-ORDER

HOLD

Figure 10. SRC Time Domain

In the frequency domain shown in Figure 11, the interpolation expands the frequency axis of the zero-order hold. The images from the interpolation can be sufficiently attenuated by a good low-pass filter. The images from the zero-order hold are now pushed by a factor of 2 of the zero-order hold, which is f

closer to the infinite attenuation point

× 220 The images at the

S_IN

zero-order hold are the determining factor for the fidelity of the output at f

. The worst-case images can be computed from

S_OUT

the zero-order hold frequency response, maximum image = sin (× F/f image that would be 2

The following worst-case images would appear for f

S_INTERP

)/(× F/f

). F is the frequency of the worst-case

S_INTERP

× f

± f

S_IN

/2 , and f

S_IN

S_INTERP

is f

S_IN

kHz:

SPECTRUMOF f

S_OUT

FREQUENCY RESPONSE OF fS_OUT CONVOLVEDWITH ZERO-ORDER HOLD SPECTRUM

S_OUT

SAMPLING

2 × f

S_OUT

801-0008

Figure 9. Zero Order Hold Being Used by fS OUT to Resample Data from fS_IN

CONCEPTUAL HIGH INTERPOLATION MODEL

Interpolation of the input data by a factor of 220 involves placing

−1) samples between each f both the time domain and the frequency domain of interpolation by a factor of 2

would involve the steps of zero-stuffing (220 −1) number of

samples between each f

sample and convolving this

S_IN

interpolated signal with a digital low-pass filter to suppress the images. In the time domain, it can be seen that f closest f the nearest f

× 220 sample from the zero-order hold as opposed to

S_IN

sample in the case of no interpolation. This

S_IN

significantly reduces the re-sampling error.

sample. Figure 10 shows

S_IN

. Conceptually, interpolation by

selects the

S_OUT

Rev. Pr G | Page 16 of 54

Image at f

− 96 kHz = –125.1 dB

S_INTERP

+ 96 kHz = –125.1 dB

S_INTERP

Preliminary Technical Data ADAV804

IN OUT

INTERPOLATE

BY N

S_IN

FREQUENCY DOMAIN OF SAMPLES ATf

FREQUENCY DOMAIN OF THE INTERPOLATION

SIN(X)/X OF ZER0-ORDER HOLD

FREQUENCY DOMAIN OF f

FREQUENCY DOMAIN AFTER RESAMPLING

LOW-P ASS

FILTER

S_OUT

RESAMPLING

S_IN

220× f

ZERO-ORDER

HOLD

S_IN

220× f

S_IN

220× f

S_IN

S_OUT

0 8

Figure 11. Frequency Domain of the Interpolation and Resampling

HARDWARE MODEL

The output rate of the low-pass filter of Figure 10 would be the interpolation rate, 2 rate of 201.3 GHz is clearly impractical, not to mention the number of taps required to calculate each interpolated sample. However, since interpolation by 2 samples between each f low-pass FIR filter are by zero. A further reduction can be realized by the fact that since only one interpolated sample is taken at the output at the f to be performed per f 64-tap FIR filter for each f the images caused by the interpolation. The difficulty with the above approach is that the correct interpolated sample needs to be selected upon the arrival of f convolutions per f must be measured with an accuracy of 1/201.3 GHz = 4.96 ps. Measuring the f frequency is clearly impossible; instead, several coarse measurements of the f over time.

Another difficulty with the above approach is the number of coefficients required. Since there are 2 with a 64-tap FIR filter, there needs to be 2 coefficients for each tap, which requires a total of 2 coefficients. To reduce the amount of coefficients in ROM, the SRC stores small subset of coefficients and performs a high order interpolation between the stored coefficients. So far the above approach works for the case of f the case when the output sample rate, f input sample rate, f

× 192000 kHz = 201.3 GHz. Sampling at a

involves zero-stuffing 220−1

sample, most of the multiplies in the

S_IN

rate, only one convolution needs

S_OUT

period instead of 220 convolutions. A

S_OUT

sample is sufficient to suppress

S_OUT

. Since there are 220 possible

S_OUT

period, the arrival of the f

S_OUT

period with a clock of 201.3 GHz

S_OUT

clock period are made and averaged

S_OUT

possible convolutions

S_OUT

, the ROM starting address, input data,

S_IN

S_OUT

polyphase

> f

. However, in

S_IN

, is less than the

clock

and the length of the convolution must be scaled. As the input sample rate rises over the output sample rate, the anti-aliasing filter’s cutoff frequency has to be lowered because the Nyquist frequency of the output samples is less than the Nyquist frequency of the input samples. To move the cutoff frequency of the antialiasing filter, the coefficients are dynamically altered and the length of the convolution is increased by a factor of (f

S_IN/fS_OUT

This technique is supported by the Fourier transform property that if f(t) is F(ω), then f(k × t) is F(ω/k). Thus, the range of decimation is simply limited by the size of the RAM.

THE SAMPLE RATE CONVERTER ARCHITECTURE

The architecture of the sample rate converter is shown in Figure

12. The sample rate converter’s FIFO block adjusts the left and right input samples and stores them for the FIR filter’s convolution cycle. The f to the FIFO block and the ramp input to the digital servo loop. The ROM stores the coefficients for the FIR filter convolution and performs a high order interpolation between the stored coefficients. The sample rate ratio block measures the sample rate for dynamically altering the ROM coefficients and scaling of the FIR filter length as well as the input data. The digital servo loop automatically tracks the f and provides the RAM and ROM start addresses for the start of the FIR filter convolution.

RIGHT DA TA IN

LEFTDATAIN FIFO

S_IN

COUNTER

S_IN

S_OUT

Figure 12. Architecture of the Sample Rate Converter

The FIFO receives the left and right input data and adjusts the amplitude of the data for both the soft muting of the sample rate converter and the scaling of the input data by the sample rate ratio before storing the samples in the RAM. The input data is scaled by the sample rate ratio because as the FIR filter length of the convolution increases, so does the amplitude of the convolution output. To keep the output of the FIR filter from saturating, the input data is scaled down by multiplying it by (f

S_OUT/fS_IN

) when f

data for muting and unmuting of the SRC.

The RAM in the FIFO is 512 words deep for both left and right channels. An offset to the write address provided by the f counter is added to prevent the RAM read pointer from ever overlapping the write address. The minimum offset on the SRC

counter provides the write address

S_IN

and f

S_IN

ROM A

ROM B

ROM C ROM D

DIGITAL

SERVO LOOP

SAMPLE RATERATIO

SAMPLE RATE

RATIO

< f

S_OUT

. The FIFO also scales the input

S_IN

EXTERNAL

RATIO

FIR FILTER

sample rates

S_OUT

ORDER INTERP

L/R DATA OU

HIGH

801-0011

S_IN

Rev. Pr G | Page 17 of 54

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