ANALOG DEVICES ADAV803 Service Manual

Audio Codec for Recordable DVD

FEATURES

Stereo analog-to-digital converter (ADC) Supports 48 kHz/96 kHz sample rates 102 dB dynamic range Single-ended input Automatic level control Stereo digital-to-analog converter (DAC) Supports 32 kHz/44.1 kHz/48 kHz/96 kHz/192 kHz

sample rates 101 dB dynamic range Single-ended output Asynchronous operation of ADC and DAC Stereo sample rate converter (SRC) Input/output range: 8 kHz to 192 kHz 140 dB dynamic range Digital interfaces Record Playback Auxiliary record Auxiliary playback S/PDIF (IEC 60958) input and output Digital interface receiver (DIR) Digital interface transmitter (DIT) PLL-based audio MCLK generators Generates required DVDR system MCLKs Device control via I 64-lead LQFP package

C-compatible serial port

FUNCTIONAL BLOCK DIAGRAM

MCLKI

XOUT

XIN

MCLKO

VINL

VINR

VREF

VOUTL

VOUTR

FILTD

ANALOG-TO-DI GITAL

CONVERTER

REFERENCE SRC

DIGITAL-TO-ANALO G

CONVERTER

ADAV803

APPLICATIONS

DVD-recordable All formats CD-R/W

SYSCLK1

PLL

PLAYBACK

DATA INPUT

IBCLK

ILRCLK

SYSCLK3

SYSCLK2

DIGITAL

INPUT/OUTPUT

SWITCHING MATRIX

(DATAPATH)

AUX DATA

INPUT

ISDATA

IAUXBCLK

IAUXSDATA

IAUXLRCLK

Figure 1.

ADAV803

SDA

SCL

AD0

AD1

CONTROL

REGISTERS

RECORD

DATA

OUTPUT

AUX DATA

OUTPUT

DIT

DIR

DIRIN

OLRCLK

OBCLK

OSDATA

OAUXLRCLK

OAUXBCLK

OAUXSDATA

DITOUT

ZEROL/INT

ZEROR

04756-001

GENERAL DESCRIPTION

The ADAV803 is a stereo audio codec intended for applications such as DVD or CD recorders that require high performance and flexible, cost-effective playback and record functionality. The ADAV803 features Analog Devices, Inc. proprietary, high performance converter cores to provide record (ADC), playback (DAC), and format conversion (SRC) on a single chip. The ADAV803 record channel features variable input gain to allow for adjustment of recorded input levels and automatic level control, followed by a high performance stereo ADC whose digital output is sent to the record interface. The record channel also features level detectors that can be used in feedback loops to adjust input levels for optimum recording. The playback channel features a high performance stereo DAC with independent digital volume control.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

The sample rate converter (SRC) provides high performance sample rate conversion to allow inputs and outputs that require different sample rates to be matched. The SRC input can be selected from playback, auxiliary, DIR, or ADC (record). The SRC output can be applied to the playback DAC, both main and auxiliary record channels, and a DIT. Operation of the ADAV803 is controlled via an I

C®-compatible serial interface, which allows the programming of individual control register settings. The ADAV803 operates from a single analog 3.3 V power supply and a digital power supply of 3.3 V with an optional digital interface range of 3.0 V to 3.6 V.

The part is housed in a 64-lead LQFP package and is characterized for operation over the commercial temperature range of

−40°C to +85°C.

ADAV803

Features.............................................................................................. 1

Functional Block Diagram .............................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Test Conditions............................................................................. 3

ADAV803 Specifications ............................................................. 3

Timing Specifications .................................................................. 7

Temperature Range ...................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ...........................................11

Functional Description.................................................................. 15

ADC Section ............................................................................... 15

DAC Section................................................................................ 18

Sample Rate Converter (SRC) Functional Overview ............ 19

PLL Section ................................................................................. 22

S/PDIF Transmitter and Receiver............................................ 23

Serial Data Ports......................................................................... 27

Interface Control ............................................................................ 30

C Interface ................................................................................ 30

Block Reads and Writes ............................................................. 31

Layout Considerations................................................................... 59

ADC ............................................................................................. 59

DAC.............................................................................................. 59

PLL ............................................................................................... 59

Reset and Power-Down Considerations ................................. 59

Outline Dimensions....................................................................... 60

Ordering Guide .......................................................................... 60

REVISION HISTORY

7/07—Rev. 0 to Rev. A

Changes to Table 1............................................................................ 3

Changes to ADC Section ............................................................... 15

Changes to Figure 25...................................................................... 15

Changes to Figure 33...................................................................... 21

Changes to SRC Architecture Section ......................................... 21

Changes to Table 7.......................................................................... 22

Changes to Figure 36...................................................................... 22

Changes to Figure 39, Figure 40, Figure 41, Figure 42 .............. 23

Changes to Transmitter Operation Section ................................ 27

Changes to Interrupts Section ...................................................... 27

Changes to Figure 50...................................................................... 28

Changes to Table 97........................................................................ 47

Changes to Table 101...................................................................... 48

Changes to Table 136 and Table 137............................................ 56

Updated Outline Dimensions....................................................... 60

Changes to Ordering Guide.......................................................... 60

7/04—Revision 0: Initial Version

Rev. A | Page 2 of 60

ADAV803

SPECIFICATIONS

TEST CONDITIONS

Test conditions, unless otherwise noted.

Table 1.

Test Parameter Condition

Supply Voltage Analog 3.3 V Digital 3.3 V Ambient Temperature 25°C Master Clock (MCLKI) 12.288 MHz Measurement Bandwidth 20 Hz to 20 kHz Word Width (All Converters) 24 bits Load Capacitance on Digital Outputs 100 pF ADC Input Frequency 1007.8125 Hz at −1 dBFS DAC Output Frequency 960.9673 Hz at 0 dBFS Digital Input Slave Mode, I2S Justified Format Digital Output Slave Mode, I2S Justified Format

ADAV803 SPECIFICATIONS

Table 2.

Parameter Min Typ Max Unit Comments

PGA SECTION

Input Impedance 4 kΩ Minimum Gain 0 dB Maximum Gain 24 dB Gain Step 0.5 dB

REFERENCE SECTION

Absolute Voltage, V V

Temperature Coefficient 80 ppm/°C

REF

ADC SECTION

Number of Channels 2 Resolution 24 Bits Dynamic Range −60 dB input

Unweighted 99 dB fS = 48 kHz 98 dB fS = 96 kHz A-Weighted 98 102 dB fS = 48 kHz 101 dB fS = 96 kHz

Total Harmonic Distortion + Noise Input = −1.0 dBFS

−88 dB fS = 48 kHz

−87 dB fS = 96 kHz Analog Input

Input Range (± Full Scale) 1.0 V rms

DC Accuracy

Gain Error −1.5 −0.8 dB Interchannel Gain Mismatch 0.05 dB Gain Drift 1 mdB/°C Offset −10 mV

1.5 V

REF

Rev. A | Page 3 of 60

ADAV803

Parameter Min Typ Max Unit Comments

Crosstalk (EIAJ Method) −110 dB Volume Control Step Size (256 Steps) 0.39 % per step Maximum Volume Attenuation −48 dB Mute Attenuation ∞ dB ADC outputs all zero codes Group Delay

fS = 48 kHz 910 μs fS = 96 kHz 460 μs

ADC LOW-PASS DIGITAL DECIMATION FILTER CHARACTERISTICS

Pass-Band Frequency 22 kHz fS = 48 kHz 44 kHz fS = 96 kHz Stop-Band Frequency 26 kHz fS = 48 kHz 52 kHz fS = 96 kHz Stop-Band Attenuation 120 dB fS = 48 kHz 120 dB fS = 96 kHz Pass-Band Ripple ±0.01 dB fS = 48 kHz ±0.01 dB fS = 96 kHz

ADC HIGH-PASS DIGITAL FILTER CHARACTERISTICS

Cutoff Frequency 0.9 Hz fS = 48 kHz

SRC SECTION

Resolution 24 Bits Sample Rate 8 192 kHz XIN = 27 MHz SRC MCLK

Maximum Sample Rate Ratios

Upsampling 1:8 Downsampling 7.75:1

Dynamic Range 140

Total Harmonic Distortion + Noise 120 dB

DAC SECTION

Number of Channels 2 Resolution 24 Dynamic Range 20 Hz to 20 kHz, −60 dB input

Unweighted 99 98 A-Weighted 97 101 100

Total Harmonic Distortion + Noise

−91

−90 Analog Outputs

Output Range (± Full Scale) 1.0 Output Resistance 60 Common-Mode Output Voltage 1.5

DC Accuracy

Gain Error −2 −0.8 Interchannel Gain Mismatch 0.05 Gain Drift 1 DC Offset −30

138 × f

MAX

33 MHz

S-

+30

Bits

dB fS = 48 kHz dB fS = 96 kHz dB fS = 48 kHz dB fS = 96 kHz Referenced to 1V rms dB fS = 48 kHz dB fS = 96 kHz

V rms Ω V

dB dB mdB/°C mV

is the greater of the input or

S-MAX

output sample rate

20 Hz to f f

= 44.1 kHz, f

/2, 1 kHz, −60 dBFS input,

= 48 kHz

OUT

/2, 1 kHz, 0 dBFS input,

= 48 kHz

OUT

Rev. A | Page 4 of 60

ADAV803

Parameter Min Typ Max Unit Comments

Crosstalk (EIAJ Method) −110 Phase Deviation 0.05 Mute Attenuation −95.625 Volume Control Step Size (256 Steps) 0.375 Group Delay

48 kHz 630 96 kHz 155 192 kHz 66

DAC LOW-PASS DIGITAL INTERPOLATION FILTER CHARACTERISTICS

Pass-Band Frequency 20 kHz fS = 44.1 kHz 22 kHz fS = 48 kHz 42 kHz fS = 96 kHz Stop-Band Frequency 24 kHz fS = 44.1 kHz 26 kHz fS = 48 kHz 60 kHz fS = 96 kHz Stop-Band Attenuation 70 dB fS = 44.1 kHz 70 dB fS = 48 kHz 70 dB fS = 96 kHz

Pass-Band Ripple ±0.002 dB fS = 44.1 kHz ±0.002 dB fS = 48 kHz ±0.005 dB fS = 96 kHz PLL SECTION

Master Clock Input Frequency 27/54 MHz

Generated System Clocks

MCLKO 27/54 MHz SYSCLK1 256 768 × fS

SYSCLK2 256 768 × fS

SYSCLK3 256 512 × fS 256/512 × 32 kHz/44.1 kHz/48 kHz

Jitter

SYSCLK1 65 ps rms SYSCLK2 75 ps rms SYSCLK3 75 ps rms

DIR SECTION

Input Sample Frequency 27.2 200 kHz

Differential Input Voltage 200 mV DIT SECTION

Output Sample Frequency 27.2 DIGITAL I/O

Input Voltage High, VIH 2.0

Input Voltage Low, VIL

Input Leakage, IIH @ VIH = 3.3 V

Input Leakage, IIL @ VIL = 0 V

Output Voltage High, VOH @ IOH = 0.4 mA 2.4 V

Output Voltage Low, VOL @ IOL = −2 mA

Input Capacitance

dB Degrees dB dB

μs μs μs

256/384/512/768 × 32 kHz/44.1 kHz/48 kHz

200 kHz

DVDD V

0.8 V 10 μA 10 μA

0.4 V 15 pF

Rev. A | Page 5 of 60

ADAV803

Parameter Min Typ Max Unit Comments

POWER

Supplies

Voltage, AVDD 3.0 3.3 3.6 V Voltage, DVDD 3.0 3.3 3.6 V Voltage, ODVDD 3.0 3.3 3.6 V

Operating Current All supplies at 3.3 V

Analog Current 60 mA Digital Current 38 mA Digital Interface Current 13 mA DIRIN/DIROUT Current 5 mA PLL Current 18 mA

Power-Down Current

Analog Current 18 mA Digital Current 2.5 mA Digital Interface Current 700 μA DIRIN/DIROUT Current 3.5 mA PLL Current 900 μA

Power Supply Rejection

Signal at Analog Supply Pins −70 dB 1 kHz, 300 mV p-p

−70 dB 20 kHz, 300 mV p-p

Guaranteed by design.

RESET low, no MCLK

Rev. A | Page 6 of 60

ADAV803

TIMING SPECIFICATIONS

Timing specifications are guaranteed over the full temperature and supply range.

Table 3.

Parameter Symbol Min Typ Max Unit Comments

MASTER CLOCK AND RESET

MCLKI Frequency f

XIN Frequency f

RESET Low I2C PORT

SCL Clock Frequency f

SCL High t

SCL Low t

Start Condition

Setup Time t

Hold Time t Data Setup Time tDS 100 ns SCL Rise Time t SCL Fall Time t SDA Rise Time t SDA Fall Time t

Stop Condition

Setup Time t

SERIAL PORTS

Slave Mode

xBCLK High t xBCLK Low t xBCLK Frequency f xLRCLK Setup t xLRCLK Hold t xSDATA Setup t xSDATA Hold t xSDATA Delay t

Master Mode

xLRCLK Delay t xSDATA Delay t xSDATA Setup t xSDATA Hold t

The prefix x refers to I-, O-, IAUX-, or OAUX- for the full pin name.

12.288 54 MHz

MCLK

27 54 MHz

XIN

20 ns

RESET

400 kHz

SCL

0.6 μs

SCLH

1.3 μs

SCLL

0.6 μs Relevant for repeated start condition

SCS

0.6 μs After this period, the first clock is generated

SCH

300 ns

SCR

300 ns

SCF

300 ns

SDR

300 ns

SDF

0.6 μs

SCS

40 ns

SBH

40 ns

SBL

64 × fS

SBF

10 ns To xBCLK rising edge

SLS

10 ns From xBCLK rising edge

SLH

10 ns To xBCLK rising edge

SDS

10 ns From xBCLK rising edge

SDH

10 ns From xBCLK falling edge

SDD

5 ns From xBCLK falling edge

MLD

10 ns From xBCLK falling edge

MDD

10 ns From xBCLK rising edge

MDS

10 ns From xBCLK rising edge

MDH

TEMPERATURE RANGE

Table 4.

Parameter Min Typ Max Unit

Specifications Guaranteed 25 °C Functionality Guaranteed −40 +85 °C Storage −65 +150 °C

Rev. A | Page 7 of 60

ADAV803

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

DVDD to DGND and ODVDD

to DGND AVDD to AGND 0 V to 4.6 V Digital Inputs DGND − 0.3 V to DVDD + 0.3 V Analog Inputs AGND − 0.3 V to AVDD + 0.3 V AGND to DGND −0.3 V to +0.3 V Reference Voltage

Soldering (10 sec) 300°C

0 V to 4.6 V

Indefinite short circuit to ground

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 8 of 60

ADAV803

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGND

VOUTLNCVOUTR

AVD D

ADVDD

ADGND

PLL_LF2

PLL_LF1

PLL_GND

PLL_VDD

DGND

SYSCLK1

SYSCLK2

SYSCLK3

XIN

XOUT

MCLKO

MCLKI

DVDD

DGND

VINR

VINL

AGND

AVD D

DIR_LF

DIR_GND

DIR_VDD

RESET

AD0

SDA

SCL

AD1

EROL/INT

ZEROR

DVDD

DGND

CAPLN

CAPLP

AGND

PIN 1 INDICATOR

CAPRP

64 63 62 61 60 59 58

17 18 19 20 21 22 23 24

CAPRN

AVD D

AGND

VREF

AGND

FILTD

57 56 55 54 53 52 51 50 49

ADAV803

TOP VIEW

(Not to Scale)

25 26 27 31302928 32

DIRIN

OBCLK

ODVDD

DITOUT

ODGND

OSDATA

OLRCLK

OAUXLRCLK

IAUXBCLK

OAUXBCLK

IAUXSDATA

IAUXLRCLK

OAUXSDATA

04756-002

NC = NO CONNECT

IBCLK

ISDATA

ILRCLK

Figure 2. ADAV803 Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic I/O Description

1 VINR I Analog Audio Input, Right Channel. 2 VINL I Analog Audio Input, Left Channel. 3 AGND Analog Ground. 4 AVDD Analog Voltage Supply. 5 DIR_LF DIR Phase-Locked Loop (PLL) Filter Pin. 6 DIR_GND Supply Ground for DIR Analog Section. This pin should be connected to AGND. 7 DIR_VDD Supply for DIR Analog Section. This pin should be connected to AVDD. 8

RESET

I Asynchronous Reset Input (Active Low).

9 AD0 I I2C Address LSB. 10 SDA I/O Data Input/Output of I2C-Compatible Control Interface. 11 SCL I Clock Input of I2C Compatible Control Interface. 12 AD1 I I2C Address MSB. 13 ZEROL/INT O

Left Channel (Output) Zero Flag or Interrupt (Output) Flag. The function of this pin is determined by

the INTRPT bit in DAC Control Register 4. 14 ZEROR O Right Channel (Output) Zero Flag. 15 DVDD Digital Voltage Supply. 16 DGND Digital Ground. 17 ILRCLK I/O Sampling Clock (LRCLK) of Playback Digital Input Port. 18 IBCLK I/O Serial Clock (BCLK) of Playback Digital Input Port. 19 ISDATA I Data Input of Playback Digital Input Port. 20 OLRCLK I/O Sampling Clock (LRCLK) of Record Digital Output Port. 21 OBCLK I/O Serial Clock (BCLK) of Record Digital Output Port. 22 OSDATA O Data Output of Record Digital Output Port. 23 DIRIN I Input to Digital Input Receiver (S/PDIF). 24 ODVDD Interface Digital Voltage Supply. 25 ODGND Interface Digital Ground. 26 DITOUT O S/PDIF Output from DIT.

Rev. A | Page 9 of 60

ADAV803

Pin No. Mnemonic I/O Description

27 OAUXLRCLK I/O Sampling Clock (LRCLK) of Auxiliary Digital Output Port. 28 OAUXBCLK I/O Serial Clock (BCLK) of Auxiliary Digital Output Port. 29 OAUXSDATA O Data Output of Auxiliary Digital Output Port. 30 IAUXLRCLK I/O Sampling Clock (LRCLK) of Auxiliary Digital Input Port. 31 IAUXBCLK I/O Serial Clock (BCLK) of Auxiliary Digital Input Port. 32 IAUXSDATA I Data Input of Auxiliary Digital Input Port. 33 DGND Digital Ground. 34 DVDD Digital Supply Voltage. 35 MCLKI I External MCLK Input. 36 MCLKO O Oscillator Output. 37 XOUT I Crystal Input. 38 XIN I Crystal or External MCLK Input. 39 SYSCLK3 O System Clock 3 (from PLL2). 40 SYSCLK2 O System Clock 2 (from PLL2). 41 SYSCLK1 O System Clock 1 (from PLL1). 42 DGND Digital Ground. 43 PLL_VDD Supply for PLL Analog Section. This pin should be connected to AVDD. 44 PLL_GND Ground for PLL Analog Section. This pin should be connected to AGND. 45 PLL_LF1 Loop Filter for PLL1. 46 PLL_LF2 Loop Filter for PLL2. 47 ADGND Analog Ground (Mixed Signal). This pin should be connected to AGND. 48 ADVDD Analog Voltage Supply (Mixed Signal). This pin should be connected to AVDD. 49 VOUTR O Right Channel Analog Output. 50 NC No Connect. 51 VOUTL O Left Channel Analog Output. 52 NC No Connect. 53 AVDD Analog Voltage Supply. 54 AGND Analog Ground. 55 FILTD Output DAC Reference Decoupling. 56 AGND Analog Ground. 57 VREF Voltage Reference Voltage. 58 AGND Analog Ground. 59 AVDD Analog Voltage Supply. 60 CAPRN ADC Modulator Input Filter Capacitor (Right Channel, Negative). 61 CAPRP ADC Modulator Input Filter Capacitor (Right Channel, Positive). 62 AGND Analog Ground. 63 CAPLP ADC Modulator Input Filter Capacitor (Left Channel, Positive). 64 CAPLN ADC Modulator Input Filter Capacitor (Left Channel, Negative).

Rev. A | Page 10 of 60

ADAV803

TYPICAL PERFORMANCE CHARACTERISTICS

–50

MAGNITUDE ( dB)

–100

–150

0 0.5 1.0 1.5 2.0

FREQUENCY (Normalized to fS)

Figure 3. ADC Composite Filter Response

–5

–10

–15

MAGNITUDE (d B)

–20

–25

–30

0 5 10 15 20

Figure 4. ADC High-Pass Filter Response, f

FREQUENCY (Hz)

= 48 kHz

–50

MAGNITUDE (dB)

–100

04756-003

–150

0 96 192 288 384

FREQUENCY (kHz )

04756-006

Figure 6. DAC Composite Filter Response, 48 kHz

–50

MAGNITUDE (dB)

–100

04756-004

–150

02412 36 48

FREQUENCY (kHz)

Figure 7. DAC Pass-Band Filter Response, 48 kHz

04756-007

–5

–10

–15

MAGNITUDE (d B)

–20

–25

–30

0 5 10 15 20

Figure 5. ADC High-Pass Filter Response, f

FREQUENCY (Hz)

= 96 kHz

04756-005

Rev. A | Page 11 of 60

0.06

0.04

0.02

MAGNITUDE (d B)

–0.02

–0.04

–0.06

0816

FREQUENCY ( kHz)

Figure 8. DAC Filter Ripple, 48 kHz

04756-008

ADAV803

–50

–100

MAGNITUDE (dB)

–100

–150

0 192 384 576 768

FREQUENCY (kHz)

Figure 9. DAC Composite Filter Response, 96 kHz

–50

MAGNITUDE (dB)

–100

–150

0 2448729

FREQUENCY ( kHz)

Figure 10. DAC Pass-Band Filter Response, 96 kHz

04756-009

04756-010

MAGNITUDE (dB)

–150

–200

0 384 768 1152 1536

FREQUENCY (kHz)

Figure 12. DAC Composite Filter Response, 192 kHz

–2

–4

–6

MAGNITUDE (dB)

–8

–10

48 64 80 96

FREQUENCY (kHz)

Figure 13. DAC Pass-Band Filter Response, 192 kHz

04756-012

04756-013

0.10

0.05

MAGNITUDE (dB)

–0.05

–0.10

0 2448729

FREQUENCY ( kHz)

Figure 11. DAC Filter Ripple, 96 kHz

04756-011

Rev. A | Page 12 of 60

0.50

0.40

0.30

0.20

0.10

–0.10

MAGNITUDE (dB)

–0.20

–0.30

–0.40

–0.50

0 8 16 32 64

FREQUENC Y (kHz)

Figure 14. DAC Filter Ripple, 192 kHz

04756-014

ADAV803

–20

DNR = 102dB

(A-WEIGHTED)

–20

THD+N = 95dB

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 2 4 6 8 1012 141618 20

Figure 15. DAC Dynamic Range, f

–20

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

02468101214161820

Figure 16. DAC THD + N, f

FREQUENCY (kHz)

= 48 kHz

THD+N = 96dB

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

04756-015

04756-016

–160

0 5 10 15 20 25 30 35 40 45 48

Figure 18. DAC THD + N, f

–20

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 5 10 15 20

Figure 19. ADC Dynamic Range, f

FREQUENCY (kHz)

= 96 kHz

FREQUENCY (kHz)

= 48 kHz

DNR = 102dB

(A-WEIGHTED)

04756-018

04756-019

–20

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 5 10 15 20 25 30 35 40 45 48

Figure 17. DAC Dynamic Range, f

FREQUENCY (kHz)

= 96 kHz

DNR = 102dB

(A-WEIGHTED)

04756-017

Rev. A | Page 13 of 60

–20

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 5 10 15 20

Figure 20. DAC THD + N, f

FREQUENCY (kHz)

= 48 kHz

THD+N = 92dB

= –3dB)

04756-020

ADAV803

–20

DNR = 102dB

(A-WEIGHTED)

–20

THD+N = 92dB

= –3dB)

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 8 16 24 32 40 48

Figure 21. ADC Dynamic Range, f

FREQUENCY (kHz)

= 96 kHz

04756-021

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 8 16 24 32 40 48

Figure 22. ADC THD + N, f

FREQUENCY (kHz)

= 96 kHz

04756-022

Rev. A | Page 14 of 60

ADAV803

FUNCTIONAL DESCRIPTION

ADC SECTION

The ADAV803’s ADC section is implemented using a secondorder multibit (5 bits) Σ-Δ modulator. The modulator is sampled at either half of the ADC MCLK rate (modulator clock = 128 × f clock = 64 × f followed by a cascade of three half-band FIR filters. The Sinc decimates by a factor of 16 at 48 kHz and by a factor of 8 at 96 kHz. Each of the half-band filters decimates by a factor of 2.

Figure 23 shows the details of the ADC section. By default, the ADC assumes that the MCLK rate is 256 times the sample rate. The ADC can be clocked by a number of different clock sources to control the sample rate. MCLK selection for the ADC is set by Internal Clocking Control Register 1 (Address 0x76). The ADC provides an output word of up to 24 bits of resolution in twos complement format. The output word can be routed to the output ports, the sample rate converter, or the S/PDIF digital transmitter.

) or one-quarter of the ADC MCLK rate (modulator

). The digital decimator consists of a Sinc^5 filter

)

PLL2 INTE RNAL

PLL1 INTE RNAL

MCLKI

DIR PLL(256 × f

DIR PLL(512 × f

ADC MCLK

DIVIDER

ADC

MCLK

ADC

XIN

REG 0x76 BITS[4:2]

REG 0x6F BITS[1:0]

Programmable Gain Amplifier (PGA)

The input of the record channel features a PGA that converts the single-ended signal to a differential signal, which is applied to the analog Σ-Δ modulator of the ADC. The PGA can be programmed to amplify a signal by up to 24 dB in 0.5 dB increments.

VREF

Figure 24 shows the structure of the PGA circuit.

4kΩ TO 64k Ω

EXTERNAL

4kΩ

8kΩ

CAPACITOR

8kΩ

(1nF NPO)

125Ω

EXTERNAL

CAPACITOR

(1nF NPO)

CAPxN

EXTERNAL

CAPACITOR

(1nF NPO)

CAPxP

Figure 24. PGA Block Diagram

MODULATOR

04756-024

Analog Σ-Δ Modulator

The ADC features a second-order, multibit, Σ-Δ modulator. The input features two integrators in cascade followed by a flash converter. This multibit output is directed to a scrambler, followed by a DAC for loop feedback. The flash ADC output is also converted from thermometer coding to binary coding for input as a 5-bit word to the decimator.

Figure 25 shows the

ADC block diagram.

The ADC also features independent digital volume control for the left and right channels. The volume control consists of 256 linear steps, with each step reducing the digital output codes by 0.39%. Each channel also has a peak detector that records the peak level of the input signal. The peak detector register is cleared by reading it.

Figure 23. Clock Path Control on the ADC

MULTIBIT

Σ-Δ

MODULATOR

ADC MCLK

AMC

(REG 0x6E

BIT 7)

÷2

÷4

MODULATOR

CLOCK

(6.144MHz MAX)

04756-023

SINC^5

DECIMATOR

384kHz

768kHz

HALF-BAND

FILTER

VOLUME

CONTROL

192kHz

384kHz

Figure 25. ADC Block Diagram

Rev. A | Page 15 of 60

HPF

SINC

COMPENSATION

96kHz

192kHz

PEAK

DETECT

HALF-BAND

FILTER

48kHz

96kHz

04756-025

ADAV803

Automatic Level Control (ALC)

The ADC record channel features a programmable automatic level control block. This block monitors the level of the ADC output signal and automatically reduces the gain, if the signal at the input pins causes the ADC output to exceed a preset limit. This function can be useful to maximize the signal dynamic range when the input level is not well defined. The PGA can be used to amplify the unknown signal, and the ALC reduces the gain until the ADC output is within the preset limits. This results in maximum front end gain.

Because the ALC block monitors the output of the ADC, the volume control function should not be used. The ADC volume control scales the results from the ADC, and any distortion caused by the input signal exceeding the input range of the ADC is still present at the output of the ADC, but scaled by a value determined by the volume control register.

The ALC block has two functions, attack mode and recovery mode. Recovery mode consists of three settings: no recovery, normal recovery, and limited recovery. These modes are discussed in the following sections. of the ALC block. When the ALC has been enabled, any changes made to the PGA or ALC settings are ignored. To change the functionality of the ALC, it must first be disabled. The settings can then be changed and the ALC re-enabled.

Figure 26 is a flow diagram

Attack Mode

When the absolute value of the ADC output exceeds the level set by the attack threshold bits in ALC Control Register 2, attack mode is initiated. The PGA gain for both channels is reduced by one step (0.5 dB). The ALC then waits for a time determined by the attack timer bits before sampling the ADC output value again. If the ADC output is still above the threshold, the PGA gain is reduced by a further step. This procedure continues until the ADC output is below the limit set by the attack threshold bits. The initial gains of the PGAs are defined by the ADC left PGA gain register and the ADC right PGA gain register, and they can have different values. The ALC subtracts a common gain offset to these values. The ALC preserves any gain difference in dB as defined by these registers. At no time do the PGA gains exceed their initial values. The initial gain setting, therefore, also serves as a maximum value.

The limit detection mode bit in ALC Control Register 1 determines how the ALC responds to an ADC output that exceeds the set limits. If this bit is a 1, both channels must exceed the threshold before the gain is reduced. This mode can be used to prevent unnecessary gain reduction due to spurious noise on a single channel. If the limit detection mode bit is a 0, the gain is reduced when either channel exceeds the threshold.

No Recovery Mode

By default, there is no gain recovery. Once the gain has been reduced, it is not recovered until the ALC is reset, either by toggling the ALCEN bit in ALC Control Register 1 or by writing any value to ALC Control Register 3. The latter option is more efficient because it requires only one write operation to reset the ALC function. No recovery mode prevents volume modulation of the signal caused by adjusting the gain, which can create undesirable artifacts in the signal. The gain can be reduced but not recovered. Therefore, care should be taken that spurious signals do not interfere with the input signal because these might trigger a gain reduction unnecessarily.

Normal Recovery Mode

Normal recovery mode allows for the PGA gain to be recovered, provided that the input signal meets certain criteria. First, the ALC must not be in attack mode, that is, the PGA gain has been reduced sufficiently such that the input signal is below the level set by the attack threshold bits. Second, the output result from the ADC must be below the level set by the recovery threshold bits in the ALC control register. If both of these criteria are met, the gain is recovered by one step (0.5 dB). The gain is incrementally restored to its original value, assuming that the ADC output level is below the recovery threshold at intervals determined by the recovery time bits.

If the ADC output level exceeds the recovery threshold while the PGA gain is being restored, the PGA gain value is held and does not continue restoration until the ADC output level is again below the recovery threshold. Once the PGA gain is restored to its original value, it is not changed again unless the ADC output value exceeds the attack threshold and the ALC then enters attack mode. Care should be taken when using this mode to choose values for the attack and recovery thresholds that prevent excessive volume modulation caused by continuous gain adjustments.

Limited Recovery Mode

Limited recovery mode offers a compromise between no recovery and normal recovery modes. If the output level of the ADC exceeds the attack threshold, attack mode is initiated. When attack mode has reduced the PGA gain to suitable levels, the ALC attempts to recover the gain to its original level. If the ADC output level exceeds the level set by the recovery threshold bits, a counter is incremented (GAINCNTR). This counter is incremented at intervals equal to the recovery time selection, if the ADC has any excursion above the recovery threshold. If the counter reaches its maximum value, determined by the GAINCNTR bits in ALC Control Register 1, the PGA gain is deemed suitable and no further gain recovery is attempted. Whenever the ADC output level exceeds the attack threshold, attack mode is reinitiated and the counter is reset.

Rev. A | Page 16 of 60

ADAV803

ATTA

Selecting a Sample Rate

The output sample rate of the ADC is always ADC MCLK/256, as shown in

Figure 23. By default, the ADC modulator runs at ADC MCLK/2. When the ADC MCLK exceeds 12.288 MHz, the ADC modulator should be set to run at ADC MCLK/4. This is achieved by setting the AMC (ADC Modulator Clock) bit in the ADC Control Register 1. To compensate for the reduced modulator clock speed, a different set of filters is used in the decimator section, ensuring that the sample rate remains the same.

The AMC bit can also be used to boost the THD + N performance of the ADC at the expense of dynamic range. The improvement is typically 0.5 dB to 1.0 dB and works because

IS A RECOV ERY

MODE ENABL ED?

selecting the lower modulator rate reduces the amount of digital noise, improving THD + N, but also reduces the oversampling ratio, therefore reducing the dynamic range by a corresponding amount.

For best performance of the ADC, avoid using similar frequency clocks from separate sources in the ADAV803. For example, running the ADC from a 12.288 MHz clock connected to MCLKI and using the PLL to generate a separate 12.288 MHz clock for the DAC can reduce the performance of the ADC. This is due to the interaction of the clocks, which generate beat frequencies that can affect the charge on the switch capacitors of the analog inputs.

CK MODE

WAIT FOR SAMPLE

IS SAMPLE

GREATER THAN ATTACK

THRESHOL D?

YES

INCREASE GAIN BY 0.5dB

HAS GAIN BEEN

FULLY RESTORED?

YES

DECREASE GAIN BY 0.5dB

AND WAIT ATTACK TIME

LIMITED RECOVERY

WAIT FOR SAMPLE WAIT FOR SAMPLE

IS SAMPLE

ABOVE ATTACK

THRESHOLD?

HAS RECOVERY

TIME BEEN REACHED?

YES

ARE ALL

SAMPLES BELOW

RECOVERY

THRESHOLD?

YES NO

NO NO

INCREMENT

GAINCNTR

IS GAINCNTR

AT MAXIMUM?

YES

NORMAL RECO VERY

IS SAMPLE

ABOVE ATTACK

THRESHOL D?

NONO

HAS RECOVE RY

TIME BEEN REACHED?

YES

ARE ALL

SAMPLES BELOW

RECOVERY

THRESHOL D?

YES

INCREASE GAIN BY 0.5dB

WAIT RECOVERY TIME

HAS GAIN BEEN

FULLY RESTORED?

YESNO

04756-026

Figure 26. ALC Flow Diagram

Rev. A | Page 17 of 60

ADAV803

)

DAC SECTION

The ADAV803 has two DAC channels arranged as a stereo pair with single-ended analog outputs. Each channel has its own independently programmable attenuator, adjustable in 128 steps of 0.375 dB per step. The DAC can receive data from the playback or auxiliary input ports, the SRC, the ADC, or the DIR. Each analog output pin sits at a dc level of VREF, and swings 1.0 V rms for a 0 dB digital input signal. A single op amp third-order external low-pass filter is recommended to remove high frequency noise present on the output pins. Note that the use of op amps with low slew rate or low bandwidth can cause high frequency noise and tones to fold down into the audio band. Care should be taken in selecting these components.

The FILTD and VREF pins should be bypassed by external capacitors to AGND. The FILTD pin is used to reduce the noise of the internal DAC bias circuitry, thereby reducing the DAC output noise. The voltage at the VREF pin can be used to bias external op amps used to filter the output signals. For applications in which the VREF is required to drive external op amps, which might draw more than 50 μA or have dynamic load changes, extra buffering should be used to preserve the quality of the ADAV803 reference.

The digital input data source for the DAC can be selected from a number of available sources by programming the appropriate bits in the datapath control register. digital data source and the MCLK source for the DAC are selected. Each DAC has an independent volume register giving 256 steps of control, with each step giving approximately

0.375 dB of attenuation. Note that the DACs are muted by default to prevent unwanted pops, clicks, and other noises from appearing on the outputs while the ADAV803 is being configured. Each DAC also has a peak-level register that records the peak value of the digital audio data. Reading the register clears the peak.

Figure 27 shows how the

Selecting a Sample Rate

Correct operation of the DAC is dependent upon the data rate provided to the DAC, the master clock applied to the DAC, and the selected interpolation rate. By default, the DAC assumes that the MCLK rate is 256 times the sample rate, which requires an 8× oversampling rate. This combination is suitable for sample rates of up to 48 kHz.

For a 96 kHz data rate that has a 24.576 MHz MCLK (256 × f

)

associated with it, the DAC MCLK divider should be set to divide the MCLK by 2. This prevents the DAC engine from running too fast. To compensate for the reduced MCLK rate, the interpolator should be selected to operate in 4 × (DAC MCLK = 128 × f

). Similar combinations can be selected for

different sample rates.

PLL2 INTE RNAL

PLL1 INTE RNAL

MCLKI

REG 0x65 BITS[3:2]

DAC

INPUT

XIN

REG 0x76 BITS[7:5]

REG 0x63 BITS[5:3]

AUXILIARY IN

PLAYBACK

DIR

ADC

04756-027

DIR PLL( 256 × f

DIR PLL( 512 × f

MCLK

DIVIDER

DAC

MCLK

DAC

Figure 27. Clock and Datapath Control on the DAC

PEAK

DETECTOR

VOLUME/MUTE

CONTROL

ZERO DETECT

FROM DAC DATA PATH MULTIPLEXER

04756-028

ANALOG

OUTPUT

DAC

MULTI-BIT

Σ-Δ

MODULATOR

TO CONT ROL

REGISTERS

INTERPOLATOR

TO ZERO FLAG PINS

Figure 28. DAC Block Diagram

Rev. A | Page 18 of 60

+ 42 hidden pages

ANALOG DEVICES ADAV803 Service Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TEST CONDITIONS

ADAV803 SPECIFICATIONS

TIMING SPECIFICATIONS

TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

ADC SECTION

Programmable Gain Amplifier (PGA)

Analog Σ-Δ Modulator

Automatic Level Control (ALC)

Attack Mode

No Recovery Mode

Normal Recovery Mode

Limited Recovery Mode

Selecting a Sample Rate

DAC SECTION

Selecting a Sample Rate