Analog Devices ADAV801 Datasheet

Audio Codec for Recordable DVD

FEATURES

Stereo analog-to-digital converter (ADC)

Supports 48/96 kHz sample rates 102 dB dynamic range Single-ended input Automatic level control

Stereo digital-to-analog converter (DAC)

Supports 32/44.1/48/96/192 kHz sample rates 101 dB dynamic range

Single-ended output Asynchronous operation of ADC and DAC Stereo sample rate converter (SRC)

Input/output range: 8 kHz to 192 kHz

140 dB dynamic range Digital interfaces

Record

Playback

Auxiliary record

Auxiliary playback S/PDIF (IEC60958) input and output

Digital interface receiver (DIR)

Digital interface transmitter (DIT) PLL-based audio MCLK generators Generates required DVDR system MCLKs Device control via SPI®-compatible serial port 64-lead LQFP package

PRODUCT OVERVIEW

The ADAV801 is a stereo audio codec intended for applications such as DVD or CD recorders that require high performance and flexible, cost-effective playback and record functionality. The ADAV801 features Analog Devices’ proprietary, high performance converter cores to provide record (ADC), playback (DAC), and format conversion (SRC) on a single chip. The ADAV801 record channel features variable input gain to allow for adjustment of recorded input levels and automatic level control, followed by a high performance stereo ADC whose digital output is sent to the record interface. The record channel also features level detectors that can be used in feedback loops to adjust input levels for optimum recording. The playback channel features a high performance stereo DAC with independent digital volume control.

ADAV801

FUNCTIONAL BLOCK DIAGRAM

COUT

CIN

CCLK

CONTROL

REGISTERS

RECORD

DATA

OUTPUT

AUX DATA

OUTPUT

CLATCH

OLRCLK OBCLK

OSDATA

OAUXLRCLK OAUXBCLK OAUXSDATA

DIT

DITOUT

ZEROL/INT ZEROR

MCLKO

SYSCLK1

PLL

PLAYBACK

DATA INPUT

IBCLK

ILRCLK

DIGITAL

INPUT/OUTPUT

SWITCHING MATRIX

(DATAPATH)

AUX DATA

INPUT

ISDATA

IAUXBCLK

IAUXSDATA

IAUXLRCLK

DIR

DIRIN

VINL VINR

VREF

VOUTL

VOUTR

FILTD

MCLKI

XOUT

XIN

ANALOG-TO-DIGITAL

CONVERTER

REFERENCE SRC

DIGITAL-TO-ANALOG

CONVERTER

ADAV801

SYSCLK3

SYSCLK2

Figure 1.

APPLICATIONS

DVD-recordable All formats CD-R/W

The sample rate converter (SRC) provides high performance sample rate conversion to allow inputs and outputs that require different sample rates to be matched. The SRC input can be selected from playback, auxiliary, DIR, or ADC (record). The SRC output can be applied to the playback DAC, both main and auxiliary record channels, and a DIT.

Operation of the ADAV801 is controlled via an SPI-compatible serial interface, which allows the programming of individual control register settings. The ADAV801 operates from a single analog 3.3 V power supply and a digital power supply of 3.3 V with optional digital interface range of 3.0 V to 3.6 V.

The part is housed in a 64-lead LQFP package and is characterized for operation over the commercial temperature range of

−40°C to +85°C.

04577-0-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Anal og Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

ADAV801

TABLE OF CONTENTS

Specifications..................................................................................... 3

PLL Section ................................................................................. 22

Test Conditions............................................................................. 3

ADAV801 Specifications ............................................................. 3

Timing Specifications .................................................................. 6

Temperature Range ...................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 11

Functional Description ..................................................................15

ADC Section ............................................................................... 15

DAC Section................................................................................ 18

Sample Rate Converter (SRC) Functional Overview ............ 19

REVISION HISTORY

7/04—Revision 0: Initial Version

SPDIF Transmitter and Receiver.............................................. 23

Serial Data Ports ......................................................................... 27

Interface Control ............................................................................ 30

SPI Interface ................................................................................ 30

Block Reads and Writes ............................................................. 30

Layout Considerations................................................................... 54

ADC ............................................................................................. 54

DAC.............................................................................................. 54

PLL ............................................................................................... 54

Reset and Power-Down Considerations ................................. 54

Outline Dimensions....................................................................... 55

Ordering Guide .......................................................................... 55

Rev. 0 | Page 2 of 56

ADAV801

SPECIFICATIONS

TEST CONDITIONS

Test conditions, unless otherwise noted.

Table 1.

Test Parameter Condition

Supply Voltage

Analog 3.3 V

Digital 3.3 V Ambient Temperature 25°C Master Clock (XIN) 12.288 MHz Measurement Bandwidth 20 Hz to 20 kHz Word Width (All Converters) 24 bits Load Capacitance on Digital Outputs 100 pF ADC Input Frequency 1007.8125 Hz at −1 dBFS DAC Output Frequency 960.9673 Hz at 0 dBFS Digital Input Slave Mode, I2S Justified Format Digital Output Slave Mode, I2S Justified Format

ADAV801 SPECIFICATIONS

Table 2.

Parameter Min Typ Max Unit Comments

PGA SECTION

Input Impedance 4 kΩ

Minimum Gain 0 dB

Maximum Gain 24 dB

Gain Step 0.5 dB REFERENCE SECTION

Absolute Voltage, V

V

Temperature Coefficient 80 ppm/°C

REF

ADC SECTION

Number of Channels 2

Resolution 24 Bits

Dynamic Range −60 dB input

Unweighted 99 dB fS = 48 kHz 98 dB fS = 96 kHz A-Weighted 98 102 dB fS = 48 kHz 101 dB fS = 96 kHz

Total Harmonic Distortion plus Noise

−88 dB fS = 48 kHz

−87 dB fS = 96 kHz

Analog Input

Input Range (± Full Scale) 1.0 V rms

DC Accuracy

Gain Error −1.5 −0.8 dB Interchannel Gain Mismatch 0.05 dB Gain Drift 1 mdB/°C

Offset −10 mV Crosstalk (EIAJ Method) −110 dB Volume Control Step Size (256 Steps) 0.39

REF

1.5 V

Input = −1.0 dBFS

% per step

Rev. 0 | Page 3 of 56

ADAV801

Parameter Min Typ Max Unit Comments

Maximum Volume Attenuation −48 dB Mute Attenuation

∞

Group Delay

fS = 48 kHz 910 µs fS = 96 kHz 460 µs

ADC LOW-PASS DIGITAL DECIMATION FILTER CHARACTERISTICS1

Pass-Band Frequency 22 kHz Sample rate: 48 kHz 44 kHz Sample rate: 96 kHz Stop-Band Frequency 26 kHz Sample rate: 48 kHz

52 kHz Sample rate: 96 kHz

Stop-Band Attenuation 120 dB Sample rate: 48 kHz

120 dB Sample rate: 96 kHz

Pass-Band Ripple ±0.01 dB Sample rate: 48 kHz ±0.01 dB Sample rate: 96 kHz ADC HIGH-PASS DIGITAL FILTER CHARACTERISTICS

Cutoff Frequency 0.9 Hz fS = 48 kHz SRC SECTION

Resolution 24 Bits

Sample Rate 8 192 kHz XIN = 27 MHz

SRC MCLK 138 × f

33 MHz

S-MAX

Maximum Sample Rate Ratios

Upsampling 1:8 Downsampling 7.75:1

Dynamic Range 140

Total Harmonic Distortion plus Noise 120 dB

DAC SECTION

Number of Channels 2

Resolution 24

Dynamic Range 20 Hz to 20 kHz, −60 dB input

Unweighted 99

98

A-Weighted 97 101

100

Total Harmonic Distorton plus Noise

−91

−90

Analog Outputs

Output Range (± Full Scale) 1.0 Output Resistance 60 Common-Mode Output Voltage 1.5

DC Accuracy

Gain Error −2 −0.8 Interchannel Gain Mismatch 0.05 Gain Drift 1

DC Offset −30 Crosstalk (EIAJ Method) −110 Phase Deviation 0.05 Mute Attenuation −95.625

dB ADC outputs all zero codes

is the greater of the input

f

S-MAX

or output sample rate

/2, 1 kHz,

S

= 48 kHz

/2, 1 kHz,

S

= 48 kHz

= 44.1 kHz,

IN

= 44.1 kHz,

IN

+30

20 Hz to f

−60 dBFS input, f f

OUT

20 Hz to f 0 dBFS input, f f

OUT

Bits

dB fS = 48 kHz dB fS = 96 kHz dB fS = 48 kHz dB fS = 96 kHz Referenced to 1 V rms dB fS = 48 kHz dB fS = 96 kHz

V rms Ω V

dB dB mdB/°C mV dB Degrees dB

Rev. 0 | Page 4 of 56

ADAV801

Parameter Min Typ Max Unit Comments

Volume Control Step Size (256 Steps) 0.375 Group Delay

48 kHz 630 96 kHz 155 192 kHz 66

DAC LOW-PASS DIGITAL INTERPOLATION FILTER CHARACTERISTICS

Pass-Band Frequency 20 kHz Sample rate: 44.1 kHz 22 kHz Sample rate: 48 kHz 42 kHz Sample rate: 96 kHz Stop-Band Frequency 24 kHz Sample rate: 44.1 kHz 26 kHz Sample rate: 48 kHz 60 kHz Sample rate: 96 kHz Stop-Band Attenuation 70 dB Sample rate: 44.1 kHz 70 dB Sample rate: 48 kHz 70 dB Sample rate: 96 kHz

Pass-Band Ripple ±0.002 dB Sample rate: 44.1 kHz ±0.002 dB Sample rate: 48 kHz ±0.005 dB Sample rate: 96 kHz PLL SECTION

Master Clock Input Frequency 27/54 MHz

Generated System Clocks

MCLKO 27/54 MHz SYSCLK1 256 768 × f

SYSCLK2 256 768 × f

SYSCLK3 256 512 × f

Jitter

SYSCLK1 65 ps rms SYSCLK2 75 ps rms SYSCLK3 75 ps rms

DIR SECTION

Input Sample Frequency 27.2 200 kHz

Differential Input Voltage 200 mV DIT SECTION Output Sample Frequency 27.2 DIGITAL I/O

Input Voltage High, V

Input Voltage Low, V

IH

IL

Input Leakage, IIH @ VIH = 3.3 V

Input Leakage, IIL @ VIL = 0 V

2.0

Output Voltage High, VOH @ IOH = 0.4 mA 2.4 V

Output Voltage Low, VOL @ IOL = −2 mA

Input Capacitance POWER

Supplies

Voltage, AVDD 3.0 3.3 3.6 V Voltage, DVDD 3.0 3.3 3.6 V Voltage, ODVDD 3.0 3.3 3.6 V

µs µs µs

dB

S

256/384/512/768 × 32/44.1/ 48 kHz

S

256/384/512/768 × 32/44.1/ 48 kHz

S

256/512 × 32/44.1/48 kHz

200 kHz

DVDD V

0.8 V 10 µA 10 µA

0.4 V 15 pF

Rev. 0 | Page 5 of 56

ADAV801

Parameter Min Typ Max Unit Comments

Operating Current All supplies at 3.3 V

Analog Current 60 mA Digital Current 38 mA Digital Interface Current 13 mA DIRIN/DIROUT Current 5 mA PLL Current 18 mA

Power-Down Current

Analog Current 18 mA Digital Current 2.5 mA Digital Interface Current 700 µA DIRIN/DIROUT Current 3.5 mA PLL Current 900 µA

Power Supply Rejection

Signal at Analog Supply Pins −70 dB 1 kHz, 300 mV p-p

−70 dB 20 kHz, 300 mV p-p

1

Guaranteed by design.

TIMING SPECIFICATIONS

Timing specifications are guaranteed over the full temperature and supply range.

Table 3.

Parameter Min Typ Max Unit Comments

MASTER CLOCK AND RESET

f

MCLK

f

XIN

t

RESET

SPI PORT

t

CCH

t

CCL

t

CIS

t

CIH

t

CLS

t

CLH

t

COE

t

COD

t

COTS

SERIAL PORTS

1

Slave Mode

t

SBH

t

SBL

f

SBF

t

SLS

t

SLH

t

SDS

t

SDH

t

SDD

MCLKI Frequency 12.288 54 MHz XIN Frequency 27.0 54 MHz RESET Low

20 ns

CCLK High 40 ns CCLK Low 40 ns CIN Setup 10 ns To CCLK rising edge CIN Hold 10 ns From CCLK rising edge CLATCH Setup 10 ns To CCLK rising edge CLATCH Hold 10 ns From CCLK rising edge COUT Enable 15 ns From CLATCH falling edge COUT Delay 20 ns From CCLK falling edge COUT Three-State 25 ns From CLATCH rising edge

xBCLK High 40 ns xBCLK Low 40 ns xBCLK Frequency 64 × fS xLRCLK Setup 10 ns To xBCLK rising edge xLRCLK Hold 10 ns From xBCLK rising edge xSDATA Setup 10 ns To xBCLK rising edge xSDATA Hold 10 ns From xBCLK rising edge xSDATA Delay 10 ns From xBCLK falling edge

RESET low, no MCLK

Rev. 0 | Page 6 of 56

ADAV801

Parameter Min Typ Max Unit Comments

Master Mode

t

MLD

t

MDD

t

MDS

t

MDH

1

The prefix x refers to I-, O-, IAUX-, or OAUX- for the full pin name.

TEMPERATURE RANGE

Table 4.

Min Typ Max Unit

Specifications Guaranteed 25 °C Functionality Guaranteed −40 +85 °C Storage −65 +150 °C

xLRCLK Delay 5 ns From xBCLK falling edge xSDATA Delay 10 ns From xBCLK falling edge xSDATA Setup 10 ns From xBCLK rising edge xSDATA Hold 10 ns From xBCLK rising edge

Rev. 0 | Page 7 of 56

ADAV801

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

DVDD to DGND and ODVDD to

DGND AVDD to AGND 0 V to 4.6 V Digital Inputs DGND − 0.3 V to DVDD + 0.3 V Analog Inputs AGND − 0.3 V to AVDD + 0.3 V AGND to DGND −0.3 V to +0.3 V Reference Voltage Indefinite short circuit to ground Soldering (10 s) 300°C

0 V to 4.6 V

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. 0 | Page 8 of 56

ADAV801

Z

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NC

AGND

AVDD

VOUTLNCVOUTR

48

ADVDD

47

ADGND

46

PLL_LF2

45

PLL_LF1

44

PLL_GND

43

PLL_VDD

42

DGND

41

SYSCLK1

40

SYSCLK2

39

SYSCLK3

38

XIN

37

XOUT

36

MCLKO

35

MCLKI

34

DVDD

33

DGND

VINR

VINL AGND AVDD

DIR_LF DIR_GND DIR_VDD

RESET

CLATCH

CIN CCLK COUT

EROL/INT

ZEROR

DVDD DGND

CAPLN

CAPLP

AGND

PIN 1 INDICATOR

CAPRP

64 63 62 61 60 59 58

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

17 18 19 20 21 22 23 24

CAPRN

AVDD

AGND

VREF

AGND

FILTD

57 56 55 54 53 52 51 50 49

ADAV801

TOP VIEW

(Not to Scale)

25 26 27 31302928 32

OBCLK

OLRCLK

OSDATA

DIRIN

ODVDD

ODGND

DITOUT

OAUXLRCLK

OAUXBCLK

OAUXSDATA

IAUXBCLK

IAUXLRCLK

IAUXSDATA

04577-0-002

NC = NO CONNECT

IBCLK

ILRCLK

ISDATA

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic I/O Description

1 VINR I Analog Audio Input, Right Channel. 2 VINL I Analog Audio Input, Left Channel. 3 AGND Analog Ground. 4 AVDD Analog Voltage Supply. 5 DIR_LF DIR Phase-Locked Loop (PLL) Filter Pin. 6 DIR_GND Supply Ground for DIR Analog Section. This pin should be connected to AGND. 7 DIR_VDD Supply for DIR Analog Section. This pin should be connected to AVDD. 8

RESET

I Asychronous Reset Input (Active Low). 9 CLATCH I Chip Select (Control Latch) Pin of SPI-Compatible Control Interface. 10 CIN I Data Input of SPI-Compatible Control Interface. 11 CCLK I Clock Input of SPI-Compatible Control Interface. 12 COUT O Data Output of SPI-Compatible Control Interface. 13 ZEROL/INT O

Left Channel (Output) Zero Flag or Interrupt (Output) Flag. The function of this pin is determined

by the INTRPT pin in DAC Control Register 4. 14 ZEROR O Right Channel (Output) Zero Flag. 15 DVDD Digital Voltage Supply. 16 DGND Digital Ground. 17 ILRCLK I/O Sampling Clock (LRCLK) of Playback Digital Input Port. 18 IBCLK I/O Serial Clock (BCLK) of Playback Digital Input Port. 19 ISDATA I Data Input of Playback Digital Input Port. 20 OLRCLK I/O Sampling Clock (LRCLK) of Record Digital Output Port. 21 OBCLK I/O Serial Clock (BCLK) of Record Digital Output Port. 22 OSDATA O Data Output of Record Digital Output Port. 23 DIRIN I Input to Digital Input Receiver (S/PDIF). 24 ODVDD Interface Digital Voltage Supply. 25 ODGND Interface Digital Ground. 26 DITOUT O S/PDIF Output from DIT. 27 OAUXLRCLK I/O Sampling Clock (LRCLK) of Auxiliary Digital Output Port.

Rev. 0 | Page 9 of 56

ADAV801

Pin No. Mnemonic I/O Description

28 OAUXBCLK I/O Serial Clock (BCLK) of Auxiliary Digital Output Port. 29 OAUXSDATA O Data Output of Auxiliary Digital Output Port. 30 IAUXLRCLK I/O Sampling Clock (LRCLK) of Auxiliary Digital Input Port. 31 IAUXBCLK I/O Serial (BCLK) of Auxiliary Digital Input Port. 32 IAUXSDATA I Data Input of Auxiliary Digital Input Port. 33 DGND Digital Ground. 34 DVDD Digital Supply Voltage. 35 MCLKI I External MCLK Input. 36 MCLKO O Oscillator Output. 37 XOUT I Crystal Input. 38 XIN I Crystal or External MCLK Input. 39 SYSCLK3 O System Clock 3 (from PLL2). 40 SYSCLK2 O System Clock 2 (from PLL2). 41 SYSCLK1 O System Clock 1 (from PLL1). 42 DGND Digital Ground. 43 PLL_VDD Supply for PLL Analog Section. This pin should be connected to AVDD. 44 PLL_GND Ground for PLL Analog Section. This pin should be connected to AGND. 45 PLL_LF1 Loop Filter for PLL1. 46 PLL_LF2 Loop Filter for PLL2. 47 ADGND Analog Ground (Mixed Signal). This pin should be connected to AGND. 48 ADVDD Analog Voltage Supply (Mixed Signal). This pin should be connected to AVDD. 49 VOUTR O Right Channel Analog Output. 50 NC No Connect. 51 VOUTL O Left Channel Analog Output. 52 NC No Connect. 53 AVDD Analog Voltage Supply. 54 AGND Analog Ground. 55 FILTD Output DAC Reference Decoupling. 56 AGND Analog Ground. 57 VREF Voltage Reference Voltage. 58 AGND Analog Ground. 59 AVDD Analog Voltage Supply. 60 CAPRN ADC Modulator Input Filter Capacitor (Right Channel, Negative). 61 CAPRP ADC Modulator Input Filter Capacitor (Right Channel, Positive). 62 AGND Analog Ground. 63 CAPLP ADC Modulator Input Filter Capacitor (Left Channel, Positive). 64 CAPLN ADC Modulator Input Filter Capacitor (Left Channel, Negative).

Rev. 0 | Page 10 of 56

ADAV801

TYPICAL PERFORMANCE CHARACTERISTICS

0

–50

MAGNITUDE (dB)

–100

–150

0 0.5 1.0 1.5 2.0

FREQUENCY (Normalized to fS)

Figure 3. ADC Composite Filter Response

5

0

–5

–10

–15

MAGNITUDE (dB)

–20

–25

–30

0 5 10 15 20

FREQUENCY (Hz)

Figure 4. ADC High-Pass Filter Response, fS = 48 kHz

5

04577-0-037

04577-0-038

–50

MAGNITUDE (dB)

–100

–150

0 96 192 288 384

FREQUENCY (kHz)

Figure 6. DAC Composite Filter Response, 48 kHz

0

–50

MAGNITUDE (dB)

–100

–150

02412 36 48

FREQUENCY (kHz)

Figure 7. DAC Pass-Band Filter Response, 48 kHz

0.06

04577-0-040

04577-0-041

0

–5

–10

–15

MAGNITUDE (dB)

–20

–25

–30

0 5 10 15 20

Figure 5. ADC High-Pass Filter Response, f

FREQUENCY (Hz)

= 96 kHz

S

04577-0-039

Rev. 0 | Page 11 of 56

0.04

0.02

0.00

MAGNITUDE (dB)

–0.02

–0.04

–0.06

0 8 16 24

FREQUENCY (kHz)

Figure 8. DAC Filter Ripple, 48 kHz

04577-0-042

ADAV801

0

–50

0

–50

–100

MAGNITUDE (dB)

–100

–150

0 192 384 576 768

FREQUENCY (kHz)

Figure 9. DAC Composite Filter Response, 96 kHz

0

–50

MAGNITUDE (dB)

–100

–150

0 2448729

FREQUENCY (kHz)

Figure 10. DAC Pass-Band Filter Response, 96 kHz

0.10

0.05

0.00

MAGNITUDE (dB)

–0.05

–0.10

0 2448729

FREQUENCY (kHz)

Figure 11. DAC Filter Ripple, 96 kHz

04577-0-043

04577-0-044

6

04577-0-045

6

MAGNITUDE (dB)

–150

–200

0 384 768 1152 1536

FREQUENCY (kHz)

Figure 12. DAC Composite Filter Response, 192 kHz

0

–2

–4

–6

MAGNITUDE (dB)

–8

–10

48 64 80 96

Figure 2 kHz

13. DAC Pass-Band Filter Response, 19

FREQUENCY (kHz)

0.50

0.40

0.30

0.20

0.10

0.00

–0.10

MAGNITUDE (dB)

–0.20 –0.30

–0.40

–0.50

0 8 16 32 64

FREQUENCY (kHz)

Figure 14. DAC Fil r Ripple, 192 kHz te

04577-0-046

04577-0-047

04577-0-048

Rev. 0 | Page 12 of 56

ADAV801

–20

–40

0

DNR = 102dB (A-Weighted)

–20

–40

0

THD+N = 95dB

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 2 4 6 8 101214161820

Fig

ure 15. DAC Dynamic Range, f

FREQUENCY (kHz)

= 48 k

S

Hz

0

–20

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

02468101214161820

FREQUENCY (kHz)

Figure 16. DAC THD + N, f

THD+N = 96dB

= 48 kHz

S

0

–20

–40

DNR = 102dB (A-Weighted)

04577-0-049

04577-0-050

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 5 10 15 20 25 30 35 40 45 48

Figure 18. DAC THD + N, f

FREQUENCY (kHz)

= 96 kHz

S

0

–20

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 5 10 15 20

Figure 19. ADC Dynam c Range, f

FREQUENCY (kHz)

i

DNR = 102dB (A-Weighted)

= 48 kHz

S

0

–20

–40

THD+N = 92dB

= –3dB)

(V

IN

04577-0-052

04577-0-053

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 5 10 15 20 25 30 35 40 45 48

Figure 17. DAC Dynamic Range, f

FREQUENCY (kHz)

= 96 kHz

S

04577-0-051

Rev. 0 | Page 13 of 56

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 5 10 15 20

Figure 20. DAC THD + N, f

FREQUENCY (kHz)

= 48 kHz

S

04577-0-054

ADAV801

0

–20

–40

DNR = 102dB (A-Weighted)

–20

–40

0

TH(VD+N = 92dB

= –3dB)

IN

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 8 16 24 32 40 48

Figure 21. ADC Dynamic Range, f

FREQUENCY (kHz)

= 96 kHz

S

04577-0-055

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

0 8 16 24 32 40 48

Figure 22. ADC THD + N, f

FREQUENCY (kHz)

= 96 kHz

S

04577-0-056

Rev. 0 | Page 14 of 56

ADAV801

Ω

A

K

FUNCTIONAL DESCRIP

TION

ADC SECTION

The ADAV801’s ADC section is implemented using a secondorder multibit (5 bits) Σ-∆ modulator. The modulator is sampled at either half of the ADC MCLK rate (modulator clo = 128 × f clock = 64 × f followed by a cascade of three half-band FIR filters. The Sin decimates by a factor of 16 at 48 kHz 96 kHz. Each of the half-band filters decimates by a factor of 2.

Figure 23 shows the details of the ADC section. The ADC can be clocked by a number of different clock sources to control t sample rate. MCLK selection for the ADC is set by Internal Clocking Control Register 1 (Address 0x76). The ADC provide an output word of up to 24 bits in resolution in twos complement format. The output word can be routed to ei output ports, the sample rate converter, or the SPDIF digital transmitter.

) or one-quarter of the ADC MCLK rate (modulator

S

). The digital decimator consists of a Sinc^5 filter

S

and by a factor of 8 at

ther the

)

S

PLL2 INTERNAL

PLL1 INTERNAL

MCLKI

DIR PLL (256 × f

DIR PLL (512 × f

XIN

REG 0x76 BITS 4–2

c

ck

he

Programmable Gain Amplifier (PGA)

The input of the record channel features a PGA that converts the single-ended signal to a differential signal, which is applied to the analog Σ-Δ modulator of the ADC. The PGA can be programmed to amplify a signal by up to 24 dB in 0.5 dB

s

increments. Figure 24 shows the structure of the PGA circuit.

4kΩ TO 64k

EXTERNAL

4kΩ

VREF

8kΩ

CAPACITOR

8kΩ

(1nF NPO)

125Ω

EXTERNAL

CAPACITOR

(1nF NPO)

CAPxN

EXTERNAL

CAPACITOR

(1nF NPO)

CAPxP

Figure 24. PGA Block Diagram

TO

MODULATOR

04577-0-004

Analog Σ-∆ Modulator

The ADC features a second-order, multibit, Σ-Δ modulator. The input features two integrators in cascade followed by a flash converter. This multibit output is directed to a scrambler, followed by a DAC for loop feedback. The flash ADC outp also converted from thermometer coding to binary codin input as a 5-bit word to the decimator. F

igure 25 shows the

ut is

g for

ADC block diagram.

ADC MCLK

DIVIDER

MCLK

ADC

REG 0x6F BITS 1–0

04577-0-003

Figure 23. Clock Path Control on the ADC

MULTIBIT

Σ–∆

MODULATOR

DC MCL

AMC

(REG 0X63

BIT-7)

÷2 ÷4

MODULATOR

CLOCK

(6.144MHz MAX)

SINC^5

DECIMATOR

384kHz 768kHz

HALF-BAND

FILTER

The ADC also features independent digital volume control for the left and right channels. The volume control consists of 256 linear steps, with each step reducing the digital output codes by 0.39%. Each channel also has a peak detector that records the peak level of the input signal. The peak detector register is cleared by reading it.

PEAK

DETECT

HALF-BAND

FILTER

48kHz 96kHz

04577-0-005

VOLUME

ONTROL

C

192kHz 384kHz

Diagram Figure 25. A DC Block

HPF

SINC

COMPENSATION

96kHz

192kHz

Rev. 0 | Page 15 of 56

ADAV801

Automatic Level Control (

The ADC record channel features a programmable automatic level control block. This block monitors the level of the ADC output signal and automatically reduces the gain, if the signal the input pins causes the ADC output to exceed a preset limit. This function can be useful to maximize the signal dynamic range when the input level is not well defined. The PGA can b used to amplify the unknown signal, and the ALC reduces the gain until the ADC output is within the preset limits. This results in m

Because the ALC block monitors the output of the ADC, the volume control function should not be used. The ADC v control scales the results from the ADC, and any distortion caused by the input signal exceeding the input range of the ADC is still present at the output of the ADC, but scaled by a value determined by the volume control register.

The ALC block has two functions, attack mode and recover mode. Recovery mode consists of three settings: no recovery, normal recovery, and limited recovery. These modes are discussed in the following sections. Figure 26 is a flow diagram of the ALC block. When the ALC has been enabled, any changes made to the PGA or ALC settings are ignored. To change the functionality of the ALC, it must first be disabled. The settings can then be changed and the ALC re-enabled.

aximum front end gain.

Attack Mode

When the absolute value of the ADC output exceeds the level set by the attack threshold bits in ALC Control Register 2, attack mode is initiated. The PGA gain for both channels is reduced by one step (0.5 dB). The ALC then waits for a time determined by the attack timer bits before sampling the ADC output value again. If the ADC output is still above the threshold, the PGA gain is reduced by a further step. This procedure continues until the ADC output is below the limit set by the attack threshold bits. The initial gains of the PGAs are defined by the ADC left PGA gain register and the ADC right PGA gain register, and they can have different values. The ALC subtracts a common gain offset to these values. The ALC preserves any gain difference in dB as defined by these registers. At no time do the PGA gains exceed their initial values. The initial gain setting, therefore, also serves as a maximum value.

The limit detection mode bit in ALC Control Register 1 determines how the ALC responds to an ADC output that exceeds the set limits. If this bit is a 1, then both channels must exceed the threshold before the gain is reduced. This mode can be used to prevent unnecessary gain reduction due to spurious noise on a single channel. If the limit detection mode bit is a 0, the gain is reduced when either channel exceeds the threshold.

ALC)

at

e

olume

y

No Recovery Mode

By default, there is no gain recovery. Once the gain has bee reduced, it by toggling the ALCEN bit in ALC Control Register 1 o writing any value to ALC Control Register 3. The latter option more efficient, because it requires only one write operation to reset the ALC function. No recovery mode prevents volume modulation of the signal caused by adjusting the gain, which can create undesirable artifacts in the signal. The gain can be reduced but not recovered. Therefore, care should be taken that spurious signals do not interfere with the input signal, because these might trigger a ga

ormal Recovery Mode

N

Normal recovery mode allows for the PGA gain to be recovered, provided that the input signal meets certain criteria. First, the ALC must not be in attack mode, that is, the PGA gain has been reduced set by the attack threshold bits. Second, the output result from the ADC must be below the level set by the recovery threshold bits in the ALC control register. If both of these criteria are met, the gain is recovered by one step (0.5 dB). The gain is incrementally restored to its original value, assuming that the ADC output level is below the recovery threshold at intervals determined by the recovery time bits.

If the ADC output level exceeds the recovery threshold while the PGA gain is being restored, the PGA gain value is held and does not continue restoration until the ADC output level is again below the recovery threshold. Once the PGA gain is restored to its original value, it is not changed again unless the ADC output value exceeds the attack threshold and the ALC then enters attack mode. Care should be taken when using this mode to choose values for the attack and recovery thresholds that prevent excessive volume modulation caused by continuous gain adjustments.

is not recovered until the ALC has been reset, either

in reduction unnecessarily.

sufficiently such that the input signal is below the level

n

r by

is

Limited Recovery Mode

Limited recovery mode offers a compromise between no recovery and normal recovery modes. If the output level of the ADC exceeds the attack threshold, then attack mode is initiated. When attack mode has reduced the PGA gain to suitable levels, the ALC attempts to recover the gain to its original level. If the ADC output level exceeds the level set by the recovery threshold bits, a counter is incremented (GAINCNTR). This counter is incremented at intervals equal to the recovery time selection, if the ADC has any excursion above the recovery threshold. If the counter reaches its maximum value, determined by the GAINCNTR bits in ALC Control Register 1, the PGA gain is deemed suitable and no further gain recovery is attempted. Whenever the ADC output level exceeds the attack threshold, attack mode is reinitiated and the counter is reset.

Rev. 0 | Page 16 of 56

ADAV801

Selecting a Samp

le Rate

The output sample rate of the ADC is always ADC MCLK/256, as shown in Figure 23. By default, the ADC modulator runs at ADC MCLK/2. When the ADC MCLK exceeds 12.288 MHz, the ADC modulator should be set to run at ADC MCLK/4. This is achieved by setting the AMC (ADC Modulator Clock) bit in the ADC Control Register 1. To compensate for the reduced modulator clock speed, a different set of filters are used in the decimator section ensuring that the sample rate remains the same.

The AMC bit can also be used to boost the THD + N perform

ance of the ADC at the expense of dynamic range. The improvement is typically 0.5 dB to 1.0 dB and works, b selecting the lower modulator rate reduces the amount of dig

ecause

NO

IS A RECOVERY

MODE ENABLED?

ital

noise, improving THD + N, b therefore reducing the dynamic range by a corresponding amount.

For best performance of the ADC, avoid using similar frequency clocks from separate sources in the ADAV801. For example, running the ADC from a 12.288 MHz clock conne to MCLKI and using the PLL t clock for the DAC can reduce the performance of the ADC. This is due to the interaction of the clocks, which generate b frequencies that can affect the charge on the switch capacitors of the analog inputs.

ATTACK MODE

WAIT FOR SAMPLE

NO

IS SAMPLE

GREATER THAN ATTACK

THRESHOLD?

ut reduces the oversampling ratio,

cted

o generate a separate 12.288 MHz

eat

YES

INCREASE GAIN BY 0.5dB

HAS GAIN BEEN

FULLY RESTORED?

NO

YES

YESYES

DECREASE GAIN BY 0.5dB

AND WAIT ATTACK TIME

LIMITED RECOVERY

WAIT FOR SAMPLE WAIT FOR SAMPLE

IS SAMPLE

ABOVE ATTACK

THRESHOLD?

HAS RECOVERY

TIME BEEN

REACHED?

YES

ARE ALL

SAMPLES BELOW

RECOVERY

THRESHOLD?

YES NO

NO NO

NO

INCREMENT

GAINCNTR

IS GAINCNTR

AT MAXIMUM?

NORMAL RECOVERY

IS

SAMPLE

ABO

VE ATTACK

THRESHOLD?

NONO

HAS RECOVERY

TIME BEEN REACHED?

YES

ARE ALL

SAMPLES BELOW

RECOVERY

THRESHOLD?

YES

INCREASE GAIN BY 0.5dB

WAIT RECOVERY TIME

HAS GAIN BEEN

FULLY RESTORED?

NO

YESNO

Figure 26. ALC Flow Diagram

Rev. 0 | Page 17 of 56

04577-0-006