Audio Processor for Advanced TV with
Sound IF Demodulator and Stereo Decoder
FEATURES
Sound IF (SIF) processor
SIF demodulator and broadcast stereo decoder
NICAM (BG, DK, I, L), A2 (BG, DK, M), BTSC (M, N), EIAJ (M)
Automatic sound IF standard detection
Fully programmable 28-bit audio processor for enhanced
ATV sound—default TV audio flow loaded on reset
Implements Analog Devices and third-party branded audio
algorithms
Adjustable digital delay line for audio/video
Synchronization for up to 200 ms stereo delay
High performance 24-bit ADC and DAC
94 dB DNR performance on DAC channels
95 dB DNR performance on ADC channels
Dual headphone outputs with integrated amplifiers
High performance pulse-width modulation (PWM) digital
outputs
Multichannel digital baseband I/O
4 stereo synchronous digital I
One 6-channel sample rate converter (SRC) and one
stereo SRC supporting input sample rates from
5 kHz to 50 kHz
One stereo synchronous digital I
S/PDIF output with S/PDIF input mux capability
2
Fast I
C control
Operates from 3.3 V (analog), 1.8 V (digital core), and 3.3 V
(digital interface)
Available in 80-lead LQFP
APPLICATIONS
General-purpose consumer audio postprocessing
Home audio
DVD recorders
Home theater in a box (HTIB) systems and DVD receivers
Audio processing subsystems for DTV-ready TVs
Analog broadcast capability for iDTVs
2
S input channels
2
S output
ADAV4622
PRODUCT OVERVIEW
The ADAV4622 is an enhanced audio processor targeting
advanced TV applications with full support for digital and
analog baseband audio as well as multistandard broadcast SIF
demodulation and decoding.
The audio processor, by default, loads a dedicated TV audio
flow that incorporates full matrix switching (any input to any
output), automatic volume control that compensates for volume
changes during advertisements or when switching channels,
dynamic bass, a multiband equalizer, and up to 200 ms of stereo
delay memory for audio-video synchronization.
Alternatively, Analog Devices, Inc., offers an award-winning
graphical programming tool (SigmaStudio™) that allows custom
flows to be quickly developed and evaluated. This allows the
creation of customer-specific audio flows, including use of the
Analog Devices library of third-party algorithms.
The analog I/O integrates Analog Devices proprietary
continuous-time, multibit Σ-Δ architecture to bring a higher
level of performance to ATV systems, required by third-party
algorithm providers to meet system branding certification. The
analog input is provided by 95 dB dynamic range (DNR) ADCs,
and analog output is provided by 94 dB DNR DACs.
The main speaker outputs can be supplied as a digitally
modulated PWM stream to support digital amplifiers.
The ADAV4622 includes multichannel digital inputs and
outputs. In addition, digital input channels can be routed
through integrated sample rate converters (SRC), which are
capable of supporting any arbitrary sample rate from 5 kHz
to 50 kHz.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of p atents or other
rights of third parties that may result from its use. Specifications subject to chan ge without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved.
ADAV4622
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Product Overview ............................................................................. 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications ..................................................................................... 4
Performance Parameters ............................................................. 4
Timing Specifications .................................................................. 9
Timing Diagrams ........................................................................ 10
Absolute Maximum Ratings .......................................................... 12
Thermal Resistance .................................................................... 12
Thermal Conditions ................................................................... 12
ESD Caution ................................................................................ 12
Pin Configuration and Function Descriptions ........................... 13
Typical Performance Characteristics ........................................... 16
Terminology .................................................................................... 18
Pin Functions .................................................................................. 19
SDIN0, SDIN1, SDIN2, and SDIN3/SPDIF_IN0 ................... 19
LRCLK0, BCLK0, LRCLK1, BCLK1, LRCLK2, and BCLK2 19
SDO0/AD0 .................................................................................. 19
SPDIF_OUT (SDO1) ................................................................. 19
MCLKI/XIN ................................................................................ 19
XOUT ........................................................................................... 19
MCLK_OUT ............................................................................... 19
SDA ............................................................................................... 19
SCL ............................................................................................... 20
MUTE
.......................................................................................... 20
.......................................................................................... 20
RESET
AUXIN1L, AUXIN2L, AUXIN1R, and AUXIN2R ................ 20
AUXOUT1L, AUXOUT2L, AUXOUT3L, AUXOUT4L,
AUXOUT1R, AUXOUT2R, AUXOUT3R, and AUXOUT4R
....................................................................................................... 20
HPOUT1L, HPOUT2L, HPOUT1R, and HPOUT2R .......... 20
PLL_LF ......................................................................................... 20
REVISION HISTORY
7/09—Rev. A to Rev. B
Added Advantiv Logo ...................................................................... 1
Change to PWM Outputs Section ................................................ 24
Rev. B | Page 2 of 28
VREF ............................................................................................ 20
FILTA and FILTD ....................................................................... 20
PWM1A, PWM1B, PWM2A, PWM2B, PWM3A, PWM3B,
PWM4A, and PWM4B .............................................................. 20
PWM_READY ........................................................................... 20
AVDD .......................................................................................... 20
DVDD .......................................................................................... 20
ODVDD ....................................................................................... 20
DGND .......................................................................................... 20
AGND .......................................................................................... 20
ODGND ...................................................................................... 20
SIF_REFP, SIF_REFCM, and SIF_REFN ................................ 20
SIF_IN1 and SIF_IN2 ................................................................ 20
SIF_PGA_REF ............................................................................ 20
ISET .............................................................................................. 20
Functional Descriptions ................................................................ 21
SIF Processor ............................................................................... 21
Master Clock Oscillator ............................................................. 21
I2C Interface ................................................................................ 22
ADC Inputs ................................................................................. 22
I2S Digital Audio Inputs ............................................................ 22
DAC Voltage Outputs ................................................................ 23
PWM Outputs ............................................................................ 24
Headphone Outputs ................................................................... 24
I2S Digital Audio Outputs ......................................................... 24
S/PDIF Input/Output ................................................................. 25
Hardware Mute Control ............................................................ 25
Audio Processor ......................................................................... 25
Graphical Programming Environment ................................... 25
Application Layer ....................................................................... 25
Loading a Custom Audio Processing Flow ............................. 26
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
Change to Hardware Mute Control, Graphical Programming
Environment, and Application Layer Sections ........................... 25
Changes to Ordering Guide .......................................................... 28
11/08—Revision A: Initial Version
ADAV4622
FUNCTIONAL BLOCK DIAGRAM
SDO0/AD0
BCLK1
LRCLK1
SPDIF_IN0
SPDIF_IN1
SPDIF_IN2
SPDIF_IN3
SPDIF_IN4
SPDIF_IN5
SPDIF_IN6
SPDIF_OUT/SDO1
PWM1A
PWM1B
PWM2A
PWM2B
PWM3A
PWM3B
PWM4A
PWM4B
PWM_READY
AUXOUT4L
AUXOUT4R
HPOUT1L
HPOUT1R
AUXOUT1L
AUXOUT1R
AUXOUT2L
AUXOUT2R
HPOUT2L
HPOUT2R
AUXOUT3L
AUXOUT3R
07068-001
SIF_IN1
SIF_IN2
MCLK_OUT
MCLKI/XIN
XOUT
SCL
SDA
MUTE
BCLK2
LRCLK2
BCLK0
LRCLK0
SDIN0
SDIN1
SDIN2
SDIN3
AUXIN1L
AUXIN1R
AUXIN2L
AUXIN2R
BCLK1
LRCLK1
PLL
I2C INTERF ACE
AD0
ADAV4622
SIF PROCESSOR
SYSTEM
CLOCKS
2-CHANNEL SRC
ASYNCHRONOUS
DIGITAL INPUT
6-CHANNEL SRC
ASYNCHRONOUS
DIGITAL INPUT
SYNCHRONOUS
MULTICHANNEL
DIGITAL INPUTS
ADC
ADC
AUDIO
PROCESSOR
A-V
SYNCHRONOUS
DELAY
MEMORY
DIGITAL
OUTPUTS
S/PDIF I/O
PWM
DIGITAL
OUTPUT
DAC
DAC
DAC
DAC
Figure 1. ADAV4622 with PWM-Based Speaker Outputs
Rev. B | Page 3 of 28
ADAV4622
SPECIFICATIONS
AVDD = 3.3 V, DVDD = 1.8 V, ODVDD = 3.3 V, operating temperature = −40°C to +85°C, master clock = 24.576 MHz, measurement
bandwidth = 20 Hz to 20 kHz, ADC input signal = DAC output signal = 1 kHz, unless otherwise noted.
PERFORMANCE PARAMETERS
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
SIF ADC INPUT SECTION
Analog Input Frequency Range 10 MHz
Recommended Analog Input Level 90 ± 18 dB dBu FM, AGC in PGA priority mode
Maximum Analog Input Range 1.6 V p-p Default setting
Input Im pedance 12 kΩ PGA Gain = 0 dB
6 KΩ PGA Gain = 10 dB
2.3 kΩ PGA Gain = 20 dB
DC Bias Level 1.9 V
SIF Input Isolation 60 dB SIF_IN1 to SIF_ IN2
FM Limiting Sensitivity 32 dBu A2 (DK), Mono, deviation mode = 100%, fFM = 400 Hz,
31 dBu A2 (I), Mono, deviation mode = 100%, fFM = 400 Hz,
31 dBu A2 (BG), Mono, deviation mode = 100%, fFM = 400 Hz,
34 dBu BTSC (M, N), Mono, deviation mode = 100%,
28.5 dBu A2 (M), Mono, deviation mode = 100%, fFM = 400 Hz,
30 dBu EIAJ (M), Mono, deviation mode = 100%, fFM = 400 Hz,
FM Output Level at 25% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, V
53.6 % FS BTSC (M, N), Mono, V
56.3 % FS A2 (M), Mono, V
56.7 % FS EIAJ (M), Mono, V
FM Output Level at 50% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, V
53.6 % FS BTSC (M, N), Mono, V
56.3 % FS A2 (M), Mono, V
56.7 % FS EIAJ (M), Mono, V
FM Output Level at 100% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, V
53.6 % FS BTSC (M, N), Mono, V
56.3 % FS A2 (M), Mono, V
56.7 % FS EIAJ (M), Mono, V
FM Output Level at 200% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, V
53.6 % FS BTSC (M, N), Mono, V
56.3 % FS A2 (M), Mono, V
56.7 % FS EIAJ (M), Mono, V
Δf = 50 kHz, BW = 20 Hz to 15 kHz, rms detector
Δf = 50 kHz, BW = 20 Hz to 15 kHz, rms detector
Δf = 50 kHz, BW = 20 Hz to 15 kHz, rms detector
f
= 400 Hz, Δf = 25 kHz, BW = 20 Hz to 15 kHz,
FM
rms detector
Δf = 25 kHz, BW = 20 Hz to 15 kHz, rms detector
Δf = 25 kHz, BW = 20 Hz to 15 kHz, rms detector
= 100 mV, fFM = 400 Hz,
SIF
Δf = 12.5 kHz, rms detector
= 100 mV, fFM = 400 Hz,
SIF
Δf = 6.25 kHz, rms detector
= 100 mV, fFM = 400 Hz,
SIF
Δf = 6.25 kHz, rms detector
= 100 mV, fFM = 400 Hz,
SIF
Δf = 6.25 kHz, rms detector
= 100 mV, fFM = 400 Hz,
SIF
Δf = 25 kHz, rms detector
= 100 mV, fFM = 400 Hz,
SIF
Δf = 12.5 kHz, rms detector
= 100 mV, fFM = 400 Hz,
SIF
Δf = 12.5 kHz, rms detector
= 100 mV, fFM = 400 Hz,
SIF
Δf = 12.5 kHz, rms detector
= 100 mV, fFM = 400 Hz,
SIF
Δf = 50 kHz, rms detector
= 100 mV, fFM = 400 Hz,
SIF
Δf = 25 kHz, rms detector
= 100 mV, fFM = 400 Hz, Δf = 25 kHz,
SIF
rms detector
= 100 mV, fFM = 400 Hz, Δf = 25 kHz,
SIF
rms detector
=100 mV, fFM = 400 Hz,
SIF
Δf = 100 kHz, rms detector
= 100 mV, fFM = 400 Hz,
SIF
Δf = 50 kHz, rms detector
= 100 mV, fFM = 400 Hz, Δf = 50 kHz,
SIF
rms detector
= 100 mV, fFM = 400 Hz, Δf = 50 kHz,
SIF
rms detector
Rev. B | Page 4 of 28
ADAV4622
Parameter Min Typ Max Unit Test Conditions/Comments
FM Output Level at 400% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, V
Δf = 200 kHz, rms detector
53.6 % FS BTSC (M, N), Mono, V
Δf = 100 kHz, rms detector
56.4 % FS A2 (M), Mono, V
Δf = 100 kHz, rms detector
56.7 % FS EIAJ (M), Mono, V
rms detector
FM Output Level at 800% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, V
Δf = 400 kHz, rms detector
53.6 % FS BTSC (M, N), Mono, V
Δf = 200 kHz, rms detector
56.3 % FS A2 (M), Mono, V
Δf = 200 kHz, rms detector
56.7 % FS EIAJ (M), Mono, V
Δf = 200 kHz, rms detector
AM Rejec tion Rat io 69.5 dB A2 (DK), Mono, deviation mode = 100%, V
f
= 400 Hz, Δf = 27 kHz, fAM = 400 Hz, MODAM = 30%,
FM
BW = 20 Hz to 15 kHz, rms detector
70 dB A2 (I), Mono, deviation mode = 100%, V
= 400 Hz, Δf = 27 kHz, fAM = 400 Hz, MODAM = 30%,
f
FM
BW = 20 Hz to 15 kHz, rms detector
70 dB A2 (BG), Mono, deviation mode = 100%, V
= 400 Hz, Δf = 27 kHz, fAM = 400 Hz, MODAM = 30%,
f
FM
BW = 20 Hz to 15 kHz, rms detector
70.5 dB Mono (M), deviation mode = 100%, V
f
= 400 Hz, Δf = 13.5 kHz, fAM = 400 Hz, MODAM = 30%,
FM
BW = 20 Hz to 15 kHz, rms detector
AM Sensitivity 40 dBu Mono (L), fAM = 400 Hz, MOD = 30%, BW = 20 Hz to 15 kHz,
rms detector, (S + N)/N = 10 dB
BTSC (M) PERFORMANCE Measured at analog audio output, video = 75% color bar,
f
= 4.5 MHz, fFM = 1 kHz, Δf = 25 kHz (100%), deemphasis =
SC
75 μs, measuring BW = 20 Hz to 15 kHz with dBX NR
Dynamic Range
Stereo Channel 62 dB Stereo L or R (L = −R), 100%, 1 kHz
SAP Channel 68 dB SAP channel with Mono 100%, 1 kHz
Total Harmonic Distortion + Noise
Stereo Channel −46 dB Stereo L or R (L = −R), 100%, 1 kHz
SAP Channel −40 dB SAP 100%, 1 kHz
Frequency Response fFM = 20 Hz to 12 kHz
Stereo Channel +0.1/−0.7 dB Stereo L or R, 50%, (L = −R)
SAP Channel +2.5/−2.5 dB SAP 50%, Mono 100%, 1 kHz
Crosstalk
Stereo-to-SAP Channel −74 dB L or R 50%, 1 kHz
SAP-to-Stereo Channel −71 dB SAP 50%, 1 kHz
Stereo Separation dBX 30 dB L off, R 50%, 1 kHz
EIAJ (M) PERFORMANCE
Measured at analog audio output, video = 75% color bar,
f
= 4.5 MHz, fFM = 1 kHz, Δf = 25 kHz (100%),
SC
deemphasis = 75 μs, measuring BW = 20 Hz to 15 kHz
Dynamic Range
Stereo Channel 58 dB Stereo L or R, 100%, 1 kHz
Dual Channel 56 dB Dual channel with Mono 100%, 1 kHz
Total Harmonic Distortion + Noise
Stereo Channel −56 dB Stereo L or R, 100%, 1 kHz
Dual Channel −47 dB Dual 50%, 1 kHz
Frequency Response fFM = 20 Hz to 10 kHz
Stereo Channel +0.03/−0.53 dB Stereo L or R, 100%
Dual Channel +0.17/−1.4 dB Dual 100%, Mono 100%, 1 kHz
Crosstalk
Main-to-Dual Channel −75 dB Main 100%, 1 kHz
Dual-to-Main Channel −83 dB Dual 100%, 1 kHz
Stereo Separation 39 dB Stereo L or R, 100%, 1 kHz
= 100 mV, fFM = 400 Hz,
SIF
= 100 mV, fFM = 400 Hz,
SIF
= 100 mV, fFM = 400 Hz,
SIF
= 100 mV, fFM = 400 Hz, Δf = 100 kHz,
SIF
= 100 mV, fFM = 400 Hz,
SIF
= 100 mV, fFM = 400 Hz,
SIF
= 100 mV, fFM = 400 Hz,
SIF
= 100 mV, fFM = 400 Hz,
SIF
= 100 mV,
SIF
= 100 mV,
SIF
= 100 mV,
SIF
= 100 mV,
SIF
Rev. B | Page 5 of 28
ADAV4622
Parameter Min Typ Max Unit Test Conditions/Comments
A2 (M) PERFORMANCE
Dynamic Range 60 dB Mono 100%, 1 kHz
Total Harmonic Distortion + Noise −64 dB Mono 100%, 1 kHz
Frequency Response +0.4/−0.05 dB Mono 100%, fFM = 25 Hz to 15 kHz
Crosstalk (Dual) −88 dB Mono or dual off, 100%, 1 kHz
Channel Separation (Stereo) 66 dB Stereo L off, R 50%, 1 kHz
A2 (DK1/DK2/DK3) PERFORMANCE Measured at analog audio output, video = 75% color bar,
Dynamic Range 74 dB Mono 100%, 1 kHz
Total Harmonic Distortion + Noise −66 dB Mono 100%, 1 kHz
Frequency Response +0.1/−0.3 dB Mono 100%, fFM = 20 Hz to 15 kHz
Crosstalk (Dual) −88 dB Mono or dual off, 100%, 1 kHz
Channel Separation (Stereo) 77 dB Stereo L off, R 50%, 1 kHz
A2 (BG) PERFORMANCE Measured at analog audio output, video = 75% color bar,
Dynamic Range 74 dB Mono 100%, 1 kHz
Total Harmonic Distortion + Noise −61 dB Mono 100%, 1 kHz
Frequency Response +0.1/−0.3 dB Mono 100%, fFM = 25 Hz to 15 kHz
Crosstalk (Dual) −89 dB Mono or dual off, 100%, 1 kHz
Channel Separation (Stereo) 70 dB Stereo L off, R 50%, 1 kHz
NICAM (I) PERFORMANCE
Dynamic Range 72 dB Stereo L or R, 0 dB, 1 kHz
Total Harmonic Distortion + Noise −63 dB Stereo L or R, 0 dB, 1 kHz
Frequency Response −1.3/+0.07 dB Stereo L or R, 0 dB
Crosstalk −80 dB Mono or dual, 0 dB, 1 kHz
Stereo Separation 73 dB L or R, 0 dB, 1 kHz
Bit Error Rate 0 FM and NICAM nominal conditions
NICAM (BG, DK, L) PERFORMANCE Measured at analog audio output, video = 75% color bar,
Dynamic Range 72 dB Stereo L or R, 0 dB, 1 kHz
Total Harmonic Distortion + Noise −63 dB Stereo L or R, 0 dB, 1 kHz
Frequency Response −1.3/+0.07 dB Stereo L or R, 0 dB
Crosstalk −80 dB Mono or dual, 0 dB, 1 kHz
Stereo Separation 74 dB L or R, 0 dB, 1 kHz
Bit Error Rate 0 FM and NICAM nominal conditions
AM PERFORMANCE
Dynamic Range
RMS/FLAT 55 dB AM = 54% modulation
QP/CCIR 35 dB CCIR filter, AM = 54% modulation
Total Harmonic Distortion + Noise −49 dB AM = 54% modulation
Frequency Response +0.03/−1.2 dB AM = 54% modulation
REFERENCE SECTION
Absolute Voltage V
V
Temperature Coefficient 100 ppm/°C
REF
Measured at analog audio output, video = 75% color bar,
= 4.5 MHz, f
f
SC1
(100%), deemphasis = 75 μs, measuring BW = 20 Hz to
15 kHz
f
= 6.5 MHz, f
SC1
f
= 1 kHz, Δf = 50 kHz (100%), deemphasis = 50 μs,
FM
measuring BW = 20 Hz to 15 kHz
= 5.5 MHz, f
f
SC1
Δf = 50 kHz (100%), deemphasis = 50 μs,
measuring BW = 20 Hz to 15 kHz
Measured at analog audio output, video = 75% color bar,
1 kHz, unweighted, deemphasis = J17, measuring BW = 20
Hz to 15 kHz
1 kHz, unweighted, deemphasis = J17, measuring BW =
20 Hz to 15 kHz
Measured at analog audio output, 1 kHz,
AM carrier 6.5 MHz measuring BW = 20 Hz to 15 kHz
1.53 V
REF
= 4.724 MHz, fFM = 1 kHz, Δf = 25 kHz
SC2
= 6.742 MHz, (DK2 worst case),
SC2
= 5.742 MHz, fFM = 1 kHz,
SC2
Rev. B | Page 6 of 28
ADAV4622
Parameter Min Typ Max Unit Test Conditions/Comments
ADC SECTION
Number of Channels 4 Two stereo channels
Full-Scale Input Level 100 μA rms
Resolution 24 Bits
Dynamic Range (Stereo Channel)
Total Harmonic Distortion + Noise (Stereo
Gain Mismatch 0.2 dB Left- and right-channel gain mismatch
Crosstalk (Left to Right, Right to Left) −110 dB
Gain Error −1 dB Input signal is 100 μA rms
Current Setting Resistor (R
Power Supply Rejection −87 dB 1 kHz, 300 mV p-p signal at AVDD
ADC DIGITAL DECIMATOR FILTER
CHARACTERISTICS
Pass Band 22.5 kHz
Pass-Band Ripple ±0.0002 dB
Stop Band 26.5 kHz
Stop-Band Attenuation 100 dB
Group Delay 1040 μs
PWM SECTION
Frequency 384 kHz Guaranteed by design
Modulation Index 0.976 Guaranteed by design
Dynamic Range
Total Harmonic Distortion + Noise −78 dB −3 dB with respect to full-scale code input
DAC SECTION
Number of Auxiliary Output Channels 8 Four stereo channels
Resolution 24 Bits
Full-Scale Analog Output 1 V rms
Dynamic Range
Total Harmonic Distortion + Noise −86 dB −3 dBFS with respect to full-scale code input
Crosstalk (Left to Right, Right to Left) −102 dB
Interchannel Gain Mismatch 0.1 dB Left- and right-channel gain mismatch
Gain Error 0.525 dB 1 V rms output
DC Bias 1.53 V
Power Supply Rejection −90 dB 1 kHz, 300 mV p-p signal at AVDD
Output Impedance 235 Ω
DAC DIGITAL INTERPOLATION FILTER
CHARACTERISTICS
Pass Band 21.769 kHz
Pass-Band Ripple ±0.01 dB
Transition Band 23.95 kHz
Stop Band 26.122 kHz
Stop-Band Attenuation 75 dB
Group Delay 580 μs
HEADPHONE AMPLIFIER Measured at headphone output with 32 Ω load
Number of Channels 4 Two stereo channels
Full-Scale Output Power 31 mW rms 1 V rms output
Dynamic Range
Total Harmonic Distortion + Noise −83 dB −3 dBFS with respect to full-scale code input
Interchannel Gain Mismatch 0.1 dB
DC Bias 1.53 V
Power Supply Rejection −85 dB 1 kHz, 300 mV p-p signal at AVDD
A-Weighted 95 dB −60 dBFS with respect to full-scale analog input
−90 dB −3 dBFS with respect to full-scale analog input
Channel)
) 20 kΩ External resistor to set current input range of ADC for
ISET
nominal 2.0 V rms input signal
At 48 kHz, guaranteed by design
A-Weighted 98 dB −60 dB with respect to full-scale code input
A-Weighted 94 dB −60 dBFS with respect to full-scale code input
At 48 kHz, guaranteed by design
A-Weighted 93 dB −60 dBFS with respect to full-scale code input
Rev. B | Page 7 of 28
ADAV4622
Parameter Min Typ Max Unit Test Conditions/Comments
SRC
Number of Channels 8 Two channels (SRC1), six channels (SRC2)
Dynamic Range
A-Weighted 115 dB −60 dBFS input (worst-case input fS = 50 kHz)
Total Harmonic Distortion + Noise −113 dB −3 dBFS input (worst-case input fS = 50 kHz)
Sample Rate 5 50 kHz
SRC DIGITAL INTERPOLATION FILTER
CHARACTERISTICS
Pass Band 21.678 kHz
Pass-Band Ripple 0.005 dB
Stop Band 26.232 kHz
Stop-Band Attenuation 110 dB
Group Delay 876 μs
DIGITAL INPUT/OUTPUT
Input Voltage High (VIH) 2.0 ODVDD V
Input Voltage Low (VIL) 0.8 V
Input Leakage
IIH (SDIN0, SDIN1, SDIN2, SDIN3, LRCLK0,
LRCLK1, LRCLK2, BCLK0, BCLK1, BCLK2,
SPDIF_OUT, SPDIF_IN)
RESET
IIH (
)
IIL (SDO0, SCL, SDA) −40 μA VIL = 0 V, equivalent to a 90 kΩ pull-down resistor
Output Voltage High (VOH) 2.4 V IOH = 0.4 mA
Output Voltage Low (VOL) 0.4 V IOL = −2 mA
Output Voltage High (VOH) (MCLK_OUT) 1.4 V IOH = 0.4 mA
Output Voltage Low (VOL) (MCLK_OUT) 0.4 V IOL = −3.2 mA
Input Capacitance 10 pF
SUPPLIES
Analog Supplies (AVDD) 3.0 3.3 3.6 V
Digital Supplies (DVDD)
Interface Supply (ODVDD) 3.0 3.3 3.6 V
Supply Currents MCLK = 24 MHz, ADCs and DACs active, headphone
Analog Current 260 mA
Digital Current 350 mA
Interface Current 2 mA
Power Dissipation 1.495 W
Standby Currents
Analog Current 10 mA
Digital Current 4 mA
Interface Current 1.6 mA
TEMPERATURE RANGE
Operating Temperature −40 +85 °C
Storage Temperature −65 +150 °C
At 48 kHz, guaranteed by design
40 μA V
13.5 μA V
= ODVDD, equivalent to a 90 kΩ pull-up resistor
IH
= ODVDD, equivalent to a 266 kΩ pull-up resistor
IH
1.65 1.8 2.0 V
outputs active and driving a 16 Ω load
ADC, DAC, and headphone outputs floating,
MCLK = 24 MHz
RESET
low,
Rev. B | Page 8 of 28
ADAV4622
TIMING SPECIFICATIONS
Table 2.
Parameter Description Min Max Unit Comments
MASTER CLOCK AND RESET
f
MCLKI frequency 3.072 24.576 MHz
MCLKI
t
MCLKI high 10 ns
MCH
t
MCLKI low 10 ns
MCL
t
RESET
MASTER CLOCK OUTPUT
t
JIT
tCH MCLK_OUT high 45 55 %
tCL MCLK_OUT low 45 55 %
I2C PORT
f
SCL clock frequency 400 kHz
SCL
t
SCL high 600 ns
SCLH
t
SCL low 1.3 μs
SCLL
Start Condition
t
Setup time 600 ns Relevant for repeated start condition
SCS
t
Hold time 600 ns After this period, the first clock is generated
SCH
tDS Data setup time 100 ns
t
SCL rise time 300 ns
SCR
t
SCL fall time 300 ns
SCF
t
SDA rise time 300 ns
SDR
t
SDA fall time 300 ns
SDF
Stop Condition
t
Setup time 0 ns
SCS
SERIAL PORTS
Slave Mode
t
BCLK high 40 ns
SBH
t
BCLK low 40 ns
SBL
f
BCLK frequency 64 × fS
SBF
t
LRCLK setup 10 ns To BCLK rising edge
SLS
t
LRCLK hold 10 ns From BCLK rising edge
SLH
t
SDIN setup 10 ns To BCLK rising edge
SDS
t
SDIN hold 10 ns From BCLK rising edge
SDH
t
SDO delay 50 ns From BCLK falling edge
SDD
Master Mode
t
LRCLK delay 25 ns From BCLK falling edge
MLD
t
SDO delay 15 ns From BCLK falling edge
MDD
t
SDIN setup 10 ns From BCLK rising edge
MDS
t
SDIN hold 10 ns From BCLK rising edge
MDH
RESET low
Period jitter
200 ns
800 ps
Rev. B | Page 9 of 28
ADAV4622
TIMING DIAGRAMS
t
= 1/
f
MP
MCLKI
MCLKI
RESET
t
RESET
Figure 2. Master Clock and Reset Timing
t
JIT
DVDD
GND
t
CH
t
CK
t
CL
07068-036
Figure 3. Master Clock Output Timing
t
SLH
07068-004
LRCLK1
BCLK1
SDINx
SDO0
t
SLS
t
t
SDH
SDS
t
SDD
07068-002
Figure 4. Serial Port Slave Mode Timing
t
MLD
LRCLK1
BCLK1
SDINx
t
t
MDH
MDS
SDO0
t
MDD
07068-003
Figure 5. Serial Port Master Mode Timing
100µA I
OL
TO OUTPUT
PIN
50pF
100µA I
ODVDD
OH
07068-033
Figure 6. Load Circuit for Digital Output Timing Specifications
Rev. B | Page 10 of 28
ADAV4622
DVDD
AV
DD
ODVDD
0.18V
1.0s MAX
0.33V
1.0s MAX
1.65V
3.0V
1.8V
0V
3.
0V
3V
07068-034
Figure 7. Power-Up Sequence Timing
1.8V
0V
3.3V
0V
07068-035
OD
DVDD
AVDD
VDD
1.65V
0.18V
1.0s MAX
3.0V
0.33V
1.0s MAX
Figure 8. Power-Down Sequence Timing
Rev. B | Page 11 of 28
ADAV4622
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
DVDD to DGND 0 V to 2.2 V
ODVDD to DGND 0 V to 4 V
AVDD to AGND 0 V to 4 V
AGND to DGND −0.3 V to +0.3 V
Digital Inputs DGND − 0.3 V to ODVDD + 0.3 V
Analog Inputs AGND − 0.3 V to AVDD + 0.3 V
Reference Voltage Indefinite short circuit to ground
Soldering (10 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA θ
80-Lead LQFP 38.1 7.6 °C/W
1
Based on JEDEC 2S2P PCB.
1
Unit
JC
THERMAL CONDITIONS
To ensure correct operation of the device, the case temperature
) must be kept below 121°C to keep the junction tempera-
(T
CASE
ture (T
) below the maximum allowed, 125°C.
J
ESD CAUTION
Rev. B | Page 12 of 28
ADAV4622
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ISET
AUXIN1R
AUXIN1L
AUXIN2R
AUXIN2L
AUXOUT2R
AUXOUT2L
AUXOUT1R
AUXOUT1L
AVDD
AGND
AGND
AVDD
FILTDNCAUXOUT4R
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
AUXOUT4L
AUXOUT3R
AUXOUT3L
HPOUT2R
40
PWM_READY
60
HPOUT2L
59
AVDD
58
HPOUT1R
57
HPOUT1L
56
AGND
55
AGND
54
PLL_LF
53
AVDD
52
DGND
51
DVDD
50
RESET
49
PWM4B
48
PWM4A
47
PWM3B
46
PWM3A
45
PWM2B
44
PWM2A
43
PWM1B
42
PWM1A
41
DGND
DVDD
07068-006
FILTA
VREF
AGND
AVDD
SIF_REFP
SIF_REFCM
SIF_REFN
SIF_IN1
SIF_PGA_REF
SIF_IN2
AGND
AVDD
DGND
DVDD
MUTE
SDA
SCL
SPDIF_IN5/LRCLK2
SPDIF
_IN6/BCLK2
DGND
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
PIN 1
22
DVDD
SDIN023SDIN124SDIN2
ADAV4622
TOP VIEW
(Not to Scale)
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
DGND
XOUT
SPDIF_IN4/BCLK1
SDO0/AD0
SPDIF_OUT/SDO1
SPDIF_IN3/LRCLK1
MCLKI/XIN
SPDIF_IN0/SDIN3
DVDD
ODVDD
ODGND
MCLK_OUT
SPDIF_IN2/BCLK0
SPDIF_IN1/LRCLK0
Figure 9. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 FILTA ADC Filter Capacitor.
2 VREF Reference Capacitor.
3 AGND ADC Ground.
4 AVDD ADC Supply (3.3 V).
5 SIF_REFP SIF ADC Positive Reference (Typical 1.4 V).
6 SIF_REFCM SIF ADC Common-Mode Reference (Typical 1 V).
7 SIF_REFN SIF ADC Negative Reference (Typical 0.6 V).
8 SIF_IN1 SIF Input 1.
9 SIF_PGA_REF SIF PGA Reference.
10 SIF_IN2 SIF Input 2.
11 AGND SIF AGND.
12 AVDD SIF Supply (3.3 V).
13 DGND Digital Ground.
14 DVDD Digital Supply (1.8 V).
15
MUTE
Active Low Mute Request Input Signal.
Rev. B | Page 13 of 28
ADAV4622
Pin No. Mnemonic Description
16 SDA I2C Data.
17 SCL I2C Clock.
18 SPDIF_IN5/LRCLK2 External Input to S/PDIF Mux/Left/Right Clock for SRC2 (Default).
19 SPDIF_IN6/BCLK2 External Input to S/PDIF Mux/Bit Clock for SRC2 (Default).
20 DGND Digital Ground.
21 DVDD Digital Supply (1.8 V).
22 SDIN0 Serial Data Input 0/SRC Data Input.
23 SDIN1 Serial Data Input 1/SRC Data Input.
24 SDIN2 Serial Data Input 2/SRC Data Input.
25 SPDIF_IN0/SDIN3 External Input to S/PDIF Mux/SRC Data Input/Serial Data Input 3 (Default).
26 SPDIF_IN1/LRCLK0 External Input to S/PDIF Mux/Left/Right Clock for SRC1 (Default).
27 SPDIF_IN2/BCLK0 External Input to S/PDIF Mux/Bit Clock for SRC1 (Default).
28 ODGND Digital Ground.
29 ODVDD Digital Interface Supply (3.3 V).
30 MCLK_OUT Master Clock Output.
31 DVDD Digital Supply (1.8 V).
32 DGND Digital Ground.
33 MCLKI/XIN Master Clock/Crystal Input.
34 XOUT Crystal Output.
35 SPDIF_IN4/BCLK1 External Input to S/PDIF Mux/Bit Clock for Serial Data I/O (Default).
36 SPDIF_IN3/LRCLK1 External Input to S/PDIF Mux/Left/Right Clock for Serial Data I/O (Default).
37 SDO0/AD0
Serial Data Output. This pin acts as the I
resistor.
38 SPDIF_OUT/SDO1 Output of S/PDIF Mux/Serial Data Output.
39 PWM_READY PWM Ready Flag.
40 DVDD Digital Supply (1.8 V).
41 DGND Digital Ground.
42 PWM1A Pulse-Width Modulated Output 1A.
43 PWM1B Pulse-Width Modulated Output 1B.
44 PWM2A Pulse-Width Modulated Output 2A.
45 PWM2B Pulse-Width Modulated Output 2B.
46 PWM3A Pulse-Width Modulated Output 3A.
47 PWM3B Pulse-Width Modulated Output 3B.
48 PWM4A Pulse-Width Modulated Output 4A.
49 PWM4B Pulse-Width Modulated Output 4B.
50
RESET
Reset Analog and Digital Cores.
51 DVDD Digital Supply (1.8 V).
52 DGND Digital Ground.
53 AVDD PLL Supply (3.3 V).
54 PLL_LF PLL Loop Filter.
55 AGND PLL Ground.
56 AGND Headphone Driver Ground.
57 HPOUT1L Left Headphone Output 1.
58 HPOUT1R Right Headphone Output 1.
59 AVDD Headphone Driver Supply (3.3 V).
60 HPOUT2L Left Headphone Output 2.
61 HPOUT2R Right Headphone Output 2.
62 AUXOUT3L Left Auxiliary Output 3.
63 AUXOUT3R Right Auxiliary Output 3.
64 AUXOUT4L Left Auxiliary Output 4.
65 AUXOUT4R Right Auxiliary Output 4.
66 NC No Connection to this Pin Allowed.
67 FILTD DAC Filter Capacitor.
2
C address select on reset. It has an internal pull-down
Rev. B | Page 14 of 28
ADAV4622
Pin No. Mnemonic Description
68 AVDD DAC Supply (3.3 V).
69 AGND DAC Ground.
70 AGND DAC Ground.
71 AVDD DAC Supply (3.3 V).
72 AUXOUT1L Left Auxiliary Output 1.
73 AUXOUT1R Right Auxiliary Output 1.
74 AUXOUT2L Left Auxiliary Output 2.
75 AUXOUT2R Right Auxiliary Output 2.
76 AUXIN2L Left Auxiliary Input 2.
77 AUXIN2R Right Auxiliary Input 2.
78 AUXIN1L Left Auxiliary Input 1.
79 AUXIN1R Right Auxiliary Input 1.
80 ISET ADC Current Setting.
Rev. B | Page 15 of 28
ADAV4622
TYPICAL PERFORMANCE CHARACTERISTICS
0
–20
–40
–60
–80
–100
MAGNITUDE (dB)
–120
–140
–160
–180
07
192 384 576
FREQUENCY (kHz)
68
07068-007
Figure 10. DAC Composite Filter Response (48 kHz)
0
–30
–60
–90
–120
–150
–180
MAGNITUDE (dB)
–210
–240
–270
–300
03
128 256 84
FREQUENCY (kHz)
07068-010
Figure 13. ADC Composite Filter Response (48 kHz)
0
–20
–40
–60
–80
–100
MAGNITUDE (dB)
–120
–140
–160
09
24 48 72
FREQUENCY (kHz)
6
07068-008
Figure 11. DAC Band-Pass Filter Response (48 kHz)
0
–30
–60
–90
MAGNITUDE (dB)
–120
–150
–180
09
Figure 14. ADC Band-Pass Filter Response (48 kHz)
0.6
0.4
0.2
0
MAGNITUDE (d B)
–0.2
–0.4
MAGNITUDE (d B)
0.04
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
24 48 72 6
FREQUENCY (kHz)
07068-011
–0.6
02
816 4
FREQUENCY (kHz)
07068-009
Figure 12. DAC Pass-Band Ripple (48 kHz)
–0.04
02
Figure 15. ADC Pass-Band Ripple (48 kHz)
Rev. B | Page 16 of 28
816 4
FREQUENCY (kHz)
07068-012
ADAV4622
0
0
–20
–40
–60
–80
–100
MAGNIT UDE (dBV)
–120
–140
–160
0 20000
4000 8000 12000 16000
FREQUENCY (Hz)
07068-013
Figure 16. DAC Dynamic Range
0
–20
–40
–60
–80
–100
MAGNITUDE (d BV)
–120
–140
–160
020000
4000 8000 12000 16000
FREQUENCY (Hz)
07068-014
Figure 17. DAC Total Harmonic Distortion + Noise
0
–20
–40
–60
–80
–100
MAGNITUDE (dBV)
–120
–140
–160
0 20000
4000 8000 12000 16000
Figure 19. ADC Total Harmonic Distortion + Noise
0
–20
–40
–60
–80
GAIN (dB)
–100
–120
–140
010.90.80.70.60.50.40.30. 20. 1
Figure 20. Sample Rate Converter Transfer Function
–20
FREQUE NCY (Hz)
NORMALIZE D FREQUENCY
07068-016
.0
07068-017
–40
–60
–80
–100
MAGNITUDE (dBV)
–120
–140
–160
0 20000
4000 8000 12000 16000
FREQUENCY (Hz)
Figure 18. ADC Dynamic Range
07068-015
Rev. B | Page 17 of 28
ADAV4622
TERMINOLOGY
Dynamic Range
The ratio of a full-scale input signal to the integrated input
noise in the pass band (20 Hz to 20 kHz), expressed in decibels
(dB). Dynamic range is measured with a −60 dB input signal
and is equal to (S/[THD+N]) + 60 dB. Note that spurious
harmonics are below the noise with a −60 dB input, so the noise
level establishes the dynamic range. The dynamic range is
specified with and without an A-weight filter applied.
Pass Band
The region of the frequency spectrum unaffected by the
attenuation of the digital decimator’s filter.
Pass-Band Ripple
The peak-to-peak variation in amplitude response from equal
amplitude input signal frequencies within the pass band,
expressed in decibels.
Stop Band
The region of the frequency spectrum attenuated by the digital
decimator’s filter to the degree specified by stop-band
attenuation.
Gain Error
With a near full-scale input, the ratio of the actual output to the
expected output, expressed in dB.
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of the outputs of
the two stereo channels, expressed in decibels.
Crosstalk
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine wave input on the other channel, expressed
in decibels.
Power Supply Rejection
With no analog input, the signal present at the output when a
300 mV p-p signal is applied to power supply pins, expressed
in decibels of full scale.
Group Delay
Intuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in milliseconds (ms).
More precisely, the derivative of radian phase with respect to
radian frequency at a given frequency.
SIF Input Isolation
The level of the crosstalk between the SIF inputs in dB.
FM Limiting Sensitivity
FM limiting sensitivity is given by the modulated carrier level
that gives half the power to the FM demodulator’s output
amplitude comparing to that when the carrier level satisfies
the demodulator’s limiting level.
Deviation Mode
In some regions, the transmitted signal can deviate from the
specification. In order for the ADAV4622 to decode these high
deviation signals correctly, the appropriate modulation level
must be selected.
AM Rejection Ratio
AM rejection ratio is given by the ratio of FM (deviation = 54%)
demodulated audio level vs. residual AM (modulation = 27%)
demodulated audio level at the same carrier level. It is the ability
of the receiver to not mistake an AM signal for an FM signal.
AM Sensitivity
AM sensitivity is a measure of how well the receiver picks up
very weak AM signals.
Rev. B | Page 18 of 28
ADAV4622
PIN FUNCTIONS
Tabl e 5 shows the pin numbers, mnemonics, and descriptions
for the ADAV4622. The input pins have a logic threshold
compatible with 3.3 V input levels.
SDIN0, SDIN1, SDIN2, AND SDIN3/SPDIF_IN0
Serial data inputs. These input pins provide the digital audio
data to the signal processing core. Any of the inputs can be
routed to either of the SRCs for conversion; this input is then
not available as a synchronous input to the audio processor but
only as an input through the selected SRC. The serial format
for the synchronous data is selected by Bits [3:2] of the serial
port control register. If the SRCs are required, the serial format
is selected by Bits [12:9] of the same register. The synchronous
inputs are capable of using any pair of serial clocks LRCLK0/
BCLK0, LRCLK1/BCLK1, or LRCLK2/BCLK2. By default,
they use LRCLK1 and BCLK1. See Figure 24 for more details
regarding the configuration of the synchronous inputs.
SDIN3 is a shared pin with SPDIF_IN0. If SDIN3 is not in use,
this pin can be used to connect an S/PDIF signal from an
external source, such as an MPEG decoder, to the ADAV4622
on-chip S/PDIF output multiplexer. If SPDIF_OUT is selected
from one of the SPDIF_IN (external) signals, the signal is
simply passed through from input to output.
LRCLK0, BCLK0, LRCLK1, BCLK1, LRCLK2, AND BCLK2
By default, LRCLK1 and BCLK1 are associated with the
synchronous inputs, LRCLK0 and BCLK0 are associated with
SRC1, and LRCLK2 and BCLK2 are associated with SRC2.
However, the SRCs and synchronous inputs can use any of the
serial clocks (see Figure 24 for more details). LRCLK0, BCLK0,
LRCLK1, BCLK1, LRCLK2, and BCLK2 are shared pins with
SPDIF_IN1, SPDIF_IN2, SPDIF_IN3, SPDIF_IN4, SPDIF_IN5,
and SPDIF_IN6, respectively. If LRCLK0/LRCLK1/LRCLK2 or
BCLK0/BCLK1/BCLK2 are not in use, these pins can be used to
connect an S/PDIF signal from an external source, such as an
MPEG decoder, to the ADAV4622 on-chip S/PDIF output
multiplexer. If SPDIF_OUT is selected from one of the
SPDIF_IN (external) signals, the signal is simply passed
through from input to output.
SDO0/AD0
Serial data output. This pin can output two channels of digital
audio using a variety of standard 2-channel formats. The clocks
for SDO0 are always the same as those used by the synchronous
inputs; this means that LRCLK1 and BCLK1 are used by default,
although SDO0 is capable of using any pair of serial clocks,
LRCLK0/BCLK0, LRCLK1/BCLK1, or LRCLK2/BCLK2.
The serial port control register selects the serial format for the
synchronous output. On reset, the SDO0 pin duplicates as the
2
I
C® address select pin. In this mode, the logical state of the pin
is polled for four MCLKI cycles following reset. The address
select bit is set as the majority poll of the pin’s logic level after
the four MCLKI cycles.
SPDIF_OUT (SDO1)
The ADAV4622 contains an S/PDIF multiplexer functionality
that allows the SPDIF_OUT signal to be chosen from an
internally generated S/PDIF signal or from the S/PDIF signal
from an external source, which is connected via one of the
SPDIF_IN pins. This pin can also be configured as an
additional serial data output (SDO1) as an alternate function.
MCLKI/XIN
Master clock input. The ADAV4622 uses a PLL to generate the
appropriate internal clock for the audio processing core. A clock
signal of a suitable frequency can be connected directly to this
pin, or a crystal can be connected between MCLKI/XIN and
XOUT together with the appropriate capacitors to DGND to
generate a suitable clock signal.
XOUT
This pin is used in conjunction with MCLKI/XIN to generate a
clock signal for the ADAV4622.
MCLK_OUT
This pin can be used to output MCLKI or one of the internal
system clocks. It should be noted that the output level of this
pin is referenced to DVDD (1.8 V) and not ODVDD (3.3 V)
like all other digital inputs and outputs.
SDA
Serial data input for the I2C control port. SDA features a glitch
elimination filter that removes spurious pulses that are less than
50 ns wide.
Rev. B | Page 19 of 28
ADAV4622
SCL
Serial clock for the I2C control port. SCL features a glitch
elimination filter that removes spurious pulses that are less
than 50 ns wide.
FILTA AND FILTD
Decoupling nodes for the ADC and DAC. Decoupling
capacitors should be connected between these nodes and
AGND, typically 47 μF/0.1 μF and 10 μF/0.1 μF, respectively.
MUTE
Mute input request. This active-low input pin controls the
muting of the output ports (both analog and digital) from the
ADAV4622. When low, it asserts mute on the outputs that are
enabled in the audio flow.
RESET
Active-low reset signal. After
blocks are powered down. The blocks can be individually
powered up with software. When the part is powered up, it
takes approximately 3072 internal clocks to initialize the
internal circuitry. The internal system clock is equal to MCLKI
until the PLL is powered and enabled, after which the internal
system clock becomes 2560 × f
is powered up and enabled after reset, it takes approximately
3 ms to lock. When the audio processor is enabled, it takes
approximately 32,768 internal system clocks to initialize and
load the default flow to the audio processor memory. The audio
processor is not available during this time.
RESET
goes high, all the circuit
(122.88 MHz). Once the PLL
S
AUXIN1L, AUXIN2L, AUXIN1R, AND AUXIN2R
Analog inputs to the on-chip ADCs.
AUXOUT1L, AUXOUT2L, AUXOUT3L, AUXOUT4L, AUXOUT1R, AUXOUT2R, AUXOUT3R, AND AUXOUT4R
Auxiliary DAC analog outputs. These pins can be programmed
to supply the outputs of the internal audio processing for line
out or record use.
HPOUT1L, HPOUT2L, HPOUT1R, AND HPOUT2R
Analog outputs from the headphone amplifiers.
PLL_LF
PLL loop filter connection. A 100 nF capacitor and a 2 kΩ
resistor in parallel with a 1 nF capacitor tied to AVDD are
required for the PLL loop filter to operate correctly.
VREF
Voltage reference for DACs and ADCs. This pin is driven by an
internal 1.5 V reference voltage.
PWM1A, PWM1B, PWM2A, PWM2B, PWM3A, PWM3B, PWM4A, AND PWM4B
Differential pulse-width modulation outputs are suitable for
driving Class-D amplifiers.
PWM_READY
This pin is set high when PWM is enabled and stable.
AVDD
Analog power supply pins. These pins should be connected to
3.3 V. Each pin should be decoupled with 10 μF and 0.1 μF
capacitors to AGND, as close to the pin as possible.
DVDD
Digital power supply. This pin is connected to a 1.8 V digital
supply. Connecting 10 μF and 0.1 μF decoupling capacitors to
DGND, as close to the pin as possible, is strongly recommended
for optimal performance.
ODVDD
Digital interface power supply pin. This pin should be
connected to a 3.3 V digital supply. The pin should be
decoupled with 10 μF and 0.1 μF capacitors to DGND, as
close to the pin as possible.
DGND
Digital ground.
AGND
Analog ground.
ODGND
Ground for the digital interface power supply.
SIF_REFP, SIF_REFCM, AND SIF_REFN
Decoupling nodes for the SIF block.
SIF_IN1 AND SIF_IN2
Analog inputs for the SIF block.
SIF_PGA_REF
PGA reference output. This pin should be decoupled to AGND
with 10 μF and 0.1 μF capacitors.
ISET
ADC current setting resistor.
Rev. B | Page 20 of 28
ADAV4622
FUNCTIONAL DESCRIPTIONS
SIF PROCESSOR
Supported SIF Standards
The ADAV4622 supports all worldwide standards, as shown in
Tabl e 6.
Table 6. ADAV4622 Worldwide SIF Standards
System Sound SC1 (MHz) SC2 (MHz)
M BTSC 4.5 –
N BTSC 4.5 –
M EIAJ 4.5 –
M A2 4.5 4.724
BG A2 5.5 5.742
BG NICAM 5.5 5.85
I Mono 6.0 –
I NICAM 6.0 6.552
DK1 A2 6.5 6.258
DK2 A2 6.5 6.742
DK3 A2 6.5 5.742
DK NICAM 6.5 5.85
L Mono 6.5 –
L NICAM 6.5 5.85
SIF Demodulation
Figure 22 shows a block diagram of the SIF demodulation
block. The selected SIF input signal is digitized by an ADC with
a sample rate of 24.576 MHz. An AGC is included to ensure
that for even low level signals, the full range of the ADC is used.
The digitized input is passed to the SIF demodulator for
demodulating. The outputs of the demodulator are then passed
to the internal audio processor. Internally, the audio processor
runs at a 48 kHz sampling frequency. When NICAM is selected,
an internal SRC upsamples the 32 kHz NICAM signal to the
audio processor rate of 48 kHz.
SIF Processor Configuration
The ADAV4622 supports automatic standard detection, which
is enabled by default. The ASD controller configures the SIF
processor with the optimum register settings based on the
detected standard. If the user prefers to operate in manual mode,
or if the user prefers to use an external ASD loop, all of the ASD
status registers are available.
MASTER CLOCK OSCILLATOR
Internally, the ADAV4622 operates synchronously to the master
MCLKI input. All internal system clocks are generated from
this single clock input using an internal PLL. This MCLKI input
can also be generated by an external crystal oscillator connected
to the MCLKI/XIN pin or by using a simple crystal resonator
connected across MCLKI/XIN and XOUT. By default, the
master clock frequency is 24.576 MHz; however, by using the
internal dividers, an MCLKI of 12.288 MHz, 6.144 MHz, and
3.072 MHz are also supported.
EXTERNAL CLOCK/
CRYSTAL
I2C
OSC
DIVIDER
REGIST ER
Figure 21. Master Clock
MASTER CL OCK FRE QUENCY
[24.576MHz, 12.288MHz ,
6.144MHz, 3.072MHz]
3.072MHz
DIVIDER W ORD
[÷8, ÷4, ÷2, ÷1]
PLL
REFERENCE
CLOCK
07068-018
SC1
SC2
FM/DQPSK/AM
DEMOD
SIF
PARAMETERS
ASD
A
B
07068-020
SIF INPUT
4.5MHz ~ 6.742MHz
SIF_IN1
SIF_IN2
MUX
AGC
ADC
24.576MHz
Figure 22. SIF Demodulation
Rev. B | Page 21 of 28
ADAV4622
I2C INTERFACE
The ADAV4622 supports a 2-wire serial (I2C compatible)
microprocessor bus driving multiple peripherals. The
ADAV4622 is controlled by an external I
2
C master device,
such as a microcontroller. The ADAV4622 is in slave mode
2
on the I
C bus, except during self-boot. While the ADAV4622
is self-booting, it becomes the master, and the EEPROM, which
contains the ROMs to be booted, is the slave. When the selfboot process is complete, the ADAV4622 reverts to slave mode
2
on the I
C bus. No other devices should access the I2C bus while
the ADAV4622 is self-booting (refer to the Application Layer
section and the Loading a Custom Audio Processing Flow
section).
Initially, all devices on the I
2
C bus are in an idle state, wherein
the devices monitor the SDA and SCL lines for a start condition
and the proper address. The I
2
C master initiates a data transfer
by establishing a start condition, defined by a high-to-low
transition on SDA while SCL remains high. This indicates that
an address/data stream follows. All devices on the bus respond
to the start condition and read the next byte (7-bit address plus
W
the R/
bit) MSB first. The device that recognizes the transmitted address responds by pulling the data line low during the
ninth clock pulse. This ninth bit is known as an acknowledge
bit. All other devices on the bus revert to an idle condition. The
W
R/
bit determines the direction of the data. A Logic Level 0
on the LSB of the first byte means the master writes information
to the peripheral. A Logic Level 1 on the LSB of the first byte
means the master reads information from the peripheral. A data
transfer takes place until a stop condition is encountered. A stop
condition occurs when SDA transitions from low to high while
SCL is held high.
The ADAV4622 determines its I
2
C device address by sampling
the SDO0 pin after reset. Internally, the SDO0 pin is sampled by
four MCLKI edges to determine the state of the pin (high or
low). Because the pin has an internal pull-down resistor default,
the address of the ADAV4622 is 0x34 (write) and 0x35 (read).
An alternate address, 0x36 (write) and 0x37 (read), is available
by tying the SDO0 pin to ODVDD via a 10 kΩ resistor. The I
2
C
interface supports a clock frequency up to 400 kHz.
ADC INPUTS
The ADAV4622 has four ADC inputs. By default, these are
configured as two stereo inputs; however, because the audio
processor is programmable, these inputs can be reconfigured.
The ADC inputs are shown in Figure 23. The analog inputs are
current inputs (100 μA rms FS) with a 1.5 V dc bias voltage.
Any input voltage can be accommodated by choosing a suitable
combination of input resistor (R
using the formulas
R
= V
IN
R
ISET
/100 μA rms
FS rms
= 2RIN/VIN
) and ISET resistor (R
IN
ISET
)
Resistor matching (typically 1%) between R
and R
IN
important to ensure a full-scale signal on the ADC without
clipping.
ANALOG INPUT
100µA
FULL SCALE
ANALOG INPUT
100µA
FULL SCALE
ANALOG INPUT
100µA
FULL SCALE
ANALOG INPUT
100µA
FULL SCALE
rms
rms
rms
rms
AUXIN1L
AUXIN1R
AUXIN2L
AUXIN2R
R
ISET
20kΩ
20kΩ
20kΩ
20kΩ
20kΩ
ISET
DC BIAS
1.5V
DC BIAS
1.5V
DC BIAS
1.5V
DC BIAS
1.5V
Figure 23. Analog Input Section
I2S DIGITAL AUDIO INPUTS
The ADAV4622 has four I2S digital audio inputs that are, by
default, synchronous to the master clock. Also available are two
SRCs capable of supporting any nonsynchronous input with a
sample rate between 5 kHz and 50 kHz. Any of the serial digital
inputs can be redirected through the SRC. Figure 24 shows a
block diagram of the input serial port.
SDIN0
SDIN1
SDIN2
SDIN3
SDIN0
SDIN1
SDIN2
SDIN3
LRCLK0
BCLK0
LRCLK1
BCLK1
LRCLK2
BCLK2
SDIN0
SDIN1
SDIN2
SDIN3
LRCLK0
BCLK0
LRCLK1
BCLK1
LRCLK2
BCLK2
LRCLK0
BCLK0
LRCLK1
BCLK1
LRCLK2
BCLK2
Figure 24. Digital Input Section
SRC2B
SRC2C
SRC1
SRC2
SRC2A
SRC2B
SRC2C
ISET
24-BIT
ADC
24-BIT
ADC
24-BIT
ADC
24-BIT
ADC
AUDIO
PROCESSOR
is
07068-019
07068-021
Rev. B | Page 22 of 28
ADAV4622
Synchronous Inputs and Outputs
The synchronous digital inputs and outputs can use any of the
BCLK or LRCLK inputs as a clock and framing signal. By
default, BCLK1 and LRCLK1 are the serial clocks used for the
synchronous inputs. The synchronous port for the ADAV4622
is in slave mode by default, which means the user must supply
the appropriate serial clocks, BCLK and LRCLK. The
synchronous port can also be set to master mode, which means
that the appropriate serial clocks, BCLK and LRCLK, can be
generated internally from the MCLK; therefore, the user does
not need to provide them. The serial data inputs are capable of
accepting all the popular audio transmission standards (see the
Serial Data Interface section for more details).
Asynchronous Inputs
The ADAV4622 has two SRCs, SRC1 and SRC2, that can be
used for converting digital data, which is not synchronous to
the master clock. Each SRC can accept input sample rates in the
range of 5 kHz to 50 kHz. Data that has been converted by the
SRC is inputted to the part and is then synchronous to the
internal audio processor.
The SRC1 is a 2-channel (single-stereo) sample rate converter
that is capable of using any of the three serial clocks available.
The SRC1 can accept data from any of the serial data inputs
(SDIN0, SDIN1, SDIN2, and SDIN3). Once selected as an input
to the SRC, this SDIN line is assumed to contain asynchronous
data and is then masked as an input to the audio processor to
ensure that asynchronous data is not processed as synchronous
data. By default, SRC1 uses the LRCLK0 and BCLK0 as the
clock and framing signals.
The SRC2 is a 6-channel (3-stereo) sample rate converter that is
capable of using any of the three serial clocks available. The
SRC2 can accept data from any of the serial data inputs (SDIN0,
SDIN1, SDIN2, and SDIN3). Once selected as an input to the
SRC, this SDIN line is assumed to contain asynchronous data
and is then masked internally as an input to the audio processor
to ensure that asynchronous data is not processed as
synchronous data. By default, SRC2 uses the LRCLK2 and
BCLK2 as the clock and framing signals.
The first output (SRC2A) from SRC2 is always available to the
audio processor. The other two outputs are muxed with two of
the serial inputs before being available to the audio processor.
SRC2B is muxed with SDIN2 and SRC2C is muxed with SDIN3.
By default, these muxes are configured so that the synchronous
inputs are available to the audio processor. The SRC2B and
SRC2C channels can be made available to the audio processor
simply by enabling them by register write.
When using the ADAV4622 in an asynchronous digital-in-todigital-out configuration, the input digital data are input to the
audio processor core from one of the SRCs, using the assigned
BCLK/LRCLK as a framing signal. The digital output is
synchronous to the BCLK/LRCLK, which is assigned to the
Rev. B | Page 23 of 28
synchronous port; the default clocks in this case are BCLK1 and
LRCLK1.
Serial Data Interface
LRCLK is the framing signal for the left- and right-channel
inputs, with a frequency equal to the sampling frequency (f
).
S
BCLK is the bit clock for the digital interface, with a frequency
of 64 × f
(32 BCLK periods for each of the left and right
S
channels).
The serial data interface supports all the popular audio interface
standards, such as I
The interface mode is software selectable, and its default is I
2
S, left-justified (LJ), and right-justified (RJ).
2
S.
The data sample width is also software selectable from 16 bits,
20 bits, or 24 bits. The default is 24 bits.
I2S Mode
In I2S mode, the data are left-justified, MSB first, with the MSB
placed in the second BCLK period following the transition of
the LRCLK. A high-to-low transition of the LRCLK signifies the
beginning of the left-channel data transfer, and a low-to-high
transition on the LRCLK signifies the beginning of the rightchannel data transfer (see Figure 26).
LJ Mode
In LJ mode, the data are left-justified, MSB first, with the MSB
placed in the first BCLK period following the transition of the
LRCLK. A high-to-low transition of the LRCLK signifies the
beginning of the right-channel data transfer, and a low-to-high
transition on the LRCLK signifies the beginning of the leftchannel data transfer (see Figure 27).
RJ Mode
In RJ mode, the data are right-justified, LSB last, with the LSB
placed in the last BCLK period preceding the transition of
LRCLK. A high-to-low transition of the LRCLK signifies the
beginning of the right-channel data transfer, and a low-to-high
transition on the LRCLK signifies the beginning of the leftchannel data transfer (see Figure 28).
DAC VOLTAGE OUTPUTS
The ADAV4622 has eight DAC outputs, configured as four stereo
auxiliary DAC outputs. However, because the flow is customizable, this is programmable. The output level is 1 V rms full scale.
AUXOUT1L
DAC
DAC
DAC
DAC
Figure 25. DAC Output Section
AUXOUT1R
AUXOUT2L
AUXOUT2R
AUXOUT3L
AUXOUT3R
AUXOUT4L
AUXOUT4R
07068-025
ADAV4622
LRCLK
BCLK
SDO0
MSB
LEFT CHANNEL
LSB
MSB
RIGHT CHANNE L
LSB
Figure 26. I
LRCLK
BCLK
SDO0
MSB
LEFT CHANNEL
LSB
Figure 27. Left-Justified Mode
LRCLK
BCLK
SDO0
LEFT CHANNEL
MSB LSB
Figure 28. Right-Justified Mode
PWM OUTPUTS
In the ADAV4622, the main outputs are available as four PWM
output channels, which are suitable for driving Class-D amplifiers.
PWM_Ready is a status pin used to signify that the ADAV4622
PWM outputs are in a valid state. During PWM power-up and
power-down, this pin remains low to signify that the outputs
are not in a valid state. The output power stage should remain
muted until this pin goes high. This functionality helps to
eliminate pop/click and other unwanted noise on the outputs.
+
PWM
MODULATOR
PWM
MODULATOR
PWM
MODULATOR
PWM
MODULATOR
Figure 29. PWM Output Section
Each set of PWM outputs is a complementary output. The
modulation frequency is 384 kHz, and the full-scale duty cycle
has a ratio of 97:3.
Full details on the use of the PWM outputs are available upon
request. Contact a local Analog Devices sales representative for
more details.
–
+
–
+
–
+
–
PWM1A
PWM1B
PWM2A
PWM2B
PWM3A
PWM3B
PWM4A
PWM4B
PWM_READY
07068-026
1 /F
S
2
S Mode
RIGHT CHANNE L
1 /F
1 /F
MSB
S
RIGHT CHANNEL
MSB
S
LSB
HEADPHONE OUTPUTS
There are two stereo headphone amplifier outputs capable
of driving 32 Ω loads at 1 V rms. HPOUT1 is shared with
AUXOUT4, and HPOUT2 is shared with AUXOUT2, as shown
in Figure 30.
AUXOUT4L
PA
DAC
AUXOUT4R
AUXOUT2L
PA
DAC
AUXOUT2R
Figure 30. Headphone Outputs Section
HPOUT1L
HPOUT1R
HPOUT2L
HPOUT2R
I2S DIGITAL AUDIO OUTPUTS
One I2S output, SDO0, uses the same serial clocks as the serial
inputs, which are BCLK1 and LRCLK1 by default. If an additional digital output is required, an additional pin can be
reconfigured as a serial digital output, as shown in Figure 31.
L
R
I2S OUTPUT
INTERFACE
L
R
S/PDIF
OUTPUT
LSB
07068-027
SDO0
SPDIF_OUT (SDO 1)
07068-022
07068-023
07068-024
Rev. B | Page 24 of 28
BCLK1
LRCLK1
Figure 31. I
2
S Digital Outputs
07068-028
ADAV4622
S/PDIF INPUT/OUTPUT
The S/PDIF output (SPDIF_OUT/SDO1) uses a multiplexer to
select an output from the audio processor or to pass through the
unprocessed SPDIF_IN signals, as shown in Figure 32. On the
ADAV4622, the S/PDIF inputs, SPDIF_IN0/SPDIF_IN1/
SPDIF_IN2/SPDIF_IN3/SPDIF_IN4/SPDIF_IN5/SPDIF_IN6,
are available on the SDIN3, LRCLK0, BCLK0, LRCLK1,
BCLK1, LRCLK2, and BCLK2 pins, respectively. It is possible to
have all seven S/PDIF inputs connected to different S/PDIF
signals at one time. A consequence of this setup is that none of
the LRCLKs and BCLKs are available for use with the digital
inputs SDIN0, SDIN1, SDIN2, and SDIN3. If there is only one
S/PDIF input in use, using the SDIN3 pin as the dedicated
S/PDIF input is recommended; this enables BCLK0/LRCLK0,
BCLK1/LRCLK1, and BCLK2/LRCLK2 to be used as the clock
and framing signal for the synchronous and asynchronous port.
If SDIN3 is used as an S/PDIF input, it should not be used
internally as an input to the audio processor because it contains
invalid data. Similarly, if BCLK or LRCLK are used as S/PDIF
inputs, they can no longer be used as the clock and framing
signals for SDIN0, SDIN1, SDIN2, and SDIN3. The S/PDIF
encoder supports only consumer formats that conform to
IEC-600958.
SDIN3 (SPDIF_IN0)
LRCLK0 (SPDI F_IN1)
BCLK0 (SPDIF _IN2)
LRCLK1 (SPDI F_IN3)
BCLK1 (SPDIF _IN4)
LRCLK2 (SPDI F_IN5)
BCLK2 (SPDIF _IN6)
ENCODER
Figure 32. S/PDIF Output
SDO1 (SPDIF_OUT)S/PDIF
07068-029
HARDWARE MUTE CONTROL
The ADAV4622 mute input can be used to mute any of the
analog or digital outputs. When the
selected outputs ramp to a muted condition. Unmuting is
handled in one of two ways and depends on the register setting.
By default, the
MUTE
pin going high causes the outputs to
immediately ramp to an unmuted state. However, it is also
possible to have the unmute operation controlled by a control
register bit. In this scenario, even if the
the device does not unmute until a bit in the control register is
set. This can be used when the user wants to keep the outputs
muted, even after the pin has gone high again, for example, in
the case of a fault condition. This allows the system controller
total control over the unmute operation.
Full details on register settings and operation of the mute function
are available upon request. Contact a local Analog Devices sales
representative for more details.
MUTE
pin goes low, the
MUTE
pin goes high,
AUDIO PROCESSOR
The internal audio processor runs at 2560 × fS; at 48 kHz, this
is 122.88 MHz. Internally, the word size is 28 bits, which allows
24 dB of headroom for internal processing. Designed specifically with audio processing in mind, it can implement complex
audio algorithms efficiently.
By default, the ADAV4622 loads a default audio flow, as shown
in Figure 34. However, because the audio processor is fully
programmable, a custom audio flow can be quickly developed
and loaded to the audio processor.
The audio flow is contained in program RAM and parameter
RAM. Program RAM contains the instructions to be processed
by the audio processor, and parameter RAM contains the
coefficients that control the flow, such as volume control, filter
coefficients, and enable bits.
GRAPHICAL PROGRAMMING ENVIRONMENT
Custom flows for the ADAV4622 are created in a powerful
drag-and-drop graphical programming application. No knowledge of assembly code is required to program the ADAV4622.
Featuring a comprehensive library of audio processing blocks
(such as filters, delays, dynamics processors, and third-party
algorithms), it allows the quick and simple creation of custom
flows. For debugging purposes, run-time control of the audio
flow allows the user to fully configure and test the created flow.
Training materials and support are available upon request.
Contact a local Analog Devices sales representative for more
details.
APPLICATION LAYER
Unique to this family is the embedded application layer, which
allows the user to define a custom set of registers to control the
audio flow, greatly simplifying the interface between the audio
processor and the system controller.
Once a custom flow is created, a user-customized register map
can be defined for controlling the flow. Each register is 16 bits,
but controls can use only one bit or all 16 bits. Users have full
control over which parameters they control and the degree of
control they have over those parameters during run time. The
combination of the graphical programming environment and
the powerful application layer allows the user to quickly develop
a custom audio flow and still maintain the usability of a simple
register-based device.
Comprehensive documentation on developing a custom audio
flow and the definition and creation of the custom application
layer for the ADAV4622 is available upon request. Contact a
local Analog Devices sales representative for more details.
Rev. B | Page 25 of 28
ADAV4622
LOADING A CUSTOM AUDIO PROCESSING FLOW
The ADAV4622 can load a custom audio flow from an external
2
C ROM. The boot process is initiated by a simple control
I
register write. The EEPROM device address and the EEPROM
start address for the audio flow ROMs can all be programmed.
For the duration of the boot sequence, the ADAV4622 becomes
the master on the I
2
C bus. Transfer of the ROMs from the
EEPROM to the ADAV4622 takes a maximum of 1.06 sec,
assuming that the full audio processor memor y is required,
during which time no other devices should access the I
2
C bus.
Once the transfer is complete, the ADAV4622 automatically
reverts to slave mode, and the I
2
C bus master can resume
sending commands.
AUDIO
PROCESSOR
ADDRESS
AUDIO
PROCESSOR
LOAD
ON
RESET
MEMORY
DEFAULT
CODE
COMMAND
I2C PORT
CUSTOM
CODE
DATA
BOOT- UP
ROM
EXTERNAL
BOOT- UP ROM
47260 BYTES (MAX )
Figure 33. External EEPROM Booting
LOAD
ON
7068-030
Rev. B | Page 26 of 28
ADAV4622
SDIN2/SRC2
CHANNEL B
SDIN3/SRC2
CHANNEL C
S
RC1
RC2
S
CHANNEL A
SIF
DELAY
AUXIN1L
AUXIN1R
AUXIN2L
AUXIN2R
SDIN0
SDIN1
SRC DELAY
SUB
CHANNEL
MUTE
MUTE
LPF
MUTE
MUTE
MUTE
PWM1
(LHIGH)
PWM2
(RHIGH)
PWM3
(LLOW)
PWM4
(RLOW)
SUB
CHANNEL
TO INPUT
MUXES
HPOUT1L/
AUXOUT4L
HPOUT1R/
AUXOUT4R
AUXOUT2L/
HPOUT2L
AUXOUT2R/
HPOUT2R
S/PDIF OUTL
(SDOL1)
S/PDIF OUTR
(SDOR1)
MUX
TRIM
MAIN MUX
TRIM
SRC1 MUTE
SRC2 MUTE
HP MUX
MUX
TRIM
AUXOUT2
TRIM
S/PDIF MUX
AVC
LIP SYNC
7-BAND EQ
LOUDNESS
SPATIALIZER
BEEPER
BALANCE
7-BAND EQ
LOUDNESS
VOLUME
TRIM
8-BAND EQ
CROSSOVER
CROSSOVER
TRIM
CROSSOVER
DYNAMIC BASS
VOLUME CO NTROL
BALANCE BALANCE
+
LIMITER
LIMITER
+
(L + R)/2
AUXOUT1L
MUX
TRIM
AUXOUT1
MUX
SDO0
TRIM
MUX
AUXOUT3
MUTE
MUTE
MUTE
AUXOUT1R
SDOL0
SDOR0
AUXOUT3L
AUXOUT3R
07068-031
Figure 34. Default Audio Processing Flow
Rev. B | Page 27 of 28
ADAV4622
OUTLINE DIMENSIONS
16.20
PIN 1
16.00 SQ
15.80
61
60
0.75
0.60
0.45
1.60
MAX
80
1
14.20
14.00 SQ
13.80
41
40
051706-A
1.45
1.40
1.35
0.15
SEATING
0.05
PLANE
VIEW A
ROTATED 90° CCW
0.20
0.09
7°
3.5°
0°
0.10
COPLANARITY
COMPLIANT TO JEDEC STANDARDS MS-026-BEC
VIEW A
20
21
TOP VIEW
(PINS DOWN)
0.65
BSC
LEAD PITCH
0.38
0.32
0.22
Figure 35. 80-Lead Low Profile Quad Flat Package [LQFP]
(ST-80-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range SIF Standard Package Description Package Option
ADAV4622BSTZ1 −40°C to +85°C PAL/NTSC/SECAM 80-Lead Low Profile Quad Flat Package (LQFP) ST-80-2
EVAL-ADAV4622EBZ1 Evaluation Board
1
Z = RoHS Compliant Part.
In addition, it is backward compatible with conventional SnPb soldering processes. This means the electroplated Sn coating can be soldered with Sn/Pb solder pastes
at conventional reflow temperatures of 220°C to 235°C.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I
2
C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07068-0-7/09(B)
Rev. B | Page 28 of 28
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