ANALOG DEVICES ADAV4601 Service Manual

Audio Processor for Advanced TV

FEATURES

Fully programmable 28-bit audio processor for enhanced

ATV sound—default audio processing flow loaded on reset

Implements Analog Devices, Inc. and third-party branded

audio algorithms

Adjustable digital delay line for audio/video

Synchronization for up to 200 ms stereo delay

High performance 24-bit ADC and DAC

94 dB DNR performance on DAC channels

95 dB DNR performance on ADC channels
Headphone output with integrated amplifiers
High performance pulse-width modulation (PWM) digital

outputs
Multichannel digital baseband I/O

4 stereo synchronous digital I

One 6-channel sample rate converter (SRC) and one stereo

SRC supporting input sample rates from 5 kHz to 50 kHz
One stereo synchronous digital I
S/PDIF output with S/PDIF input mux capability

2

Fast I

C control

Operates from 3.3 V (analog), 1.8 V (digital core), and 3.3 V

(digital interface)

Available in 80-lead LQFP

APPLICATIONS

General-purpose consumer audio post processing

Home audio
DVD recorders

Home theater in a box systems and DVD receivers
Audio processing subsystems for DTV-ready TVs
Analog broadcast capability for iDTVs

2

S input channels

2

S output

ADAV4601

GENERAL DESCRIPTION

The ADAV4601 is an enhanced audio processor targeting
advanced TV applications with full support for digital and
analog baseband audio.

The audio processor, by default, loads a dedicated TV audio flow
that incorporates full matrix switching (any input to any output),
automatic volume control that compensates for volume changes
during advertisements or when switching channels, dynamic
bass, a multiband equalizer, and up to 200 ms of stereo delay
memory for audio-video synchronization.

Alternatively, Analog Devices offers an award-winning graphical
programming tool (SigmaStudio™) that allows custom flows to be
quickly developed and evaluated. This allows the creation of
customer-specific audio flows, including the use of ADI library of
third-party algorithms.

The analog I/O integrates Analog Devices proprietary continuous­time, multibit Σ- architecture to bring a higher level of
performance to ATV systems, required by third-party algorithm
providers to meet system branding certification. The analog input
is provided by 95 dB dynamic range (DNR) ADCs, and analog
output is provided by 94 dB DNR DACs.

The main speaker outputs can be supplied as a digitally modulated
PWM stream to support digital amplifiers.

The ADAV4601 includes multichannel digital inputs and outputs.
In addition, digital input channels can be routed through integrated
sample rate converters (SRC), which are capable of supporting any
arbitrary sample rate from 5 kHz to 50 kHz.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of p atents or other
rights of third parties that may result from its use. Specifications subject to chan ge without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008–2009 Analog Devices, Inc. All rights reserved.

ADAV4601

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

Specifications ..................................................................................... 5

Performance Parameters ............................................................. 5

Timing Specifications .................................................................. 7

Timing Diagrams .......................................................................... 8

Absolute Maximum Ratings ............................................................ 9

Thermal Resistance ...................................................................... 9

Thermal Conditions ..................................................................... 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 12

Terminology .................................................................................... 14

Pin Functions .................................................................................. 15

Detailed Pin Descriptions ......................................................... 15

Functional Descriptions ................................................................ 17

Power-Up Sequence ................................................................... 17

Master Clock Oscillator ............................................................. 17

I2C Interface ................................................................................ 17

I2C Read and Write Operations ................................................ 19

ADC Inputs ................................................................................. 19

I2S Digital Audio Inputs ............................................................. 20

DAC Voltage Outputs ................................................................ 22

PWM Outputs ............................................................................ 22

Headphone Output .................................................................... 22

I2S Digital Audio Outputs ......................................................... 23

S/PDIF Input/Output ................................................................. 23

Hardware Mute Control ............................................................ 23

Audio Processor ......................................................................... 23

Graphical Programming Environment ................................... 23

SigmaStudio Pin Assignment ................................................... 24

Application Layer ....................................................................... 24

Loading a Custom Audio Processing Flow ............................. 24

Numeric Formats ....................................................................... 24

ROMs and Registers ................................................................... 25

Safe Loading to Parameter RAM and Target/Slew RAM ...... 25

Read/Write Data Formats ......................................................... 25

Target/Slew RAM ....................................................................... 26

Layout Recommendations ........................................................ 28

Typical Application Diagram ........................................................ 29

Audio Flow Control Registers....................................................... 31

Detailed Register Descriptions ................................................. 31

Main Control Registers .................................................................. 48

Detailed Register Descriptions ................................................. 48

Outline Dimensions ....................................................................... 58

Ordering Guide .......................................................................... 58

Rev. B | Page 2 of 60

ADAV4601

REVISION HISTORY

9/09—Rev. A to Rev. B

Changes to Table 11 ........................................................................ 24

Changes to Table 15 ........................................................................ 31

Changes to Table 16 ........................................................................ 32

Changes to Table 40 ........................................................................ 45

Changes to Table 50 ........................................................................ 51

Changes to Table 51 ........................................................................ 53

Changes to Table 54 ........................................................................ 54

4/09—Rev. 0 to Rev. A

Added Advantiv Logo ....................................................................... 1

Changes to General Description Section ....................................... 1

Changes to Figure 1 ........................................................................... 3

Changes to Table 2 ............................................................................ 6

Changes to FILTA and FILTD Section, AVDD Section, and

VDD Section .................................................................................... 15

Added Power-Up Sequence Section and Figure 22;

Renumbered Sequentially .............................................................. 16

Changes to Master Clock Oscillator Section ............................... 16

Added Table 6, Table 7, Table 8, Table 9, and Figure 23;

Renumbered Sequentially .............................................................. 17

Added Figure 24 .............................................................................. 18

Changes to ADC Inputs Section and Figure 25 .......................... 18

Added Figure 31 .............................................................................. 21

Changes to DAC Voltage Outputs Section, Figure 30, PWM
Outputs Section, Headphone Output Section, and Figure 33 ... 21

Added Figure 36 .............................................................................. 22

Changes to Hardware Mute Control Section .............................. 22

Added SigmaStudio Pin Assignment Section, Table 10, Table 11,

and Numeric Formats Section ....................................................... 23

Changes to Application Layer Section ......................................... 23

Added Figure 38, ROMs and Registers Section, Safe Loading to
Parameter RAM and Target/Slew RAM Section, and Read/Write

Data Formats Section ..................................................................... 24

Added Target/Slew RAM Section, Table 12, Table 13, and

Table 14 ............................................................................................. 25

Added Figure 39, Figure 40, Figure 41, Figure 42, and

Figure 43 ........................................................................................... 26

Added Figure 44, Figure 45, Figure 46, and Layout

Recommendations Section ............................................................ 27

Changes to Figure 47 ...................................................................... 28

Added Figure 48 .............................................................................. 29

Added Table 15 to Table 61 ............................................................ 30

3/08—Revision 0: Initial Version

Rev. B | Page 3 of 60

ADAV4601

FUNCTIONAL BLOCK DIAGRAM

MCLK_OUT

MCLKI/XIN

XOUT

SCL

SDA

MUTE

BCLK2

LRCLK2

BCLK0

LRCLK0

SDIN0
SDIN1
SDIN2
SDIN3

AUXIN1L

AUXIN1R

BCLK1

LRCLK1

AD0

ADAV4601

PLL

I2C INTERFACE

SYSTEM
CLOCKS

ASYNCHRONOUS

ASYNCHRONOUS

2-CHANNEL SRC

DIGITAL INPUT

6-CHANNEL SRC

DIGITAL INPUT

SYNCHRONOUS
MULTICHANNEL
DIGITAL INPUTS

ADC

AUDIO

PROCESSOR

A-V

SYNCHRONOUS

DELAY

MEMORY

DIGITAL

OUTPUTS

S/PDIF I/O

PWM
DIGITAL
OUTPUT

DAC

DAC

DAC

SDO0/AD0

BCLK1
LRCLK1

SPDIF_IN0
SPDIF_IN1
SPDIF_IN2
SPDIF_IN3
SPDIF_IN4
SPDIF_IN5
SPDIF_IN6

SPDIF_OUT/SDO1

PWM1A
PWM1B
PWM2A
PWM2B
PWM3A
PWM3B
PWM4A
PWM4B

PWM_READY

AUXOUT1L
AUXOUT1R

AUXOUT4L
AUXOUT4R

HPOUT1L

HPOUT1R

AUXOUT3L
AUXOUT3R

07070-001

Figure 1. ADAV4601 with PWM-Based Speaker Outputs

Rev. B | Page 4 of 60

ADAV4601

SPECIFICATIONS

AVDD = 3.3 V, DVDD = 1.8 V, ODVDD = 3.3 V, operating temperature = −40°C to +85°C, master clock 24.576 MHz, measurement
bandwidth = 20 Hz to 20 kHz, ADC input signal = DAC output signal = 1 kHz, unless otherwise noted.

PERFORMANCE PARAMETERS

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE SECTION

Absolute Voltage V
V

Temperature Coefficient 100 ppm/°C

REF

ADC SECTION

Number of Channels 2 One stereo channel
Full-Scale Input Level 100 μA rms
Resolution 24 Bits
Dynamic Range (Stereo Channel)

A-Weighted 95 dB −60 dBFS with respect to full-scale analog input

Total Harmonic Distortion + Noise

(Stereo Channel)
Gain Mismatch 0.2 dB Left- and right-channel gain mismatch
Crosstalk (Left-to-Right, Right-to-Left) −110 dB
Gain Error −1 dB Input signal is 100 μA rms
Current Setting Resistor (R

Power Supply Rejection −87 dB 1 kHz, 300 mV p-p signal at AVDD

ADC DIGITAL DECIMATOR FILTER

CHARACTERISTICS
Pass Band 22.5 kHz
Pass-Band Ripple ±0.0002 dB
Stop Band 26.5 kHz
Stop-Band Attenuation 100 dB
Group Delay 1040 μs

PWM SECTION

Frequency 384 kHz Guaranteed by design
Modulation Index 0.976 Guaranteed by design
Dynamic Range

A-Weighted 98 dB −60 dBFS with respect to full-scale code input
Total Harmonic Distortion + Noise −80 dB −3 dBFS with respect to full-scale code input

DAC SECTION

Number of Auxiliary Output Channels 6 Three stereo channels
Resolution 24 Bits
Full-Scale Analog Output 1 V rms
Dynamic Range

A-Weighted 94 dB −60 dBFS with respect to full-scale code input
Total Harmonic Distortion + Noise −86 dB −3 dBFS with respect to full-scale code input
Crosstalk (Left-to-Right, Right-to-Left) −102 dB
Interchannel Gain Mismatch 0.1 dB Left- and right-channel gain mismatch
Gain Error 0.525 dB 1 V rms output
DC Bias 1.53 V
Power Supply Rejection −90 dB 1 kHz, 300 mV p-p signal at AVDD
Output Impedance 235 Ω

1.53 V

REF

−90 dB −3 dBFS with respect to full-scale analog input

) 20 kΩ

ISET

External resistor to set current input range of ADC
for nominal 2.0 V rms input signal

At 48 kHz, guaranteed by design

Rev. B | Page 5 of 60

ADAV4601

Parameter Min Typ Max Unit Test Conditions/Comments

DAC DIGITAL INTERPOLATION FILTER

CHARACTERISTICS

Pass Band 21.769 kHz
Pass-Band Ripple ±0.01 dB
Transition Band 23.95 kHz
Stop Band 26.122 kHz
Stop-Band Attenuation 75 dB
Group Delay 580 μs

HEADPHONE AMPLIFIER Measured at headphone output with 32 Ω load

Number of Channels 2 One stereo channel
Full-Scale Output Power 31 mW rms 1 V rms output
Dynamic Range

A-Weighted 93 dB −60 dBFS with respect to full-scale code input
Total Harmonic Distortion + Noise −83 dB −3 dBFS with respect to full-scale code input
Interchannel Gain Mismatch 0.1 dB
DC Bias 1.53 V
Power Supply Rejection −85 dB 1 kHz, 300 mV p-p signal at AVDD

SRC

Number of Channels 8 Two channels (SRC1), six channels (SRC2)
Dynamic Range

A-Weighted 115 dB −60 dBFS input (worst-case input fS = 50 kHz)
Total Harmonic Distortion + Noise −113 dB −3 dBFS input (worst-case input fS = 50 kHz)
Sample Rate 5 50 kHz

SRC DIGITAL INTERPOLATION FILTER

CHARACTERISTICS

Pass Band 21.678 kHz
Pass-Band Ripple 0.005 dB
Stop Band 26.232 kHz
Stop-Band Attenuation 110 dB
Group Delay 876 μs

DIGITAL INPUT/OUTPUT

Input Voltage High (VIH) 2.0 ODVDD V
Input Voltage Low (VIL) 0.8 V
Input Leakage

I

(SDIN0, SDIN1, SDIN2, SDIN3,

IH

LRCLK0, LRCLK1, LRCLK2, BCLK0,

BCLK1, BCLK2, SPDIF_OUT, SPDIF_IN)
IIH (RESET)
IIL (SDO0, SCL, SDA) −40 μA VIL = 0 V, equivalent to a 90 kΩ pull-down resistor

Output Voltage High (VOH) 2.4 V IOH = 0.4 mA
Output Voltage Low (VOL) 0.4 V IOL = −2 mA
Output Voltage High (VOH) (MCLK_OUT) 1.4 V IOH = 0.4 mA
Output Voltage Low (VOL) (MCLK_OUT) 0.4 V IOL = −3.2 mA
Input Capacitance 10 pF

SUPPLIES

Analog Supplies (AVDD) 3.0 3.3 3.6 V
Digital Supplies (DVDD) 1.65 1.8 2.0 V
Interface Supply (ODVDD) 3.0 3.3 3.6 V
Supply Currents

Analog Current 115 mA
Digital Current 160 mA
Interface Current 2 mA

At 48 kHz, guaranteed by design

At 48 kHz, guaranteed by design

40 μA V

13.5 μA V

= ODVDD, equivalent to a 90 kΩ pull-up resistor

IH

= ODVDD, equivalent to a 266 kΩ pull-up resistor

IH

MCLK = 24 MHz, ADCs and DACs active, headphone
outputs active and driving a 16 Ω load

Rev. B | Page 6 of 60

ADAV4601

Parameter Min Typ Max Unit Test Conditions/Comments

Power Dissipation 0.674 W

Standby Currents

Analog Current 7 mA
Digital Current 3 mA
Interface Current 1.6 mA

TEMPERATURE RANGE

Operating Temperature −40 +85 °C

Storage Temperature −65 +150 °C

TIMING SPECIFICATIONS

Table 2.

Parameter Description Min Max Unit Comments

MASTER CLOCK AND RESET

f

MCLKI frequency 3.072 24.576 MHz

MCLKI

tMP MCLKI period 40 325 ns

t

MCLKI high 10 ns

MCH

t

MCLKI low 10 ns

MCL

t

RESET

MASTER CLOCK OUTPUT

tCK MCLK_OUT period 8 162 ns

t

JIT

tCH MCLK_OUT high 45 55 %

tCL MCLK_OUT low 45 55 %
I2C PORT

f

SCL clock frequency 400 kHz

SCL

t

SCL high 600 ns

SCLH

t

SCL low 1.3 μs

SCLL

Start Condition

t

Setup time 600 ns Relevant for repeated start condition

SCS

t

Hold time 600 ns After this period, the first clock is generated

SCH

tDS Data setup time 100 ns
t

SCL rise time 300 ns

SCR

t

SCL fall time 300 ns

SCF

t

SDA rise time 300 ns

SDR

t

SDA fall time 300 ns

SDF

Stop Condition

t

Setup time 0 ns

SCS

SERIAL PORTS

Slave Mode

t

BCLK high 40 ns

SBH

t

BCLK low 40 ns

SBL

f

BCLK frequency 64 × fS

SBF

t

LRCLK setup 10 ns To BCLK rising edge

SLS

t

LRCLK hold 10 ns From BCLK rising edge

SLH

t

SDIN setup 10 ns To BCLK rising edge

SDS

t

SDIN hold 10 ns From BCLK rising edge

SDH

t

SDO delay 50 ns From BCLK falling edge

SDD

Master Mode

t

LRCLK delay 25 ns From BCLK falling edge

MLD

t

SDO delay 15 ns From BCLK falling edge

MDD

t

SDIN setup 10 ns From BCLK rising edge

MDS

t

SDIN hold 10 ns From BCLK rising edge

MDH

RESET low

200 ns

Period jitter 800 ps

Rev. B | Page 7 of 60

ADC, DAC, and headphone outputs floating,

low, MCLK = 24 MHz

RESET

ADAV4601

V

V

TIMING DIAGRAMS

t

= 1/

f

MP

MCLKI

MCLKI

RESET

t

RESET

Figure 2. Master Clock and Reset Timing

DVDD

t

MCH

t

MCL

07070-004

t

JIT

GND

t

CH

t

CK

t

CL

07070-035

Figure 3. Master Clock Output Timing

t

LRCLK1

BCLK1

SDINx

SDO0

LRCLK1

BCLK1

SDINx

SDO0

SLH

t

SLS

t

t

SDH

SDS

t

SDD

Figure 4. Serial Port Slave Mode Timing

t

MLD

t

t

MDH

MDS

t

MDD

Figure 5. Serial Port Master Mode Timing

DVDD

AVDD

ODVDD

07070-002

0.18V

1.0s MAX

0.33V

1.0s MAX

1.65V

3.0V

Figure 7. Power-Up Sequence Timing

DVDD

AVDD

ODVDD

07070-003

1.65V

0.18V

1.0s MAX

3.0V

0.33V

1.0s MAX

Figure 8. Power-Down Sequence Timing

1.8

0V

3.3V

0V

7070-033

1.8

0V

3.3V

0V

07070-034

100µA I

OL

TO OUTPUT

PIN

50pF

100µA I

Figure 6. Load Circuit for Digital Output Timing Specifications

ODVDD

OH

07070-032

Rev. B | Page 8 of 60

ADAV4601

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

DVDD to DGND 0 V to 2.2 V
ODVDD to DGND 0 V to 4 V
AVDD to AGND 0 V to 4 V
AGND to DGND −0.3 V to +0.3 V
Digital Inputs DGND − 0.3 V to ODVDD + 0.3 V
Analog Inputs AGND − 0.3 V to AVDD + 0.3 V
Reference Voltage Indefinite short circuit to ground
Soldering (10 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Thermal resistance is based on JEDEC 2S2P PCB.

Table 4.

Package Type θJA θ

80-Lead LQFP 38.1 7.6 °C/W

Unit

JC

THERMAL CONDITIONS

To ensure correct operation of the device, the case temperature
(T

) must be kept below 121°C to keep the junction temperature

CASE

(T

) below the maximum allowed, 125°C.

J

ESD CAUTION

Rev. B | Page 9 of 60

ADAV4601

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ISET

AUXIN1R

AUXIN1LNCNCNCNC

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

AUXOUT1R

AUXOUT1L

AVDD

AGND

AGND

AVDD

FILTDNCAUXOUT4R

AUXOUT4L

AUXOUT3R

AUXOUT3L

NC

FILTA

VREF

AGND

AVDD

DGND

DVDD

MUTE

SDA

SCL

SPDIF_IN5/ LRCLK2

SPDIF_IN6/ BCLK2

DGND

NC = NO CONNECT

NC

NC

NC

NC

NC

NC

NC

NC

1

PIN 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

DVDD

25

SDIN023SDIN124SDIN2

SPDIF_IN0/ SDIN3

26

27

SPDIF_IN1/LRCLK0

ADAV4601

(Not to Scale)

28

29

ODGND

SPDIF_IN2/BCLK0

TOP VIEW

30

31

DVDD

ODVDD

MCLK_OUT

32

33

34

35

36

37

38

XOUT

DGND

MCLKI/XIN

SDO0/AD0

SPDIF_IN4/BCLK1

SPDIF_OUT/SDO1

SPDIF_IN3/LRCLK1

60

NC

59

AVDD

58

HPOUT1R

57

HPOUT1L

56

AGND

55

AGND

54

PLL_LF

53

AVDD

52

DGND

51

DVDD

50

RESET

49

PWM4B

48

PWM4A

47

PWM3B

46

PWM3A

45

PWM2B

44

PWM2A

43

PWM1B

42

PWM1A

41

DGND

39

40

DVDD

PWM_READY

07070-006

Figure 9. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 FILTA ADC Filter Capacitor.
2 VREF Reference Capacitor.
3 AGND
4 AVDD
5 to 12 NC
13 DGND
14 DVDD
15

MUTE
16 SDA
17 SCL
18 SPDIF_IN5/LRCLK2
19 SPDIF_IN6/BCLK2
20 DGND
21 DVDD
22 SDIN0
23 SDIN1

ADC Ground.
ADC Supply (3.3 V).
No Connection to This Pin Allowed.
Digital Ground.
Digital Supply (1.8 V).
Active-Low Mute Request Input Signal.

I2C Data.
I2C Clock.
External Input to S/PDIF Mux/Left/Right Clock for SRC2 (Default).
External Input to S/PDIF Mux/Bit Clock for SRC2 (Default).
Digital Ground.
Digital Supply (1.8 V).
Serial Data Input 0/SRC Data Input.
Serial Data Input 1/SRC Data Input.

24 SDIN2 Serial Data Input 2/SRC Data Input.

Rev. B | Page 10 of 60

ADAV4601

Pin No. Mnemonic Description

25 SPDIF_IN0/SDIN3 External Input to S/PDIF Mux/SRC Data Input/Serial Data Input 3 (Default).
26 SPDIF_IN1/LRCLK0
27 SPDIF_IN2/BCLK0
28 ODGND Digital Ground.
29 ODVDD Digital Interface Supply (3.3 V).
30 MCLK_OUT Master Clock Output.
31 DVDD Digital Supply (1.8 V).
32 DGND Digital Ground.
33 MCLKI/XIN Master Clock/Crystal Input.
34 XOUT Crystal Output.
35 SPDIF_IN4/BCLK1 External Input to S/PDIF Mux/Bit Clock for Serial Data I/O (Default).
36 SPDIF_IN3/LRCLK1 External Input to S/PDIF Mux/Left/Right Clock for Serial Data I/O (Default).
37 SDO0/AD0 Serial Data Output. This pin acts as the I2C address select on reset. It has an internal pull-down resistor.
38 SPDIF_OUT/SDO1 Output of S/PDIF Mux/Serial Data Output.
39 PWM_READY PWM Ready Flag.
40 DVDD Digital Supply (1.8 V).
41 DGND Digital Ground.
42 PWM1A
43 PWM1B
44 PWM2A
45 PWM2B
46 PWM3A
47 PWM3B
48 PWM4A
49 PWM4B
50

RESET
51 DVDD Digital Supply (1.8 V).
52 DGND Digital Ground.
53 AVDD PLL Supply (3.3 V).
54 PLL_LF PLL Loop Filter.
55 AGND PLL Ground.
56 AGND Headphone Driver Ground.
57 HPOUT1L Left Headphone Output.
58 HPOUT1R Right Headphone Output.
59 AVDD Headphone Driver Supply (3.3 V).
60, 61 NC
62 AUXOUT3L
63 AUXOUT3R
64 AUXOUT4L
65 AUXOUT4R
66 NC
67 FILTD DAC Filter Capacitor.
68 AVDD DAC Supply (3.3 V).
69 AGND DAC Ground.
70 AGND DAC Ground.
71 AVDD DAC Supply (3.3 V).
72 AUXOUT1L
73 AUXOUT1R
74 to 77 NC
78
79

AUXIN1L

AUXIN1R
80 ISET ADC Current Setting.

External Input to S/PDIF Mux/Left/Right Clock for SRC1 (Default).
External Input to S/PDIF Mux/Bit Clock for SRC1 (Default).

Pulse-Width Modulated Output 1A.
Pulse-Width Modulated Output 1B.
Pulse-Width Modulated Output 2A.
Pulse-Width Modulated Output 2B.
Pulse-Width Modulated Output 3A.
Pulse-Width Modulated Output 3B.
Pulse-Width Modulated Output 4A.
Pulse-Width Modulated Output 4B.
Reset Analog and Digital Cores.

No Connection to This Pin Allowed.
Left Auxiliary Output 3.
Right Auxiliary Output 3.
Left Auxiliary Output 4.
Right Auxiliary Output 4.
No Connection to This Pin Allowed.

Left Auxiliary Output 1.
Right Auxiliary Output 1.
No Connection to This Pin Allowed.
Left Auxiliary Input 1.
Right Auxiliary Input 1.

Rev. B | Page 11 of 60

ADAV4601

TYPICAL PERFORMANCE CHARACTERISTICS

0

–20

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

–180

07

192 384 576

FREQUENCY (kHz)

68

07070-007

Figure 10. DAC Composite Filter Response (48 kHz)

0

–30

–60

–90

–120

–150

–180

MAGNITUDE (dB)

–210

–240

–270

–300

03

128 256 84

FREQUENCY (kHz)

07070-010

Figure 13. ADC Composite Filter Response (48 kHz)

0

–20

–40

–60

–80

–100

MAGNITUDE (dB)

–120

–140

–160

09

24 48 72

FREQUENCY (kHz)

6

07070-008

Figure 11. DAC Pass-Band Filter Response (48 kHz)

0.6

0.4

0.2

0

MAGNITUDE (d B)

–0.2

–0.4

0

–30

–60

–90

MAGNITUDE (dB)

–120

–150

–180

09

Figure 14. ADC Pass-Band Filter Response (48 kHz)

0.04

0.03

0.02

0.01

0

–0.01

MAGNITUDE (d B)

–0.02

–0.03

24 48 72 6

FREQUENCY (kHz)

07070-011

–0.6

02

816 4

FREQUENCY (kHz)

07070-009

Figure 12. DAC Pass-Band Ripple (48 kHz)

–0.04

02

Figure 15. ADC Pass-Band Ripple (48 kHz)

Rev. B | Page 12 of 60

816 4

FREQUENCY (kHz)

07070-012

ADAV4601

0

0

–20

–40

–60

–80

–100

MAGNITUDE (d BV)

–120

–140

–160

0 20000

4000 8000 12000 16000

FREQUENCY (Hz)

Figure 16. DAC Dynamic Range

0

–20

–40

–60

–80

–100

MAGNITUDE (dBV)

–120

–140

–160

0 20000

4000 8000 12000 16000

FREQUENCY (Hz)

Figure 17. DAC Total Harmonic Distortion + Noise

0

–20

–20

–40

–60

–80

–100

MAGNITUDE (dBV)

–120

–140

–160

0 20000

07070-013

4000 8000 12000 16000

FREQUENCY (Hz)

07070-016

Figure 19. ADC Total Harmonic Distortion + Noise

0

–20

–40

–60

–80

GAIN (dB)

–100

–120

–140

010.90.80.70.60.50. 40.30.20. 1

7070-014

NORMALIZE D FREQUENCY

.0

07070-017

Figure 20. Sample Rate Converter Transfer Function

–40

–60

–80

–100

MAGNITUDE (dBV)

–120

–140

–160

0 20000

4000 8000 12000 16000

FREQUENCY (Hz)

07070-015

Figure 18. ADC Dynamic Range

Rev. B | Page 13 of 60

ADAV4601

TERMINOLOGY

Dynamic Range

The ratio of a full-scale input signal to the integrated input noise
in the pass band (20 Hz to 20 kHz), expressed in decibels (dB).
Dynamic range is measured with a −60 dB input signal and is equal
to (S/[THD+N]) + 60 dB. Note that spurious harmonics are below
the noise with a −60 dB input; therefore, the noise level establishes
the dynamic range. The dynamic range is specified with and
without an A-weight filter applied.

Pass Band

The region of the frequency spectrum unaffected by the
attenuation of the filter of the digital decimator.

Pass-Band Ripple

The peak-to-peak variation in amplitude response from equal
amplitude input signal frequencies within the pass band,
expressed in decibels.

Stop Band

The region of the frequency spectrum attenuated by the filter
of the digital decimator to the degree specified by stop-band
attenuation.

Gain Error

With a near full-scale input, the ratio of the actual output to the
expected output, expressed in dB.

Interchannel Gain Mismatch

With identical near full-scale inputs, the ratio of the outputs of
the two stereo channels, expressed in decibels.

Crosstalk

Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine wave input on the other channel, expressed
in decibels.

Power Supply Rejection

With no analog input, the signal present at the output when a
300 mV p-p signal is applied to power supply pins, expressed in
decibels of full scale.

Group Delay

Intuitively, the time interval required for an input pulse to appear at
the output of the converter, expressed in milliseconds (ms); more
precisely, the derivative of radian phase with respect to radian
frequency at a given frequency.

Rev. B | Page 14 of 60

ADAV4601

PIN FUNCTIONS

DETAILED PIN DESCRIPTIONS

Tabl e 5 shows the pin numbers, mnemonics, and descriptions
for the ADAV4601. The input pins have a logic threshold
compatible with 3.3 V input levels.

SDIN0, SDIN1, SDIN2, and SDIN3/SPDIF_IN0

Serial data inputs. These input pins provide the digital audio
data to the signal processing core. Any of the inputs can be
routed to either of the SRCs for conversion; this input is then
not available as a synchronous input to the audio processor but
only as an input through the selected SRC. The serial format for
the synchronous data is selected by Bits[3:2] of the Serial Port
Control Register 1. If the SRCs are required, the serial format is
selected by Bits[12:9] of the same register. The synchronous inputs
are capable of using any pair of serial clocks, LRCLK0/BCLK0,
LRCLK1/BCLK1, or LRCLK2/BCLK2. By default, they use
LRCLK1 and BCLK1. See Figure 26 for more details regarding
the configuration of the synchronous inputs.

SDIN3 is a shared pin with SPDIF_IN0. If SDIN3 is not in use, this
pin can be used to connect an S/PDIF signal from an external
source, such as an MPEG decoder, to the ADAV4601 on-chip
S/PDIF output multiplexer. If SPDIF_OUT is selected from one
of the SPDIF_IN (external) signals, the signal is simply passed
through from input to output.

LRCLK0/SPDIF_IN1, BCLK0/SPDIF_IN2, LRCLK1/SPDIF_IN3, BCLK1/SPDIF_IN4, LRCLK2/SPDIF_IN5, and BCLK2/SPDIF_IN6

By default, LRCLK1 and BCLK1 are associated with the
synchronous inputs, LRCLK0 and BCLK0 are associated with
SRC1, and LRCLK2 and BCLK2 are associated with SRC2.
However, the SRCs and synchronous inputs can use any of
the serial clocks (see Figure 26). LRCLK0, BCLK0, LRCLK1,
BCLK1, LRCLK2, and BCLK2 are shared pins with SPDIF_IN1,
SPDIF_IN2, SPDIF_IN3, SPDIF_IN4, SPDIF_IN5, and
SPDIF_IN6, respectively. If LRCLK0/LRCLK1/ LRCLK2 or
BCLK0/BCLK1/BCLK2 are not in use, these pins can be used
to connect an S/PDIF signal from an external source, such as an
MPEG decoder, to the ADAV4601 on-chip S/PDIF output
multiplexer. If SPDIF_OUT is selected from one of the SPDIF_IN
(external) signals, the signal is simply passed through from input
to output.

SDO0/AD0

Serial data output. This pin can output two channels of digital
audio using a variety of standard 2-channel formats. The clocks
for SDO0 are always the same as those used by the synchronous
inputs; therefore, LRCLK1 and BCLK1 are used by default,
although SDO0 is capable of using any pair of serial clocks,
LRCLK0/BCLK0, LRCLK1/BCLK1, or LRCLK2/BCLK2.
The Serial Port Control Register 1 selects the serial format for the
synchronous output. On reset, the SDO0 pin duplicates as the

2

I

C® address select pin. In this mode, the logical state of the pin
is polled for four MCLKI cycles following reset. The address
select bit is set as the majority poll of the logic level of the pin after
the four MCLKI cycles.

SPDIF_OUT/SDO1

The ADAV4601 contains an S/PDIF multiplexer functionality that
allows the SPDIF_OUT signal to be chosen from an internally
generated S/PDIF signal or from the S/PDIF signal of an external
source, which is connected via one of the SPDIF_IN pins. This pin
can also be configured as an additional serial output (SDO1) as an
alternate function.

MCLKI/XIN

Master clock input. The ADAV4601 uses a PLL to generate the
appropriate internal clock for the audio processing core. A clock
signal of a suitable frequency can be connected directly to this pin,
or a crystal can be connected between MCLKI/XIN and XOUT
together with the appropriate capacitors to DGND to generate
a suitable clock signal.

XOUT

This pin is used in conjunction with MCLKI/XIN to generate a
clock signal for the ADAV4601.

MCLK_OUT

This pin can be used to output MCLKI or one of the internal
system clocks. Note that the output level of this pin is referenced to
DVDD (1.8 V) and not ODVDD (3.3 V) like all the other digital
inputs and outputs.

SDA

Serial data input for the I2C control port. SDA features a glitch
elimination filter that removes spurious pulses that are less than
50 ns wide.

Rev. B | Page 15 of 60

ADAV4601

SCL

Serial clock for the I2C control port. SCL features a glitch
elimination filter that removes spurious pulses that are
less than 50 ns wide.

MUTE

Mute input request. This active-low input pin controls the
muting of the output ports (both analog and digital) from the
ADAV4601. When low, it asserts mute on the outputs that are
enabled in the audio flow.

RESET

Active-low reset signal. After
are powered down. The blocks can be individually powered up
with software. When the part is powered up, it takes approximately
3072 internal clocks to initialize the internal circuitry. The internal
system clock is equal to MCLKI until the PLL is powered and
enabled, after which the internal system clock becomes 2560 × f
(122.88 MHz). When the PLL is powered up and enabled after
reset, it takes approximately 3 ms to lock. When the audio
processor is enabled, it takes approximately 32,768 internal system
clocks to initialize and load the default flow to the audio processor
memory. The audio processor is not available during this time.

RESET

goes high, the circuit blocks

AUXIN1L AND AUXIN1R

Analog inputs to the on-chip ADCs.

AUXOUT1L, AUXOUT1R, AUXOUT3L, AUXOUT3R, AUXOUT4L, and AUXOUT4R

Auxiliary DAC analog outputs. These pins can be programmed
to supply the outputs of the internal audio processing for line
out or record use.

HPOUT1L and HPOUT1R

Analog outputs from the headphone amplifiers.

PLL_LF

PLL loop filter connection. A 100 nF capacitor and a 2 kΩ resistor
in parallel with a 1 nF capacitor tied to AVDD are required for
the PLL loop filter to operate correctly.

VREF

Voltage reference for DACs and ADCs. This pin is driven by an
internal 1.5 V reference voltage.

S

FILTA and FILTD

Decoupling nodes for the ADC and DAC. Decoupling
capacitors should be connected between these nodes and
AGND, typically 47 µF in parallel with 0.1 µF and 10 µF in
parallel with 0.1 µF, respectively.

PWM1A, PWM1B, PWM2A, PWM2B, PWM3A, PWM3B, PWM4A, and PWM4B

Differential pulse-width modulation outputs are suitable for
driving Class-D amplifiers.

PWM_READY

This pin is set high when PWM is enabled and stable.

AVDD

Analog power supply pins. These pins should be connected
to 3.3 V. Each AVDD pin should be decoupled with a 0.1 µF
capacitor to AGND, as close to the pin as possible. In addition,
the ADC supply (Pin 4) and the DAC supplies (Pin 68 and Pin 71)
should share a 10 µF capacitor to ground. The PLL supply (Pin 53)
should have an additional 1 nF and 10 µF capacitor to ground,
and the headphone supply (Pin 59) should have an additional
10 µF capacitor to ground.

DVDD

Digital power supply pins. These pins should be connected to a 1.8 V
digital supply. For optimal performance, each DVDD/DGND
pair requires a 0.1 µF decoupling capacitor as close to the pin as
possible. In addition, these 0.1 µF decoupling capacitors are in
parallel with a single 10 µF capacitor.

ODVDD

Digital interface power supply pin. Connect this pin to a 3.3 V
digital supply. Decouple this pin with 10 µF and 0.1 µF capacitors to
DGND, as close to the pin as possible.

DGND

Digital ground.

AGND

Analog ground.

ODGND

Ground for the digital interface power supply.

ISET

ADC current setting resistor. See the ADC Inputs section for
more details.

Rev. B | Page 16 of 60

ADAV4601

FUNCTIONAL DESCRIPTIONS

POWER-UP SEQUENCE

The following sequence provides an overview of how to
initialize the IC:

1. Apply power to the ADAV4601.

2. Enable PLL via an I

3. Power up via an I

2

C write and wait 15 ms for PLL to lock.

2

C write to the global power-up bit in the

initialization control register (0x0000).

4. A default flow is automatically loaded on power-up. If a

user-defined flow is loaded, see the Loading a Custom
Audio Processing Flow section for additional information.

5. Depending on the I/O blocks required, other steps may

need to be taken; for example, headphone outputs may
need to be tristated. See the ADC Inputs, DAC Voltage
Outputs, PWM Outputs, Headphone Output and S/PDIF
Input/Output sections that describe the I/O blocks in detail.

6. Un mute.

MASTER CLOCK OSCILLATOR

Internally, the ADAV4601 operates synchronously to the master
MCLKI input. All internal system clocks are generated from this
single clock input using an internal PLL. This MCLKI input
can also be generated by an external crystal oscillator connected
to the MCLKI/XIN pin or by using a simple crystal oscillator
connected across MCLKI/XIN and XOUT. By default, the master
clock frequency is 24.576 MHz; however, by using the internal
dividers, an MCLKI of 12.288 MHz, 6.144 MHz, and 3.072 MHz
are also supported.

EXTERNAL CL OCK/

CRYSTAL

I2C

OSC

DIVIDER

REGISTER

Figure 21. Master Clock

Figure 22 shows the external circuit recommended for proper
operation when using a crystal oscillator. Due to the effect of
stray capacitance, consideration must be given to the value of
C1 and C2 when calculating the desired C

C +

=

LOAD

MASTER CLO CK FREQUENCY
[24.576MHz, 12.288MHz,

6.144MHz, 3.072MHz]

3.072MHz

DIVIDER W ORD
[÷8, ÷4, ÷2, ÷1]

for the crystal.

LOAD

CCCC

++

)2)(1(

pgpg

21

CCCC

+++

21

pgpg

21

C

S

PLL
REFERENCE
CLOCK

7070-018

where:

C

and C

pg1

C

is the PCB stray capacitance.

S

A good rule of thumb is to approximate
between 5 pF and 10 pF and

are the pin to ground capacitances.

pg2

C

pg1

C

to be between 2 pF and 3 pF.

S

C1

C2

Figure 22. Circuit for Crystal Resonator

XIN

XOUT

and C

07070-100

pg2

to be

I2C INTERFACE

The ADAV4601 supports a 2-wire serial (I2C compatible)
microprocessor bus driving multiple peripherals. The ADAV4601
is controlled by an external I
controller. The ADAV4601 is in slave mode on the I
during self-boot. While the ADAV4601 is self-booting, it becomes
the master, and the EEPROM, which contains the ROMs to be
booted, is the slave. When the self-boot process is complete, the
ADAV4601 reverts to slave mode on the I
should access the I

2

C bus while the ADAV4601 is self-booting
(refer to the Application Layer section and the Loading a
Custom Audio Processing Flow section).

Initially, all devices on the I
the devices monitor the SDA and SCL lines for a start condition
and the proper address. The I
establishing a start condition, defined by a high-to-low transition
on SDA while SCL remains high. This indicates that an address/
data stream follows. All devices on the bus respond to the start
condition and read the next byte (7bit address plus the R/
MSB first. The device that recognizes the transmitted address
responds by pulling the data line low during the ninth clock
pulse. This ninth bit is known as an acknowledge bit.

All other devices on the bus revert to an idle condition. The R/
bit determines the direction of the data. A Logic Level 0 on the
LSB of the first byte means the master writes information to the
peripheral. A Logic Level 1 on the LSB of the first byte means the
master reads information from the peripheral. A data transfer takes
place until a stop condition is encountered. A stop condition occurs
when SDA transitions from low to high while SCL is held high.

The ADAV4601 determines its I
the SDO0 pin after reset. Internally, the SDO0 pin is sampled by
four MCLKI edges to determine the state of the pin (high or
low). Because the pin has an internal pull-down resistor default,
the address of the ADAV4601 is 0x34 (write) and 0x35 (read).
An alternate address, 0x36 (write) and 0x37 (read), is available
by tying the SDO0 pin to ODVDD via a 10 kΩ resistor. The I
interface supports a clock frequency of up to 400 kHz.

2

C master device, such as a micro-

2

C bus. No other devices

2

C bus are in an idle state, wherein

2

C master initiates a data transfer by

2

C bus, except

W

2

C device address by sampling

W

bit)

2

C

Rev. B | Page 17 of 60

ADAV4601

Table 6. Single Word I2C Write1

S Chip address,

W

R/

= 0

1

S = start bit, P = stop bit, and AS = acknowledge by slave.

Table 7. Burst Mode I2C Write1

S Chip

address,

W

R/

= 0

1

S = start bit, P = stop bit, and AS = acknowledge by slave.

Table 8. Single Word I2C Read1

S Chip address,

W

R/

= 0

1

S = start bit, P = stop bit, AM = acknowledge by master, and AS = acknowledge by slave.

Table 9. Burst Mode I2C Read1

S Chip address,

W

= 0

R/

1

S = start bit, P = stop bit, AM = acknowledge by master, and AS = acknowledge by slave.

SCL

AS Subaddress high AS Subaddress low AS Data Byte 1 AS Data Byte 2 … AS Data Byte N P

AS Subaddress

high

AS Subaddress

AS Subaddress

AS Subaddress

high

high

low

AS Data-Word 1,

AS Subaddress

low

AS Subaddress

low

Byte 1

AS Data-Word 1,

AS S Chip address,

R/W = 1

AS S Chip address,

R/W = 1

Byte 2

AS Data-Word 2,

AS Data-Word 2,

Byte 1

AS Data Byte 1 AM Data

Byte 2

AS Data-Word 1

Byte 1

AM Data-Word 1

Byte 2

Byte 2

… AM Data

AS … P

P

Byte N

AM … P

SDA 0

START BY

MASTER

SCL

(CONTINUED)

SDA

(CONTINUED)

0

FRAME 1

FRAME 2

1

1

CHIP ADDRESS BYTE

SUBADDRESS BYTE 2

ADR

0

SEL

R/W0

ACK BY

ADAV4601

ACK BY

ADAV4601

Figure 23. I

2

C Write Format

FRAME 2

SUBADDRESS BYTE 1

FRAME 3

DATA BYTE 1

ACK BY

ADAV4601

ACK BY

ADAV4601

STOP BY

MASTER

07070-101

Rev. B | Page 18 of 60