ANALOG DEVICES ADAV400 Service Manual

Audio Codec with

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FEATURES

Fully programmable audio digital signal processing (DSP) for

enhanc

ed sound processing

Scalable digital audio delay line

Pool of 400 ms @ 48 kHz (200 ms for stereo channel)

High performance, integrated analog-to-digital converters

ADCs) and digital-to-analog converters (DACs)

( 1 stereo analog input (ADC) 4 stereo analog inputs with mux-to-stereo ADC 4 stereo (8-channel) analog outputs (DACs) Dedicated headphone output with integrated amplifier

Multichannel digital I/O

8-channel I 8- and 16-channel TDM input and output modes 2-channel (1 stereo) asynchronous I

integrated sample rate converter (SRC), supporting sample rates from 5 kHz to 50 kHz

2

S input and output modes

2

S input with

FUNCTIONAL BLOCK DIAGRAM

Embedded SigmaDSP Processor

ADAV400

Features SigmaStudio™, a proprietary graphical

programming tool for fast development of custom signal flows Includes various third-party audio algorithms

2

C control interface

I Operates from 3.3 V (analog), 1.8 V (digital core),

V (digital interface)

3.3 Features on-chip regulator for single 3.3 V operation 80-lead LQFP (14 mm × 14 mm) Temperature range: 0°C to 70°C

APPLICATIONS

ATV and AV audio applications

TV audio processing Set-top box (STB) HTiB

General audio enhancement

MCLKI

MCLKO

SCL

SDA

AD0

BCLK0

LRCLK0

SDIN0

SDIN1

SDIN2 SDIN3

AINL1

AINR1

AINL4

AINR4

ADAV400

PLL

2

C INTERFACE

I

SRC

ASYNCHRONIZE

DIGITAL INPU T

SYNCHRONIZE

MULTICHANNEL

DIGITAL INPUT

ADC

SYSTEM CLOCKS

PROGRAMMABLE

AUDIO

PROCESSOR

CORE

A–V

SYNC DELAY

MEMORY

Figure 1.

MULTICHANNEL

DIGITAL OUTPUTS

DAC

SDO0

SDO1 SDO2

SDO3

LRCLK1

BCLK1

VOUT1

VOUT2

VOUT3

VOUT4

HPOUTL

HPOUTR

AUXL1

AUXR1

AUXL2

AUXR2

05811-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADAV400

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REVISION HISTORY

7/07—Rev. 0 to Rev. A

Change to ADC Section, Total Harmonic Distortion + Noise......... 4

Change to DAC Outputs (Single-Ended),

Total Harmonic Distortion + Noise.................................................. 4

Changes to Ordering Guide...................................................................35

1/06—Revision 0: Initial Version

Power Control Register ............................................................. 33

User Control Register 2 ............................................................. 33

User Control Register 1 ............................................................. 33

DAC Amplifier Register ............................................................ 33

Typical Application Diagram........................................................ 34

Outline Dimensions....................................................................... 35

Ordering Guide .......................................................................... 35

Rev. A | Page 2 of 36

ADAV400

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GENERAL DESCRIPTION

The ADAV400 is an enhanced audio processor. Integrating high performance analog and digital I/Os with a powerful, audiospecific, programmable core enables designers to differentiate their products through audio performance.

The audio processing core is based on Analog Devices SigmaDSP® t

echnology featuring full 28-bit processing (56-bit in double precision mode); a sophisticated, fully programmable dynamics processor; and delay memory.

This technology allows the system designer to compensate for re

al-world limitations of speakers, amplifiers, and listening environments. This compensation results in a dramatic improvement of the perceived audio quality through speaker equalization, multiband compression and limiting, and thirdparty-branded algorithms.

The analog I/O integrates Analog Devices proprietary continuous t

ime, multibit, sigma-delta (Σ-) architecture. This integration

brings a higher level of performance to systems that are required to meet system branding certification by third-party algorithm providers. The analog inputs feature a 95 dB dynamic range stereo ADC fed from a four-stereo input mux. The four stereo analog outputs are each driven by a 95 dB dynamic range DAC. A dedicated headphone channel is included with integrated amplifiers.

The ADAV400 supports multichannel digital inputs and outputs.

n integrated SRC on one channel provides the capability to

A support any input sample rate in the range of 5 kHz to 50 kHz, synchronizing this input to the internal DSP engine.

The ADAV400 is supported by a powerful graphical programming t

ool that includes blocks such as general filters, EQ filters, dynamics processing, mixers, volume, and third-party algorithms for fast development of custom signal flows.

Rev. A | Page 3 of 36

ADAV400

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SPECIFICATIONS

AV DD n1 = 3.3 V, ODVDD = 3.3 V, DVDD = internal voltage regulator, temperature = 0°C to 70°C, master clock = 12.288 MHz, measurement bandwidth = 20 Hz to 20 kHz, ADC input signal = 1 kHz, DAC output signal = 1 kHz, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE SECTION

Absolute Voltage (V V

Temperature Coefficient 130 ppm/°C

REF

ANALOG INPUTS (SINGLE ENDED)

Number of Channels 8 Four stereo input channels Full-Scale Analog Input 100 A rms 2 V rms input with 20 kΩ series resistor DC Offset ±10 mV Relative to V

ADC SECTION

Resolution 24 Bits Dynamic Range

A-Weighted 90 95 dB −60 dB with respect to full-scale analog input Total Harmonic Distortion + Noise −90 dB −3 dB with respect to full-scale analog input Interchannel Gain Mismatch 0.1 dB Left and right channel gain mismatch Crosstalk −78 dB Analog channel crosstalk (AINYm2 to AINYm2)

Gain Error −6 % Power Supply Rejection −83 dB 1 kHz, 300 mV p-p signal at AVDDn

ADC DIGITAL DECIMATOR FILTER

CHARACTERISTICS @ 48 kHz Pass Band 22.5 kHz Pass-Band Ripple ±0.0002 dB Transition Band 24 kHz Stop Band 26.5 kHz Stop-Band Attenuation 100 dB Group Delay 1040 s

DAC OUTPUTS (SINGLE-ENDED) DAC amplifier register contents = 0x0010

Number of Channels 8 Four stereo output channels Resolution 24 Bits Full-Scale Analog Output 1 V rms Dynamic Range

A-Weighted 90 95 dB −60 dB with respect to full-scale code input Total Harmonic Distortion + Noise Crosstalk −100 dB Analog channel crosstalk (VOUTm2 to VOUTm2)

Gain Error 5 % Interchannel Gain Mismatch 0.1 dB Left and right channel gain mismatch DC Offset 1 mV Relative to V Power Supply Rejection −87 dB 1 kHz, 300 mV p-p signal at AVDDn

DAC DIGITAL INTERPOLATION FILTER

CHARACTERISTICS @ 48 kHz Pass Band 21.769 kHz Pass-Band Ripple ±0.01 dB Transition Band 23.95 kHz Stop Band 26.122 kHz Stop-Band Attenuation 75 dB Group Delay 580 s

) 1.5 V

REF

3

4

3

REF

Stereo ADC

One channel = −3 dB, other channel = 0 V

1

−93 dB −3 dB with respect to full-scale code input

One channel = −3 dB, other channels = 0 V

REF

1

Rev. A | Page 4 of 36

ADAV400

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Parameter Min Typ Max Unit Test Conditions/Comments

HEADPHONE OUTPUT (SINGLE ENDED)

Number of Channels 2 One stereo channel Resolution 24 Bits Full-Scale Analog Output 1 V rms Dynamic Range

A-Weighted 92 dB −60 dBFS with respect to full-scale code input Total Harmonic Distortion + Noise −84 dB −3 dBFS with respect to full-scale code input Gain Error 4 % Interchannel Gain Mismatch 0.5 dB DC Offset −30 mV Relative to V Power Supply Rejection −84 dB 1 kHz, 300 mV p-p signal at AVDDn

PLL SECTION

Master Clock Input (MCLKI) 64 × fS

3

SRC

Dynamic Range

3

512 × fS MHz

A-Weighted 115 dB −60 dBFS input (worst-case input, fS = 50 kHz) Total Harmonic Distortion + Noise −113 dB 0 dBFS input (worst-case input, fS = 50 kHz) Sample Rate 5 50 kHz

DIGITAL INPUT/OUTPUT

Input Voltage High (VIH) 2.0 ODVDD V Input Voltage Low (VIL) 0.8 V Input Leakage (IIH @ VIH = ODVDD) Input Leakage (IIL @ VIL = 0 V) −60 Output Voltage High (VOH @ IOH = 0.4 mA) 2.4 Output Voltage Low (VOL @ IOL = −3.2 mA)

10 A A V

0.4 V

Input Capacitance 10 pF

SUPPLIES

Analog Supplies (AVDDn) Digital Supplies (DVDD)

1

3.15 3.30 3.45 V

1.6 1.8 2.0 V

Interface Supply (ODVDD) 3.15 3.30 3.45 V

Supply Current, Normal Mode

Analog Current (AVDD1) 90 110 mA

Digital and Interface Current 120 135 mA

PLL Current 5 6 mA

Supply Current, Power-Down Mode

Analog Current 6 8.5 mA

Digital and Interface Current 1.5 6 mA

PLL Current 5 50 µA

1

The n refers to supply number.

2

The m refers to channel number, and the Y refers to stereo channel identifier: L for left channel or R for right channel.

3

Guaranteed by design.

4

Measured on one DAC with other DACs and ADCs off.

Measured at headphone output with 32 Ω load, headphone am

plifier register contents = 0x0001

REF

1

MCLK = 12.288 MHz, ADCs and DACs active, headphon

e outputs active and driving a 32 Ω load,

Power control register = 0xFFFF

RESET low, MCLK = 3.074 MHz, AINx = AGND, DAC and headphone outputs floating

Rev. A | Page 5 of 36

ADAV400

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DIGITAL TIMING

Table 2.

Parameter Min Max Unit Comments

MASTER CLOCK AND RESET

f

(MCLKI Frequency) 3.024 24.576 MHz

MCLKI

t

(MCLKI High) 10 ns

MCH

t

(MCLKI Low) 10 ns

MCL

t

(RESET Low Pulse Width)

RLPW

20 ns

I2C® PORT

f

(SCL Clock Frequency) 400 kHz

SCL

t

(SCL High) 0.6 µs

SCLH

t

(SCL Low) 1.3 µs

SCLL

Start Condition

t

(Setup Time) 0.6 µs Relevant for repeated start condition

SCS

t

(Hold Time) 0.6 µs The first clock is generated after this period

SCH

tDS (Data Setup Time) 100 ns t

(SCL Rise Time) 300 ns

SCR

t

(SCL Fall Time) 300 ns

SCF

t

(SDA Rise Time) 300 ns

SDR

t

(SDA Fall Time) 300 ns

SDF

Stop Condition

t

(Setup Time) 0.6

SCSH

SERIAL PORTS

Slave Mode

t

(BCLKx High) 40

SBH

t

(BCLKx Low) 40

SBL

f

(BCLKx Frequency) 64 × fS

SBF

t

(LRCLKx Setup) 10

SLS

t

(LRCLKx Hold) 10

SLH

t

(SDINx Setup) 10

SDS

t

(SDINx Hold) 10

SDH

t

(SDOx Delay) 40 ns From BCLK falling edge

SDD

Master Mode

t

(LRCLKx Delay) 5 ns From BCLK falling edge

MLD

t

(SDOx Delay) 40 ns From BCLK falling edge

MDD

t

(SDINx Setup) 10

MDS

t

(SDINx Hold) 10

MDH

µs

ns ns

ns To BCLK rising edge ns From BCLK rising edge ns To BCLK rising edge ns From BCLK rising edge

ns From BCLK rising edge ns From BCLK rising edge

Rev. A | Page 6 of 36

ADAV400

S

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Digital Timing Diagrams

t

SBH

BCLKx

t

SBL

t

SLH

LRCLKx

t

SLH

SDINx

LEFT-JUSTIFIED

MODE

SDOx

I

MODE

t

SDS

MSB

2

S

t

MDD

t

SDD

MSB – 1

MSB

t

SDH

05811-002

Figure 2. Serial Port Timing

DA

SCL

t

SCH

SDR

t

SCR

t

SCLL

t

MP

t

SCLH

t

Figure 3. I

SCF

t

DS

2

C Port Timing

t

SCH

t

SCS

t

SDF

t

SCSH

05811-003

MCLK

05811-004

Figure 4. Master Clock T

iming

Rev. A | Page 7 of 36

ADAV400

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ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

DVDD to DGND 0 V to 2.2 V ODVDD to DGND 0 V to 4.0 V AVDD to AGND 0 V to 4.0 V AGND to DGND −0.3 V to +0.3 V Digital Inputs DGND − 0.3 V to ODVDD + 0.3 V Analog Inputs AGND − 0.3 V to ADVDD + 0.3 V Reference Voltage Indefinite short circuit to ground Soldering (10 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 8 of 36

ADAV400

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

IDAC79AINR478AINL477AINR376AINL375AINR274AINL273AINR172AINL171AVDD570AGND69AGND68AVDD467FILTD66NC65NC64TEST263AUXR262AUXL261VOUT4

80

1

FILTA

2

VREF

3

AGND

4

AVDD1

5

NC

6

NC

7

NC

8

NC

9

NC

10

NC

11

NC

12

NC

13

DGND

14

DVDD

15

AD0

16

SDA

17

SCL

18

TEST0

19

TEST1

20

DGND

NC = NO CONNECT

PIN 1

21

22

DVDD

SDIN023SDIN124SDIN225SDIN3

26

27

LRCLK0

ADAV400

(Not to Scale)

28

29

DGND

BCLK0

TOP VIEW

30

31

ODVDD

VDRIVE

DVDD

32

33

34

35

36

37

DGND

MCLKI

MCLKO

SDO038SDO1

BCLK1

LRCLK1

39NC40

DVDD

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

VOUT3

VOUT2

VOUT1

AUXR1

AUXL1

AVDD3

HPOUTR

HPOUTL

AGND

PLL_LF

AVDD2

DGND

DVDD

RESET

NC

SDO3

SDO2

DGND

05811-005

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic I/O Description

1 FILTA O ADC Filter Decoupling Node for the ADC. Decouple this pin to AGND (Pin 3). 2 VREF Voltage Reference. This pin is driven by an internal 1.5 V reference voltage. Decouple this pin to AGND (Pin 3). 3 AGND 4 AVDD1 5 to 12,

NC

ADC Ground. Connect this pin to the analog ground plane. Analog Power Supply Pin for the ADC. Connect this pin to 3.3 V and decouple to AGND (Pin 3). Not Connected Internally.

65, 66 13, 20,

DGND

Digital Ground. Connect this pin to the digital ground plane. 28, 32, 41, 48

14, 21, 31, 40,

DVDD

Digital Power Supply Pins. Connect these pins to 1.8 V, either directly or by using the on-chip regulator.

Decouple to DGND. 47

15 AD0 I

2

C Address Select. Tie to ODVDD for Address 0x28 (write) and Address 0x29 (read) or to DGND for

I

Address 0x2A (write) and Address 0x2B (read). 16 SDA I/O 17 SCL I 18 TEST0 19 TEST1 22 to 25 SDIN [0:3] I 26 LRCLK0 I

27 BCLK0 I

Serial Data Input/Output for the I2C Control Port.

Serial Clock for the I2C Control Port.

Test Pin. Connect to ODVDD.

Serial Data Inputs. BCLK1 and LRCLK1 are used as the timing signals for SDIN0 to SDIN3.

Left/Right Clock for Sample Rate Converter (SRC). This input frame synchronization signal is associated

with SDIN0 to SDIN3 when one of these input channels is redirected to the SRC.

Bit Clock for Sample Rate Converter (SRC). This input clock is associated with SDIN0 to SDIN3 when one of

these input channels is redirected to the SRC. 29 ODVDD Digital Interface Supply (3.3 V) Pin. Connect this pin to a 3.3 V digital supply. Decouple to DGND. 30 VDRIVE Drive for External PNP Transistor. This is used with the on-chip 1.8 V regulator circuit.

Rev. A | Page 9 of 36

ADAV400

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Pin No. Mnemonic I/O Description

33 MCLKI I

34 MCLKO O Audio Clock Output. The MCLKO pin can be programmed to output the internal audio clock. 35 BCLK1 I/O

36 LRCLK1 I/O

37, 38, 42, 43

39, 44, 45

46 49 AVDD2 Analog Power Supply Pin for the PLL. Connect this pin to 3.3 V and decouple to AGND (Pin 51).

50 PLL_LF

51 AGND PLL Ground. Connect this pin to the analog ground plane. 52 AGND Headphone Driver Ground. Connect this pin to the analog ground plane. 53 HPOUTL O Left Headphone Output. Analog output from the headphone amplifiers. 54 HPOUTR O Right Headphone Output. Analog output from the headphone amplifiers. 55 AVDD3 Analog Power Supply Pin for the Headphone Amplifier. Connect this pin to 3.3 V and decouple to AGND (Pin 52). 56 AUXL1 O Auxiliary Analog Output Left 1. 57 AUXR1 O Auxiliary Analog Output Right 1. 58 to 61 VOUT [1:4] O Main Analog Output 1 to Output 4. 62 AUXL2 O Auxiliary Analog Output Left 2. 63 AUXR2 O Auxiliary Analog Output Right 2. 64 TEST2 Test Pin. This pin should be left unconnected. 67 FILTD DAC Filter Decoupling Node. Decouple this pin to AGND (Pin 69). 68 AVDD4 Analog Power Supply Pin for the DAC. Connect this pin to 3.3 V and decouple to AGND (Pin 69). 69, 70 AGND DAC Ground. Connect this pin to the analog ground plane. 71 AVDD5 Analog Power Supply Pin for the DAC. Connect this pin to 3.3 V and decouple to AGND (Pin 70). 72, 74,

76, 78 73, 75,

77, 79 80 IDAC

SDO [0:3] 0 Serial Data Outputs.

NC These pins should be left unconnected.

RESET

AINL [1:4] I

AINR [1:4] I

Master Clock Input. The ADAV400 uses a phase-locked loop (PLL) to generate the appropriate internal

or the DSP core.

clock f

Bit Clock for Serial Data Input/Output. for the SDINx and SDOx pins. These clocks are inputs to the ADAV400 when the port is configured as a slave, and outputs when the port is configured as a master. On power up, these pins are set to slave mode to avoid conflicts with external master mode devices.

Left/Right Clock for Serial Data Input/ signals for the SDINx and SDOx pins.

I

Active Low Reset Signal. After RESET

PLL Loop Filter. External components are required to allow the PLL to function correctly. See the PLL

k section for details of these components.

Bloc

Left Analog Input 1 to Input 4. The analog inputs are current inputs typically driven via a 20 kΩ resistor for 2 V rms input, as shown in Figure 17.

Right Analog Input 1 to Input 4. The analog inputs are cur for 2 V rms input, as shown in Figure 17.

DAC External Bias Resistor. This is an external bias pin f between this pin and AGND.

This clock and the LRCLK1 are used as clock and frame sync signals

Output. This clock and the BCLK1 are used as clock and frame sync

the ADAV400 is powered down.

rent inputs typically driven via a 20 kΩ resistor

or the DAC circuitry. Connect a 20 kΩ resistor

Rev. A | Page 10 of 36

ADAV400

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TYPICAL PERFORMANCE CHARACTERISTICS

0

–50

MAGNITUDE (d B)

–100

–150

0 192 384 576 768

FREQUENC Y (kHz)

05811-006

–100

–150

MAGNITUDE (d B)

–200

–250

–300

0 128 256 384

FREQUENC Y (kHz)

Figure 6. DAC Composite Filter Response (48 kHz) Figure 9. ADC Composite Filter Response (48 kHz)

0

–50

MAGNITUDE (d B)

–100

0

–50

–100

–150

MAGNITUDE (d B)

–200

–250

05811-009

–150

0 2448729

FREQUENC Y (kHz)

05811-007

6

–300

0244872

FREQUENC Y (kHz)

Figure 7. DAC Pass-Band Filter Response (48 kHz) Figure 10. ADC Pass-Band Filter Response (48 kHz)

0.06

0.04

0.02

0

MAGNITUDE (d B)

–0.02

–0.04

–0.06

0 8 16 24

FREQUENC Y (kHz)

05811-008

0.006

0.004

0.002

0

MAGNITUDE (d B)

–0.002

–0.004

–0.006

0 8 16 24

FREQUENCY (kHz )

Figure 8. DAC Pass-Band Ripple (48 kHz) Figure 11. ADC Pass-Band Ripp

le (48 kHz)

05811-010

96

05811-011

Rev. A | Page 11 of 36

ANALOG DEVICES ADAV400 Service Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

DIGITAL TIMING

Digital Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS