Analog Devices ADADC80-Z-12, ADADC80-12 Datasheet

REV. B

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AD ADC80

12-Bit Successive-Approximation

Integrated Circuit A/D Converter

FEATURES True 12-Bit Operation: Max Nonlinearity ⴞ0.012% Low Gain T.C.: ⴞ30 ppm/ⴗC Max Low Power: 800 mW Fast Conversion Time: 25 ␮s Precision 6.3 V Reference for External Application Short-Cycle Capability Parallel Data Output Monolithic DAC with Scaling Resistors for Stability Low Chip Count—High Reliability Industry Standard Pinout “Z“ Models for ⴞ12 V Supplies

FUNCTIONAL BLOCK DIAGRAM

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

5V ANALOG

SUPPLY

DIGITAL GND

COMPARATOR

BIPOLAR

OFFSET OUT

10V SPAN IN

20V SPAN IN

ANALOG GND

5V DIGITAL

SUPPLY

GAIN ADJUST

BIT 8

BIT 9

BIT 10

BIT 11 BIT 12

(LSB) NC –15V OR

–12V REF OUT

(6.3V) CLOCK

OUT STATUS SHORT

CYCLE CLOCK INHIBIT EXTERNAL CLOCK IN CONVERT START 15V OR 12V

COMP

12-BIT

SAR

REFERENCE

CLOCK

AND CONTROL CIRCUITS

AD ADC80

12-BIT DAC

NC = NO CONNECT

BIT 1 (MSB)

PRODUCT DESCRIPTION

The AD ADC80 is a complete 12-bit successive-approximation analog-to-digital converter that includes an internal clock, reference, and comparator. Its hybrid IC design uses MSI digital and linear monolithic chips in conjunction with a 12-bit monolithic DAC to provide modular performance and versatility with IC size, price, and reliability.

Important performance characteristics of the AD ADC80 include a maximum linearity error at 25⬚C of ± 0.012%, max gain T.C. of 30 ppm/⬚C, typical power dissipation of 800 mW, and max conversion time of 25 ␮s. Monotonic operation of the feedback D/A converter guarantees no missing codes over the temperature range of –25⬚C to +85⬚C.

The design of the AD ADC80 includes scaling resistors that provide analog signal ranges of ± 2.5 V, ± 5.0 V, ± 10 V, 0 V to

5.0 V, or 0 V to 10.0 V. The 6.3 V precision reference may be used for external applications. All digital signals are fully DTL and TTL compatible; output data is in parallel form.

The AD ADC80 is available in grades specified for use over the –25⬚C to +85⬚ C temperature range and is available in a 32-lead ceramic DIP.

PRODUCT HIGHLIGHTS

1. The AD ADC80 is a complete 12-bit A/D converter. No external components are required to perform a conversion.

2. A monolithic 12-bit feedback DAC is used for reduced chip count and higher reliability.

3. The internal buried Zener reference is laser trimmed to 6.3 V. The reference voltage is available externally and can supply up to 1.5 mA beyond that required for the reference and bipolar offset current.

4. The scaling resistors are included on the monolithic DAC for exceptional thermal tracking.

5. The AD ADC80 directly replaces other devices of this type with significant increases in performance.

6. The fast conversion rate of the AD ADC80 makes it an excellent choice for applications requiring high system throughput rates.

7. The short cycle and external clock options are provided for applications requiring faster conversion speeds or lower resolutions.

REV. B–2–

AD ADC80–SPECIFICATIONS

(Typical @ 25ⴗC, ⴞ15 V, and +5 V, unless otherwise noted.)

Model AD ADC80-12 Unit

RESOLUTION 12 Bits

ANALOG INPUTS

Voltage Ranges

Bipolar ± 2.5, ± 5, ± 10 V Unipolar 0, +5, +10 V

Impedance (Direct Input) 0 to +5, ±2.5 V

0 to +10, ± 5V ± 10 V

DIGITAL INPUTS

Convert Command Positive Pulse 100 ns Wide (min) (“0” to “1” Initiates Conversion) Logic Loading 1 TTL Load External Clock 1 TTL Load

TRANSFER CHARACTERISTICS ERROR

Gain Error

± 0.1 % of FSR

Offset

Unipolar ± 0.05 % of FSR Bipolar ± 0.1 % of FSR

Linearity Error (max)

± 0.012 % of FSR Inherent Quantization Error ± 1/2 LSB Differential Linearity Error ± 1/2 LSB No Missing Codes Temperature Range –25 to +85 ∞C Power Supply Sensitivity

± 15 V ± 0.0030 % of FSR/% V

+5 V ± 0.0015 % of FSR/% V

DRIFT

Specification Temperature Range –25 to +85 ∞C Gain (max) ± 30 ppm/∞C Offset

Unipolar ± 3 ppm of FSR/∞C

Bipolar ± 15 ppm of FSR/∞C Linearity (max) ± 3 ppm of FSR/∞C Monotonicity GUARANTEED

CONVERSION SPEED

22, 25 ms min, ms max

DIGITAL OUTPUT (All Codes Complementary)

Parallel

Output Codes

Unipolar CSB Bipolar COB, CTC

Output Drive 2 TTL Loads Status Logic “1” During Conversion

Status Output Drive 2 TTL Loads Internal Clock

Clock Output Drive 2 TTL Loads

Frequency

575 kHz

INTERNAL REFERENCE VOLTAGE +6.3, ± 10 V ± mV

Max External Current (With No Degradation of Specifications) 1.5 mA Tempco of Drift ± 10, ± 20 ppm/∞C typ, ppm/∞C max

REV. B

AD ADC80

–3–

Model AD ADC80-12 Unit

POWER REQUIREMENTS

Rated Voltages ± 15, +5 V Range for Rated Accuracy 4.75 to 5.25 and ± 14.0 to ± 16.0 V Z Models

4.75 to 5.25 and ± 11.4 to ± 16.0 V

Supply Drain +15 V +10 mA

–15 V –20 mA +5 V +70 mA

TEMPERATURE RANGE

Specification –25 to +85 ∞C Operating (Derated Specifications) –55 to +100 ∞C Storage –55 to +125 ∞C

PACKAGE OPTION

DH-32D AD ADC80-12

NOTES

DTL/TTL compatible, i.e., Logic “0” = 0.8 V max, Logic “1” = 2.0 V min for digital inputs, Logic “0” = 0.4 V max, and Logic “1” = 2.4 V min digital outputs.

Adjustable to zero with external trimpots.

FSR means Full-Scale Range, i.e., unit connected for ± 10 V range has 20 V FSR.

Error shown is the same as ± 1/2 LSB max for resolution of A/D converter.

Conversion time with internal clock.

See Table I. CSB—Complementary Straight Binary

COB—Complementary Offset Binary CTC—Complementary Twos Complement

For conversion speeds specified.

For Z models order AD ADC80Z-12.

For package outline information see Package Information section.

Specifications subject to change without notice.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

AD ADC80 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD ADC80-12 –25∞C to +85∞C 32-Lead Ceramic DIP DH-32D AD ADC80-Z-12 –25∞C to +85∞C 32-Lead Ceramic DIP DH-32D

REV. B–4–

AD ADC80

PIN CONFIGURATION

BIT 7 BIT 8

BIT 9

BIT 10

BIT 11

BIT 12 (LSB) NC

–15V OR –12V

REF OUT (6.3V)

CLOCK OUT

STATUS

SHORT CYCLE

CLOCK INHIBIT

EXTERNAL CLOCK IN

CONVERT START 15V OR 12V

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

5V ANALOG

SUPPLY

DIGITAL GND

COMPARATOR IN

BIPOLAR

OFFSET OUT

10V SPAN IN

20V SPAN IN

ANALOG GND

5V DIGITAL

SUPPLY

GAIN ADJUST

NC = NO CONNECT

BIT 1 (MSB)

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1–6BIT 6–BIT 1 (MSB) Digital Outputs

75 V ANALOG SUPPLY Analog Positive Supply (nominally ± 0.25 V) 8BIT 1 (MSB) MSB Inverted Digital Output

95 V DIGITAL SUPPLY Digital Positive Supply (nominally ± 0.25 V)

10 DIGITAL GND Digital Ground

11 COMPARATOR IN Offset Adjust

12 BIPOLAR OFFSET OUT Bipolar Offset Output

13 10 V SPAN IN Analog Input 10 V Signal Range

14 20 V SPAN IN Analog Input 20 V Signal Range

15 ANALOG GND Analog Ground

16 GAIN ADJUST Gain Adjust

17 15 V OR 12 V Analog Positive Supply (nominally ± 1.0 V for 15 V or ± 0.6 V for 12 V)

18 CONVERT START Enables Conversion

19 EXTERNAL CLOCK IN External Clock Input

20 CLOCK INHIBIT Clock Inhibit

21 SHORT CYCLE Shortens Conversion Cycle to Desired Resolution

22 STATUS Logic High, ADC Converting/Logic Low, ADC Data Valid

23 CLOCK OUT Internal Clock Output

24 REF OUT (6.3 V) 6.3 V Reference Output

25 –15 V OR –12 V Analog Negative Supply (nominally ± 1.0 V for –15 V or ± 0.6 V for –12 V)

26 NC No Connection

27–32 BIT 12 (LSB)–BIT 7 Digital Outputs

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