ANALOG DEVICES ADADC71 Service Manual

Complete, High Resolution

FEATURES

16-bit converter with reference and clock
±0.003% maximum nonlinearity
No missing codes to 14 bits
Fast conversion: 35 μs (14 bit)
Short cycle capability
Parallel logic outputs
Low power: 645 mW typical
Industry standard pinout

APPLICATIONS

Medical and analytic instrumentation
Precision measurement for industrial robots
Automatic test equipment
Multi-channel data acquisition systems
Servo-control systems

GENERAL DESCRIPTION

The ADADC71 is a high resolution 16-bit hybrid IC analog-to­digital converter including reference, clock, and laser-trimmed
thin-film components. The package is a compact 32-pin
hermetic ceramic DIP. The thin-film scaling resistors allow
analog input ranges of ±2.5 V, ±5 V, ±10 V, 0 to +5 V, 0 to +10 V,
and 0 to +20 V.

Important performance characteristics of the device are
maximum linearity error of ±0.003% of FSR, and maximum
conversion time of 50 μs. This performance is due to innovative
design and the use of proprietary monolithic DAC chips. Laser­trimmed thin-film resistors provide the linearity and wide
temperature range for no missing codes.

The ADADC71 provides data in parallel format with
corresponding clock and status outputs. All digital inputs and
outputs are TTL-compatible. The ADADC71 used to provide
data in a serial format. The serial output function is no longer
available after date code 0120.

16-Bit A/D Converter

ADADC71

FUNCTIONAL BLOCK DIAGRAM

(MSB) BIT 1

1

BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8

BIT 9
BIT 10
BIT 11
BIT 12

(LSB FOR 13 BITS) BIT 13
(LSB FOR 14 BITS) BIT 14

BIT 15
BIT 16

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

NC = NO CONNECT

ADADC71

16-BIT SAR

COMPARATOR

REFERENCE

3.75kΩ 3.75kΩ

16-BIT DAC

CLOCK

Figure 1.

PRODUCT HIGHLIGHTS

1. The ADADC71 provides 16-bit resolution with a

maximum linearity error less than ±0.003% (±0.006% for
J grades) at 25

2. Conversion time is 35 μs typical (50 μs max) to 14 bits with

short cycle capability.

3. Two binary codes are available on the ADADC71 output:

complementary straight binary (CSB) for unipolar input
voltage ranges, and complementary offset binary (COB) for
bipolar input ranges. Complementary two’s complement
(CTC) coding may be obtained by inverting Pin 1 (MSB).

4. The proprietary chips used in this hybrid design provide

excellent stability over temperature, and lower chip count
for improved reliability.

o

C.

7.5kΩ

SHORT CYCLE

32

CONVERT COMMAND

31

+5V DC SUPPLY V

30

GAIN ADJUST

29

+15V DC SUPPLY V

28

COMPARATOR IN

27

26

BIPOLAR OFFSET
+10V

25

+20V

24

REF OUT (4.3V)

23

22

ANALOG COMMON
–15V DC SUPPLY V

21

CLOCK OUT

20

DIGITAL COMMON

19

18

STATUS
NC

17

L

CC

EE

03537-001

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

ADADC71

TABLE OF CONTENTS

Specifications..................................................................................... 3

Digital Output Data......................................................................8

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Theory of Operation ........................................................................ 6

Description of Operation ................................................................ 7

Gain Adjustment .......................................................................... 7

Zero Offset Adjustment............................................................... 7

Timing............................................................................................ 7

REVISION HISTORY

6/05—Rev. B to Rev. C

Updated Format ..................................................................Universal

Removed ADADC72..........................................................Universal

Updated Outline Dimensions....................................................... 12

Changes to Ordering Guide.......................................................... 12

Input Scaling ..................................................................................8

Calibration (14-Bit Resolution Examples).................................9

Grounding, Decoupling, and Layout Considerations ........... 10

T/H Requirements for High Resolution Applications .......... 10

Using the ADADC71 at Slower Conversion Times ............... 11

Outline Dimensions ....................................................................... 12

Ordering Guide .......................................................................... 12

Rev. C | Page 2 of 12

ADADC71

SPECIFICATIONS

Typical at TA =+25oC, VS = ±15 V, +5 V unless otherwise noted.

Table 1.

Parameter Min Typ Max Units Comment

RESOLUTION 16 Bits
ANALOG INPUTS

Voltage Ranges

Bipolar
±5 V
±10 V
Unipolar

Impedance (Direct Input)

0 to ±5 V, ±2.5 V
0 to ±10 V, ±5.0 V
0 to ±20 V, ±10 V

DIGITAL INPUTS

1

Convert command

Logic Loading
TRANSFER CHARACTERISTICS
ACCURACY

Gain Error ±0.1

Offset Error

Unipolar ±0.05
Bipolar ±0.1

Linearity Error ±0.006 % of FSR J Grade
±0.003 % of FSR K Grade

Inherent Quantization Error ±1/2 LSB

Differential Linearity Error ±0.003 % of FSR

No Missing Codes @ 25oC

4

POWER SUPPLY SENSITIVITY

±15 V dc 0.003 % of FSR/%ΔVs

+5 V dc 0.001 % of FSR/%ΔVs
CONVERSION TIME5 (14 BITS) 35 50 μs
WARM-UP TIME 5 Minutes
DRIFT

Gain ±15 ppm/oC

Offset

Unipolar ±2 ±4 ppm of FSR/oC

Bipolar ±10 ppm of FSR/oC
Linearity ±2 ±3 ppm of FSR/oC
Guaranteed No Missing Code

Temperature Range

4

±2.5 V

0 to +5 V
0 to +10 V
0 to +20 V

1.88 KΩ

3.75 KΩ

7.50 KΩ

1 LSTTL Load

2

2

2

±0.2 %

±0.1 % of FSR

3

±0.2 % of FSR

Trailing edge of positive 50 ns (min) pulse
initiates conversion

to 14 bits Guaranteed K Grade

0 to 70

o

C JD (13 bits), KD (14 bits)

Rev. C | Page 3 of 12

ADADC71

Parameter Min Typ Max Units Comment

DIGITAL OUTPUT

Parallel Output Codes

Unipolar CSB
Bipolar COB, CTC
Output Drive 5 LSTTL Loads

Status Logic 1 during conversion

Status Output Drive 5 LSTTL Loads

Internal Clock

Clock Output Drive 5 LSTTL Loads
Frequency 400 kHz

INTERNAL REFERENCE VOLTAGE 6.3 V dc

Error ±5 %
Max External Current Drain with No

Degradation of Specifications
Temperature Coefficient ±10 ppm/oC

POWER SUPPLY REQUIREMENTS

Power Consumption 645 850 mW
Rated Voltage, Analog ±15 ±0.5 V dc
Rated Voltage, Digital ±5 ±0.25 V dc
Supply Drain +15 V dc +16 mA
Supply Drain −15 V dc −21 mA
Supply Drain +5 V dc +18 mA

TEMPERATURE RANGE

Specification 0 to +70 °C
Operating (Derated Specs) −25 to +85 °C
Storage −55 to +125 °C

1

For inputs Logic 0 = 0.8 V, max. Logic 1 = 2.0 V, min. For digital outputs Logic 0 = 0.4 V max. Logic 1 = 2.4 V min.

2

Adjustable to 0.

3

Full scale range.

4

For definition of “No Missing Codes,” refer to the Theory of Operation section.

5

Conversion time may be shortened with short cycle set for lower resolution.

6

CSB—Complementary straight binary. COB— Complementary offset binary, CTC—Complementary twos complement.

7

CTC coding obtained by inverting MSB (Pin 1).

1

6

All codes complementary

7

±200 μA

Rev. C | Page 4 of 12