ANALOG DEVICES ADA4940-1, ADA4940-2 Service Manual
Fully Differential ADC Driver
ADA4940-1/ADA4940-2
Rev. B
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1–FB
2+IN
3–IN
4+FB
11 –OUT
12 DISABLE
10 +OUT
9 V
OCM
5+V
S
6+V
S
7+V
S
8
+V
S
15
–V
S
16
–V
S
14
–V
S
13
–V
S
ADA4940-1
08452-001
ADA4940-2
1–IN1
2+FB1
3+V
S1
4+V
S1
5–FB2
6+IN2
15
–V
S2
16 –V
S2
17 V
OCM1
18 +OUT1
14
DISABLE2
13 –OUT2
7–IN2
8+FB2
9+V
S2
11V
OCM2
12+OUT2
10+V
S2
21
–V
S1
22
–V
S1
23
–FB1
24
+IN1
20
DISABLE1
19
–OUT1
0
–160
–140
–120
–100
–80
–60
–40
–20
0 20k 40k 60k 80k 100k
08452-300
AMPLIT UDE ( dB)
FREQUENCY ( Hz )
+D
IN
–D
IN
R1 R2
R4R3
+IN
–OUT
C
F
33Ω
2.5V
AD7982
ADA4940-1
33Ω
2.7nF
2.7nF
C
F
+OUT
+
–
–IN
IN+
IN–
GND
VDDREF
V
OCM
AD7621
65 3 16
88
Data Sheet
FEATURES
Small signal bandwidth: 260 MHz
Ultralow power 1.25mA
Extremely low harmonic distortion
−122 dB THD at 50 kHz
−96 dB THD at 1 MHz
Low input voltage noise: 3.9 nV/√Hz
0.35 mV maximum offset voltage
Balanced outputs
Settling time to 0.1%: 34 ns
Rail-to-rail output: −V
Adjustable output common-mode voltage
Flexible power supplies: 3 V to 7 V (LFCSP)
Disable pin to reduce power consumption
ADA4940-1 is available in LFCSP and SOIC packages
APPLICATIONS
Low power PulSAR®/SAR ADC drivers
Single-ended-to-differential conversion
Differential buffers
Line drivers
Medical imaging
Industrial process controls
Portable electronics
+ 0.1 V to +VS − 0.1 V
S
Ultralow Power, Low Distortion
FUNCTIONAL BLOCK DIAGRAMS
Figure 1.
GENERAL DESCRIPTION
The ADA4940-1/ADA4940-2 are low noise, low distortion fully
differential amplifiers with very low power consumption. They
are an ideal choice for driving low power, high resolution, high
performance SAR and sigma-delta (Σ-Δ) analog-to-digital
converters (ADCs) with resolutions up to 16 bits from dc to
1 MHz on only 1.25 mA of quiescent current. The adjustable
level of the output common-mode voltage allows the ADA4940-1/
ADA4940-2 to match the input common-mode voltage of
multiple ADCs. The internal common-mode feedback loop
provides exceptional output balance, as well as suppression of
even-order harmonic distortion products.
With the ADA4940-1/ADA4940-2, differential gain configurations
are easily realized with a simple external feedback network of
four resistors determining the closed-loop gain of the amplifier.
The ADA4940-1/ADA4940-2 are fabricated using Analog Devices,
Inc., SiGe complementary bipolar process, enabling them to
achieve very low levels of distortion with an input voltage noise
of only 3.9 nV/√Hz. The low dc offset and excellent dynamic
performance of the ADA4940-1/ADA4940-2 make them well
suited for a variety of data acquisition and signal processing
applications.
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Figure 2. ADA4940-1 Driving the AD7982 ADC
The ADA4940-1 is available in a Pb-free, 3 mm × 3 mm, 16-lead
LFCSP, and an 8-lead SOIC. The ADA4940-2 is available in a Pb-
free, 4 mm × 4 mm, 24-lead LFCSP. The pinout is optimized to
facilitate printed circuit board (PCB) layout and minimize
distortion. The ADA4940-1/ADA4940-2 are specified to
operate over the −40°C to +125°C temperature range.
Table 1. Similar Products to the ADA4940-1/ADA4940-2
Product
(mA)
AD8137 3 110 450 8.25
ADA4932-x 9 560 2800 3.6
ADA4941-1 2.2 31 22 5.1
Isupply
Bandwidth
(MHz)
Slew Rate
(V/µs)
Table 2. Complementary Products to the ADA4940-1/ADA4940-2
Product
(mW)
AD7982 7.0 1 18 98
AD7984 10.5 1.333 18 96.5
AD7623 45 1.333 16 88
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Power
Throughput
(MSPS)
Resolution
(Bits)
www.analog.com
Noise
(nV/√Hz)
SNR
(dB)
ADA4940-1/ADA4940-2 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
VS = 5 V .......................................................................................... 3
VS = 3 V .......................................................................................... 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
Maximum Power Dissipation ..................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 10
Test Circuits ..................................................................................... 19
Terminology .................................................................................... 20
Definition of Terms .................................................................... 20
Theory of Operation ...................................................................... 21
Applications Information .............................................................. 22
Analyzing an Application Circuit ............................................ 22
Setting the Closed-Loop Gain .................................................. 22
Estimating the Output Noise Voltage ...................................... 22
Impact of Mismatches in the Feedback Networks ................. 23
Calculating the Input Impedance of an Application Circuit 23
Input Common-Mode Voltage Range ..................................... 24
Input and Output Capacitive AC Coupling ............................ 25
Setting the Output Common-Mode Voltage .......................... 25
DISABLE
Pin .............................................................................. 25
Driving a Capacitive Load ......................................................... 25
Driving a High Precision ADC ................................................ 26
Layout, Grounding, and Bypassing .............................................. 27
ADA4940-1 LFCSP Example .................................................... 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 29
REVISION HISTORY
3/12—Rev. A to Rev. B
Reorganized Layout ............................................................ Universal
Added ADA4940-1 8-Lead SOIC Package ...................... Universal
Changes to Features Section, Table 1, and Figure 1; Replaced
Figure 2 .............................................................................................. 1
Changed V
Section ................................................................................................ 3
Changes to V
Changes to Table 4 and Table 5 ....................................................... 4
Changes to V
Changes to Table 7 and Table 8 ....................................................... 6
Added Figure 5 and Table 12, Renumbered Sequentially ........... 9
Changes to Figure 7, Figure 8, and Figure 9................................ 10
Added Figure 15 and Figure 18; Changes to Figure 13,
Figure 14, and Figure 16 ................................................................ 11
Changes to Figure 19 and Figure 20 ............................................. 12
Changes to Figure 25, Figure 26, and Figure 27; Added
Figure 28, Figure 29, and Figure 30 .............................................. 13
Changes to Figure 31, Figure 32, Figure 33, Figure 34, Figure 35,
and Figure 36 ................................................................................... 14
Changes to Figure 37, Figure38, Figure 39, and Figure 41 ........ 15
Changes to Figure 49, Figure 50, and Figure 51 ......................... 17
Added Figure 55 and Figure 57..................................................... 18
Changes to Differential V
CMRR Section ................................................................................ 20
Changes to Calculating the Input Impedance of an Application
= ±2 V(or +5 V) Section to VS = +5 V
S
= +5 V Section and Table 3.................................... 3
S
= 3 V Section and Table 6 ...................................... 5
S
, Differential CMRR, and V
OS
OCM
Rev. B | Page 2 of 32
Circuit Section ................................................................................ 23
Changes to Figure 71 ...................................................................... 25
Changes to Driving a High Precision ADC Section
and Figure 73 ................................................................................... 26
Changed ADA4940-1 Example Section to ADA4940-1 LFCSP
Example Section ............................................................................. 27
Changes to Ordering Guide .......................................................... 29
12/11—Rev. 0 to Rev. A
Changes to Features Section, General Description
Section, Table 1 .................................................................................. 1
Replaced Figure 1 and Figure 2 ....................................................... 1
Changes to V
= ±2.5 V (or +5 V) Section and Table 3 ................ 3
S
Changes to Table 6 ............................................................................. 5
Replaced Figure 7, Figure 8, Figure 9, and Figure 10 ................... 9
Replaced Figure 14, Figure 15, and Figure 17 ............................. 10
Replaced Figure 24 and Figure 27 ................................................ 12
Changes to Figure 37 ...................................................................... 14
Replaced Figure 43 and Figure 46 ................................................ 15
Replaced Figure 53 ......................................................................... 18
Changes to Estimating the Output Noise Voltage Section, Table
14, Table 15, and Calculating the Input Impedance of an
Application Circuit Section ........................................................... 21
Changes to Input Common-Mode Voltage Range Section....... 22
Changes to Driving a High Precision ADC Section and
Figure 65 .......................................................................................... 24
10/11—Revision 0: Initial Version
Data Sheet ADA4940-1/ADA4940-2
Input Offset Voltage Drift
T
to T
1.2 µV/°C
Input Resistance
Differential
33 kΩ
Linear Output Current
f = 1 MHz, R
= 22 Ω, SFDR = −60 dBc
46 mA peak
SPECIFICATIONS
VS = 5 V
V
= Mid Supply, RF = RG = 1 kΩ, R
OCM
(See Figure 61 for the definition of terms.)
+DIN or –DIN to V
Performance
OUT, dm
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth V
V
V
−3 dB Large Signal Bandwidth V
V
V
Bandwidth for 0.1 dB Flatness V
Slew Rate V
Settling Time to 0.1% V
Overdrive Recovery Time G = 2, V
NOISE/HARMONIC PERFORMANCE
HD2/HD3 V
V
V
V
V
IMD3 V
Input Voltage Noise f = 100 kHz 3.9 nV/√Hz
Input Current Noise f = 100 kHz 0.81 pA/√Hz
Crosstalk V
INPUT CHARACTERISTICS
Input Offset Voltage VIP = VIN = V
Input Bias Current −1.6 −1.1 µA
Input Bias Current Drift T
Input Offset Current −500 ±50 +500 nA
Input Common-Mode Voltage Range −VS − 0.2 to
= 1 kΩ, TA = 25°C, LFCSP package, unless otherwise noted. T
L, dm
= 0.1 V p-p, G = 1 260 MHz
OUT, dm
= 0.1 V p-p, G = 2 220 MHz
OU T, dm
= 0.1 V p-p, G = 5 75 MHz
OU T, dm
= 2 V p-p, G = 1 25 MHz
OUT, dm
= 2 V p-p, G = 2 22 MHz
OU T, dm
= 2 V p-p, G = 5 19 MHz
OU T, dm
= 2 V p-p, G = 1 and G = 2 14.5 MHz
OUT, dm
= 2 V step 95 V/µs
OUT, dm
= 2 V step 34 ns
OUT, dm
= 6 V p-p, triangle wave 86 ns
IN, dm
= 2 V p-p, fC = 10 kHz −125/−118 dBc
OU T, dm
= 2 V p-p, fC = 50 kHz −123/−126 dBc
OU T, dm
= 2 V p-p, fC = 50 kHz, G = 2 −124/−117 dBc
OU T, dm
= 2 V p-p, fC = 1 MHz −102/−96 dBc
OUT, dm
= 2 V p-p, fC = 1 MHz, G = 2 −100/–92 dBc
OU T, dm
= 2 V p-p, f1 = 1.9 MHz, f2 = 2.1 MHz −99 dBc
OUT, dm
= 2 V p-p, fC = 1 MHz −110 dB
OUT, dm
MIN
MIN
= 0 V
OCM
MAX
to T
−4.5 nA/°C
MAX
−0.35 ±0.06 +0.35 mV
MIN
+V
to T
= −40°C to +125°C.
MAX
− 1.2
S
V
Common mode 50 MΩ
Input Capacitance 1 pF
Common-Mode Rejection Ratio (CMRR) ΔV
Open-Loop Gain 91 99 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Each single-ended output −VS + 0.1 to
Output Balance Error f = 1 MHz, ΔV
OS, dm
/ΔV
IN, cm
L, dm
, ∆V
OU T, c m
= ±1 V dc 86 119 dB
IN, cm
/ΔV
Rev. B | Page 3 of 32
−65 −60 dB
OUT, dm
+V
− 0.1
S
−V
+ 0.07 to
S
− 0.07
+V
S
V
ADA4940-1/ADA4940-2 Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Quiescent Current Drift
T
to T
4.25 µA/°C
V
to V
OCM
Table 4.
V
DYNAMIC PERFORMANCE
OCM
−3 dB Small Signal Bandwidth V
−3 dB Large Signal Bandwidth V
Slew Rate V
Input Voltage Noise f = 100 kHz 83 nV/√Hz
Gain ΔV
V
CHARACTERISTICS
OCM
Input Common-Mode Voltage Range −VS + 0.8 to
Input Resistance 250 kΩ
Offset Voltage V
Input Offset Voltage Drift T
Input Bias Current −7 +4 +7 µA
CMRR ΔV
General Performance
Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range LFCSP 3 7 V
SOIC 3 6 V
Quiescent Current per Amplifier Enabled 1.05 1.25 1.38 mA
Disabled 13.5 28.5 µA
+PSRR ΔV
−PSRR ΔV
DISABLE (
DISABLE
Enabled ≥(−VS + 1.8) V
Turn-Off Time 10 µs
Turn-On Time 0.6 µs
DISABLE
Enabled
Disabled
OPERATING TEMPERATURE RANGE −40 +125 °C
Performance
OUT, cm
= 0.1 V p-p 36 MHz
OU T, cm
= 1 V p-p 29 MHz
OU T, cm
= 1 V p-p 52 V/µs
OU T, cm
/ΔV
, ΔV
OU T, c m
OCM
= ±1 V 0.99 1 1.01 V/V
OCM
V
+V
− 0.7
S
DISABLE
= V
OS, cm
to T
MIN
OS, dm
MIN
OS, dm
OS, dm
PIN)
− V
OU T, c m
20 µV/°C
MAX
/ΔV
OCM
MAX
; VIP = VIN = V
OCM
, ΔV
= ±1 V 86 100 dB
OCM
= 0 V −6 ±1 +6 mV
OCM
/ΔVS, ΔVS = 1 V p-p 80 90 dB
/ΔVS, ΔVS = 1 V p-p 80 96 dB
Input Voltage Disabled ≤(−VS + 1) V
Pin Bias Current per Amplifier
DISABLE
DISABLE
= +2.5 V 2 5 µA
= −2.5 V −10 −5 µA
Rev. B | Page 4 of 32
Data Sheet ADA4940-1/ADA4940-2
V
= 0.1 V p-p, G = 5
70 MHz
Crosstalk
V
= 2 V p-p, fC = 1 MHz
−110
dB
Open-Loop Gain
91
99 dB
Linear Output Current
f = 1 MHz, R
= 26 Ω, SFDR = −60 dBc
38 mA peak
VS = 3 V
V
= Mid Supply, RF = RG = 1 kΩ, R
OCM
(See Figure 61 for the definition of terms.)
+DIN or –DIN to V
Performance
OUT, dm
Table 6.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth V
V
−3 dB Large Signal Bandwidth V
V
V
Bandwidth for 0.1 dB Flatness V
Slew Rate V
Settling Time to 0.1% V
Overdrive Recovery Time G = 2, V
NOISE/HARMONIC PERFORMANCE
HD2/HD3 V
V
IMD3 V
Input Voltage Noise f = 100 kHz 3.9 nV/√Hz
Input Current Noise f = 100 kHz 0.84 pA/√Hz
INPUT CHARACTERISTICS
Input Offset Voltage VIP = VIN = V
Input Offset Voltage Drift T
Input Bias Current −1.6 −1.1 µA
Input Bias Current Drift T
Input Offset Current −500 ±50 +500 nA
Input Common-Mode Voltage Range −VS − 0.2 to
Input Resistance Differential 33 kΩ
Common mode 50 MΩ
Input Capacitance 1 pF
Common-Mode Rejection Ratio (CMRR) ΔV
= 1 kΩ, TA = 25°C, LFCSP package, unless otherwise noted. T
L, dm
= 0.1 V p-p 240 MHz
OU T, dm
= 0.1 V p-p, G = 2 200 MHz
OU T, dm
OU T, dm
= 2 V p-p 24 MHz
OU T, dm
= 2 V p-p, G = 2 20 MHz
OU T, dm
= 2 V p-p, G = 5 17 MHz
OU T, dm
= 0.1 V p-p 14 MHz
OU T, dm
= 2 V step 90 V/µs
OU T, dm
= 2 V step 37 ns
OU T, dm
= 3.6 V p-p, triangle wave 85 ns
IN, dm
= 2 V p-p, fC = 50 kHz (HD2/HD3) −115/−121 dBc
OU T, dm
= 2 V p-p, fC = 1 MHz (HD2/HD3) −104/−96 dBc
OU T, dm
= 2 V p-p, f1 = 1.9 MHz, f2 = 2.1 MHz −98 dBc
OU T, dm
OU T, dm
MIN
MIN
= 1.5 V
OCM
to T
1.2 µV/°C
MAX
to T
−4.5 nA/°C
MAX
/ΔV
OS, dm
IN, cm
, ∆V
= ±0.25 V dc 86 114 dB
IN, cm
−0.4 ±0.06 +0.4 mV
MIN
+V
to T
= −40°C to +125°C.
MAX
− 1.2
S
V
OUTPUT CHARACTERISTICS
Output Voltage Swing Each single-ended output −VS + 0.08 to
Output Balance Error f = 1 MHz, ΔV
L, dm
/ΔV
OU T, c m
Rev. B | Page 5 of 32
+ 0.04 to
−V
+V
− 0.08
S
−65 −60 dB
OUT, dm
+V
S
− 0.04
S
V
ADA4940-1/ADA4940-2 Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SOIC 3 6 V
V
to V
OCM
Table 7.
V
DYNAMIC PERFORMANCE
OCM
−3 dB Small Signal Bandwidth V
−3 dB Large Signal Bandwidth V
Slew Rate V
Input Voltage Noise f = 100 kHz 92 nV/√Hz
Gain ΔV
V
CHARACTERISTICS
OCM
Input Common-Mode Voltage Range −VS + 0.8 to
Input Resistance 250 kΩ
Offset Voltage V
Input Offset Voltage Drift T
Input Bias Current −5 +1 +5 µA
CMRR ΔV
General Performance
Performance
OUT, cm
= 0.1 V p-p 36 MHz
OU T, cm
= 1 V p-p 26 MHz
OU T, cm
= 1 V p-p 48 V/µs
OU T, cm
/ΔV
, ΔV
OU T, c m
OCM
= ±0.25 V 0.99 1 1.01 V/V
OCM
V
+V
− 0.7
S
OS, cm
MIN
OS,dm
= V
to T
− V
OU T, c m
20 µV/°C
MAX
/ΔV
, ΔV
OCM
; VIP = VIN = V
OCM
= ±0.25 V 80 100 dB
OCM
= 1.5 V −7 ±1 +7 mV
OCM
Table 8.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range LFCSP 3 7 V
Quiescent Current per Amplifier Enabled 1 1.18 1.33 mA
T
MIN
to T
4.25 µA/°C
MAX
Disabled 7 22 µA
+PSRR ΔV
−PSRR ΔV
DISABLE (
DISABLE
DISABLE
PIN)
Input Voltage Disabled ≤(−VS + 1) V
/ΔVS, ΔVS = 0.25 V p-p 80 90 dB
OS, dm
/ΔVS, ΔVS = 0.25 V p-p 80 96 dB
OS, dm
Enabled ≥(−VS + 1.8) V
Turn-Off Time 16 µs
Turn-On Time 0.6 µs
DISABLE
Pin Bias Current per Amplifier
Enabled
Disabled
DISABLE
DISABLE
= +3 V 0.3 1 µA
= 0 V −6 −3 µA
OPERATING TEMPERATURE RANGE −40 +125 °C
Rev. B | Page 6 of 32
Data Sheet ADA4940-1/ADA4940-2
ESD
3.5
0
–40 –20 0 20 40 60 12010080
MAXIMUM POWER DISSIPATION (W)
AMBIENT T E M P E RATURE (°C)
08452-004
0.5
1.0
1.5
2.0
2.5
3.0
ADA4940-2 (LFCSP )
ADA4940-1 (LFCSP )
ADA4940-1 (SOIC)
ABSOLUTE MAXIMUM RATINGS
Table 9.
Parameter Rating
Supply Voltage 8 V
V
±VS
OCM
Differential Input Voltage 1.2 V
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Field Induced Charged Device Model (FICDM) 1250 V
Human Body Model (HBM) 2000 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power dissipation is the voltage between the supply pins (±V
times the quiescent current (I
). The load current consists of the
S
differential and common-mode currents flowing to the load, as
well as currents flowing through the external feedback networks
and internal common-mode feedback loop. The internal
resistor tap used in the common-mode feedback loop places a
negligible differential load on the output. RMS voltages and
currents should be considered when dealing with ac signals.
Airflow reduces θ
. In addition, more metal directly in contact
JA
with the package leads from metal traces, through holes, ground,
and power planes reduces the θ
JA
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC (θ
158°C/W, single)the 16-lead LFCSP (θ
24-lead LFCSP (θ
standard 4-layer board. θ
= 65.1°C /W, dual) packages on a JEDEC
JA
values are approximations.
JA
) is the sum of the
D
.
= 91.3°C/W, single) and
JA
)
S
=
JA
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered on a circuit board in still air.
Table 10.
Package Type θJA Unit
8-Lead SOIC (Single)/4-Layer Board 158 °C/W
16-Lead LFCSP (Single)/4-Layer Board 91.3 °C/W
24-Lead LFCSP (Dual)/4-Layer Board 65.1 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4940-1/
ADA4940-2 packages is limited by the associated rise in
junction temperature (T
which is the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
can change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
ADA4940-1/ADA4940-2. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
) on the die. At approximately 150°C,
J
Figure 3. Maximum Safe Power Dissipation vs. Ambient Temperature
ESD CAUTION
Rev. B | Page 7 of 32
ADA4940-1/ADA4940-2 Data Sheet
1–FB
2+IN
3–IN
4+FB
11 –OUT
12 DISABLE
10 +OUT
9 V
OCM
5+V
S
6+V
S
7+V
S
8+V
S
15
–V
S
16
–V
S
14
–V
S
13
–V
S
ADA4940-1
08452-101
NOTES
1. CONNECT THE EXPOSE D P AD TO
–VS OR GROUND.
08452-003
–IN
1
V
OCM
2
+V
S
3
+OUT
4
+IN
8
DISABLE
7
–V
S
6
–OUT
5
ADA4940-1
paddle (EPAD)
ground.
5
−OUT
Negative Output for Load
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. ADA4940-1 Pin Configuration (16-Lead LFCSP)
Figure 5.ADA4940-1 Pin Configuration (SOIC)
Table 11. ADA4940-1 Pin Function Descriptions (16-Lead
LFCSP)
Pin No. Mnemonic Description
1 −FB Negative Output for Feedback
Component Connection.
2 +IN Positive Input Summing Node.
3 −IN Negative Input Summing Node.
4 +FB Positive Output for Feedback
Component Connection.
5 to 8 +VS Positive Supply Voltage.
9 V
Output Common-Mode Voltage.
OCM
10 +OUT Positive Output for Load
Connection.
11 −OUT Negative Output for Load
Connection.
12
DISABLE
Disable Pin.
13 to 16 −VS Negative Supply Voltage.
Exposed
Connect the exposed pad to −VS or
Table 12. ADA4940-1 Pin Function Descriptions (8-Lead
SOIC)
Pin No. Mnemonic Description
1 −IN Negative Input Summing Node.
2 V
Output Common-Mode Voltage.
OCM
3 +VS Positive Supply Voltage.
4 +OUT Positive Output for Load
Connection.
Connection.
6 −VS Negative Supply Voltage.
7
DISABLE
Disable Pin.
8 +IN Positive Input Summing Node.
Rev. B | Page 8 of 32
Data Sheet ADA4940-1/ADA4940-2
ADA4940-2
1–IN1
2+FB1
3+V
S1
4+V
S1
5–FB2
6+IN2
15
–V
S2
16 –V
S2
17 V
OCM1
18 +OUT1
14
DISABLE2
13 –OUT2
7–IN2
8+FB2
9+V
S2
11V
OCM2
12+OUT2
10+V
S2
21
–V
S1
22
–V
S1
23
–FB1
24
+IN1
20
DISABLE1
19
–OUT1
08452-102
NOTES
1. CONNECT THE EXPOSE D P AD TO
–V
S
OR GROUND.
13
−OUT2
Negative Output 2.
Exposed paddle (EPAD)
Connect the exposed pad to −VS or ground.
Figure 6. ADA4940-2 Pin Configuration (24-Lead LFCSP)
Table 13. ADA4940-2 Pin Function Descriptions (24-Lead LFCSP)
Pin No. Mnemonic Description
1 −IN1 Negative Input Summing Node 1.
2 +FB1 Positive Output Feedback Pin 1.
3, 4 +VS1 Positive Supply Voltage 1.
5 −FB2 Negative Output Feedback Pin 2.
6 +IN2 Positive Input Summing Node 2.
7 −IN2 Negative Input Summing Node 2.
8 +FB2 Positive Output Feedback Pin 2.
9, 10 +VS2 Positive Supply Voltage 2.
11 V
Output Common-Mode Voltage 2.
OCM2
12 +OUT2 Positive Output 2.
14
DISABLE2
Disable Pin 2.
15, 16 −VS2 Negative Supply Voltage 2.
17 V
Output Common-Mode Voltage 1.
OCM1
18 +OUT1 Positive Output 1.
19 −OUT1 Negative Output 1.
20
DISABLE1
Disable Pin 1.
21, 22 −VS1 Negative Supply Voltage 1.
23 −FB1 Negative Output Feedback Pin 1.
24 +IN1 Positive Input Summing Node 1.
Rev. B | Page 9 of 32
ADA4940-1/ADA4940-2 Data Sheet
3
–9
0.1 1 10 100 1000
NORMALIZED GAIN (d B)
FREQUENCY (MHz)
08452-006
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
V
OUT, dm
= 0.1V p-p
G = 2, RL = 1kΩ
G = 2, RL = 200Ω
G = 1, RL = 200Ω
G = 1, R
L
= 1kΩ
08452-007
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
0.1 1 10 100 1000
GAIN (dB)
FREQUENCY (MHz)
V
OUT, dm
= 0.1V p-p
V
S
= ±3.5V
VS = ±2.5V
VS = ±1.5V
3
–9
0.1 1 10 100 1000
NORMALIZED GAIN (d B)
FREQUENCY (MHz)
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
V
OUT
= 2V p-p
G = 2, R
L
= 1kΩ
G = 1, RL = 1kΩ
08452-009
G = 1, RL = 200Ω
G = 2, RL = 200Ω
08452-010
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
0.1 1 10 100 1000
GAIN (dB)
FREQUENCY (MHz)
V
OUT
= 2V p-p
V
S
= ±3.5V
V
S
= ±2.5V
V
S
= ±1.5V
3
–9
1 10 100 1000
GAIN (dB)
FREQUENCY (MHz)
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
V
OUT, dm
= 2V p-p
08452-011
–40°C
+25°C
+125°C
3
–9
1 10 100 1000
GAIN (dB)
FREQUENCY (MHz)
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
V
OUT, dm
= 0.1V p-p
08452-008
–40°C
+25°C
+125°C
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±2.5 V, G = 1, RF = RG = 1 kΩ, RT = 52.3 Ω (when used), RL = 1 kΩ, unless otherwise noted. See Figure 59 and Figure 60 for the
test circuits.
Figure 7. Small Signal Frequency Response for Various Gains and Loads
(LFCSP)
Figure 8. Small Signal Frequency Response for Various Supplies (LFCSP)
Figure 10. Large Signal Frequency Response for Various Gains and Loads
Figure 11. Large Signal Frequency Response for Various Supplies
Figure 9. Small Signal Frequency Response for Various Temperatures (LFCSP)
Figure 12. Large Signal Frequency Response for Various Temperatures
Rev. B | Page 10 of 32
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