Datasheet ADA4939-1, ADA4939-2 Datasheet (ANALOG DEVICES)

Ultralow Distortion

–

FEATURES

Extremely low harmonic distortion

−102 dBc HD2 @ 10 MHz

−83 dBc HD2 @ 70 MHz

−77 dBc HD2 @ 100 MHz

−101 dBc HD3 @ 10 MHz

−97 dBc HD3 @ 70 MHz

−91 dBc HD3 @ 100 MHz
Low input voltage noise: 2.3 nV/√Hz
High speed

−3 dB bandwidth of 1.4 GHz, G = 2

Slew rate: 6800 V/μs, 25% to 75%

Fast overdrive recovery of <1 ns
±0.5 mV typical offset voltage
Externally adjustable gain
Stable for differential gains ≥2
Differential-to-differential or single-ended-to-differential

operation
Adjustable output common-mode voltage
Single-supply operation: 3.3 V to 5 V

APPLICATIONS

ADC drivers
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
Line drivers

GENERAL DESCRIPTION

The ADA4939 is a low noise, ultralow distortion, high speed
differential amplifier. It is an ideal choice for driving high
performance ADCs with resolutions up to 16 bits from dc to
100 MHz. The output common-mode voltage is user adjustable
by means of an internal common-mode feedback loop, allowing
the ADA4939 output to match the input of the ADC. The internal
feedback loop also provides exceptional output balance as well as
suppression of even-order harmonic distortion products.

With the ADA4939, differential gain configurations are easily
realized with a simple external feedback network of four resistors
that determine the closed-loop gain of the amplifier.

The ADA4939 is fabricated using Analog Devices, Inc., proprietary
silicon-germanium (SiGe), complementary bipolar process,
enabling it to achieve very low levels of distortion with an input
voltage noise of only 2.3 nV/√Hz. The low dc offset and excellent
dynamic performance of the ADA4939 make it well suited for a
wide variety of data acquisition and signal processing applications.

Differential ADC Driver

ADA4939-1/ADA4939-2

FUNCTIONAL BLOCK DIAGRAMS

1–FB

2+IN

3–IN

4+FB

1–IN1
2+FB1
3+V

S1

4+V

S1

5–FB2
6+IN2

60

–65

–70

–75

–80

–85

–90

–95

HARMONIC DIST ORTIO N (dBc)

–100

–105

–110

1 10 100

The ADA4939 is available in a Pb-free, 3 mm × 3 mm 16-lead
LFCSP (ADA4939-1, single) or a Pb-free, 4 mm × 4 mm 24-lead
LFCSP (ADA4939-2, dual). The pinout has been optimized to
facilitate PCB layout and minimize distortion. The ADA4939-1
and the ADA4939-2 are specified to operate over the −40°C to
+105°C temperature range; both operate on supplies between

3.3 V and 5 V.

= 2V p-p

V

OUT, dm

HD2
HD3

Figure 3. Harmonic Distortion vs. Frequency

S

S

S

S

–V

–V

–V

–V

14

13

15

16

ADA4939-1

5

6

S

S

+V

+V

12 PD

11 –OUT

10 +OUT

9V

8

7

S

S

+V

+V

Figure 1. ADA4939-1

S1

S1

–V

–V

–FB1

+IN1

24

ADA4939-2

7

–IN2

PD1

–OUT1

20

19

21

22

23

18 + OUT1
17 V
16 – V
15

14
13 –O UT2

9

8

11

12

10

S2

S2

+V

+V

OCM2

+FB2

V

+OUT2

Figure 2. ADA4939-2

FREQUENCY (MHz)

–V
PD2

OCM

OCM1

S2
S2

07429-001

07429-002

07429-021

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

ADA4939-1/ADA4939-2

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagrams............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

5 V Operation ............................................................................... 3

3.3 V Operation ............................................................................5

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

Maximum Power Dissipation ..................................................... 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ...........................8

Typical Performance Characteristics............................................. 9

Test Circ uit s .....................................................................................15

Operational Description................................................................ 16

Definition of Terms.................................................................... 16

Theory of Operation ...................................................................... 17

Analyzing an Application Circuit............................................ 17

Setting the Closed-Loop Gain .................................................. 17

Stable for Gains ≥2..................................................................... 17

Estimating the Output Noise Voltage...................................... 17

Impact of Mismatches in the Feedback Networks................. 18

Calculating the Input Impedance for an Application Circuit

....................................................................................................... 19

Input Common-Mode Voltage Range .....................................21

Input and Output Capacitive AC-Coupling ........................... 21

Minimum R

Setting the Output Common-Mode Voltage.......................... 21

Layout, Grounding, and Bypassing.............................................. 22

High Performance ADC Driving ................................................. 23

Outline Dimensions .......................................................................24

Ordering Guide .......................................................................... 24

Value of 50 Ω...................................................... 21

G

REVISION HISTORY

5/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

ADA4939-1/ADA4939-2

SPECIFICATIONS

5 V OPERATION

TA = 25°C, +VS = 5 V, −VS = 0 V, V
All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to

±DIN to V

Performance

OUT, dm

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Small Signal Bandwidth V
Bandwidth for 0.1 dB Flatness V
V
Large Signal Bandwidth V
Slew Rate V
Overdrive Recovery Time VIN = 0 V to 1.5 V step, G = 3.16 <1 ns

NOISE/HARMONIC PERFORMANCE See Figure 41 for distortion test circuit

Second Harmonic V
V
V
Third Harmonic V
V
V
IMD f1 = 70 MHz, f2 = 70.1 MHz, V
f
Voltage Noise (RTI) f = 100 kHz 2.3 nV/√Hz
Input Current Noise f = 100 kHz 6 pA/√Hz
Crosstalk f = 100 MHz, ADA4939-2 −80 dB

INPUT CHARACTERISTICS

Offset Voltage V
T
Input Bias Current −26 −10 +2.2 μA
T
Input Offset Current −11.2 +0.5 +11.2 μA
Input Resistance Differential 180 kΩ
Common mode 450 kΩ
Input Capacitance 1 pF
Input Common-Mode Voltage 1.1 3.9 V
CMRR ∆V

OUTPUT CHARACTERISTICS

Output Voltage Swing Maximum ∆V
Linear Output Current 100 mA
Output Balance Error

= +VS/2, RF = 402 , RG = 200 , RT = 60.4  (when used), R

OCM

= 0.1 V p-p 1400 MHz

OUT, dm

= 0.1 V p-p, ADA4939-1 300 MHz

OUT, dm

= 0.1 V p-p, ADA4939-2 90 MHz

OUT, dm

= 2 V p-p 1400 MHz

OUT, dm

= 2 V p-p, 25% to 75% 6800 V/μs

OUT, dm

= 2 V p-p, 10 MHz −102 dBc

OUT, dm

= 2 V p-p, 70 MHz −83 dBc

OUT, dm

= 2 V p-p, 100 MHz −77 dBc

OUT, dm

= 2 V p-p, 10 MHz −101 dBc

OUT, dm

= 2 V p-p, 70 MHz −97 dBc

OUT, dm

= 2 V p-p, 100 MHz −91 dBc

OUT, dm

= 2 V p-p −95 dBc

OUT, dm

= 140 MHz, f2 = 140.1 MHz, V

1

= V

OS, dm

to T

MIN

to T

MIN

OUT, dm

∆V

OUT, cm

Figure 40 for test circuit

see

/2, V

OUT, dm

variation ±2.0 μV/°C

MAX

variation ±0.5 μA/°C

MAX

/∆V

IN, cm

OUT

/∆V

OUT, dm

= V

DIN+

, ∆V

= ±1 V −83 −77 dB

IN, cm

; single-ended output, RF = RG = 10 kΩ 0.9 4.1 V

, ∆V

OUT, dm

DIN−

= 1 V, 10 MHz,

= 2 V p-p −89 dBc

OUT, dm

= 2.5 V −3.4 ±0.5 +2.8 mV

= 1 kΩ, unless otherwise noted.

L, dm

Figure 42 for signal definitions.

−64 dB

Rev. 0 | Page 3 of 24

ADA4939-1/ADA4939-2

V

to V

OCM

Table 2.

Parameter Conditions Min Typ Max Unit

V

DYNAMIC PERFORMANCE

OCM

−3 dB Bandwidth 670 MHz
Slew Rate VIN = 1.5 V to 3.5 V, 25% to 75% 2500 V/μs
Input Voltage Noise (RTI) f = 100 kHz 7.5 nV/√Hz

V

INPUT CHARACTERISTICS

OCM

Input Voltage Range 1.3 3.5 V
Input Resistance 8.3 9.7 11.5 kΩ
Input Offset Voltage V
V

CMRR ΔV

OCM

Gain ΔV

General Performance

Table 3.

Parameter Conditions Min Typ Max Unit

POWER SUPPLY

Operating Range 3.0 5.25 V
Quiescent Current per Amplifier 35.1 36.5 37.7 mA
T
Powered down 0.26 0.32 0.38 mA
Power Supply Rejection Ratio ΔV

POWER-DOWN (PD)

PD Input Voltage
Enabled ≥2 V
Turn-Off Time 500 ns
Turn-On Time 100 ns
PD Pin Bias Current per Amplifier

Enabled
Disabled

OPERATING TEMPERATURE RANGE −40 +105 °C

Performance

OUT, cm

OS, cm

OUT, dm

OUT, cm

= V

OUT, cm

/ΔV

/ΔV

OCM

OCM

, V

= V

= +VS/2 −3.7 ±0.5 +3.7 mV

DIN−

= ±1 V −90 −73 dB
= ±1 V 0.97 0.98 0.99 V/V

variation 16 μA/°C

MAX

/ΔVS, ΔVS = 1 V −90 −80 dB

MIN

DIN+

, ΔV
, ΔV

to T

OUT, dm

OCM

OCM

Powered down ≤1 V

PD = 5 V
PD = 0 V

30 μA

−200 μA

Rev. 0 | Page 4 of 24

ADA4939-1/ADA4939-2

3.3 V OPERATION

TA = 25°C, +VS = 3.3 V, −VS = 0 V, V
All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to

±DIN to V

Performance

OUT, dm

Table 4.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Small Signal Bandwidth V
Bandwidth for 0.1 dB Flatness V
V
Large Signal Bandwidth V
Slew Rate V
Overdrive Recovery Time VIN = 0 V to 1.0 V step, G = 3.16 <1 ns

NOISE/HARMONIC PERFORMANCE See Figure 41 for distortion test circuit

Second Harmonic V
V
V
Third Harmonic V
V
V
IMD f1 = 70 MHz, f2 = 70.1 MHz, V
f
Voltage Noise (RTI) f = 100 kHz 2.3 nV/√Hz
Input Current Noise f = 100 kHz 6 pA/√Hz
Crosstalk f = 100 MHz, ADA4939-2 −80 dB

INPUT CHARACTERISTICS

Offset Voltage V
T
Input Bias Current −26 −10 +2.2 μA
T
Input Offset Current −11.2 ±0.4 +11.2
Input Resistance Differential 180 kΩ
Common mode 450 kΩ
Input Capacitance 1 pF
Input Common-Mode Voltage 0.9 2.4 V
CMRR ∆V

OUTPUT CHARACTERISTICS

Output Voltage Swing Maximum ∆V
Linear Output Current 75 mA
Output Balance Error

= +VS/2, RF = 402 , RG = 200 , RT = 60.4  (when used), R

OCM

= 0.1 V p-p 1400 MHz

OUT, dm

= 0.1 V p-p, ADA4939-1 300 MHz

OUT, dm

= 0.1 V p-p, ADA4939-2 90 MHz

OUT, dm

= 2 V p-p 1400 MHz

OUT, dm

= 2 V p-p, 25% to 75% 5000 V/μs

OUT, dm

= 2 V p-p, 10 MHz −100 dBc

OUT, dm

= 2 V p-p, 70 MHz −90 dBc

OUT, dm

= 2 V p-p, 100 MHz −83 dBc

OUT, dm

= 2 V p-p, 10 MHz −94 dBc

OUT, dm

= 2 V p-p, 70 MHz −82 dBc

OUT, dm

= 2 V p-p, 100 MHz −75 dBc

OUT, dm

= 2 V p-p −87 dBc

OUT, dm

= 140 MHz, f2 = 140.1 MHz, V

1

= V

OS, dm

to T

MIN

to T

MIN

OUT, dm

∆V

OUT, cm

Figure 40 for test circuit

see

/2, V

OUT, dm

variation ±2.0 μV/°C

MAX

variation ±0.5 μA/°C

MAX

/∆V

IN, cm

OUT

/∆V

OUT, dm

= V

DIN+

, ∆V

= ±1 V −85 −75 dB

IN, cm

, single-ended output, RF = RG = 10 kΩ 0.8 2.5 V

, ∆V

OUT, dm

DIN−

= 1 V, f = 10 MHz,

= 2 V p-p −70 dBc

OUT, dm

= +VS/2 −3.5 ±0.5 +3.5 mV

= 1 kΩ, unless otherwise noted.

L, dm

Figure 42 for signal definitions.

−61 dB

Rev. 0 | Page 5 of 24

ADA4939-1/ADA4939-2

V

to V

OCM

Table 5.

Parameter Conditions Min Typ Max Unit

V

DYNAMIC PERFORMANCE

OCM

−3 dB Bandwidth 560 MHz
Slew Rate VIN = 0.9 V to 2.4 V, 25% to 75% 1250 V/μs
Input Voltage Noise (RTI) f = 100 kHz 7.5 nV/√Hz

V

INPUT CHARACTERISTICS

OCM

Input Voltage Range 1.3 1.9 V
Input Resistance 8.3 9.7 11.2 kΩ
Input Offset Voltage V
V

CMRR ∆V

OCM

Gain ∆V

General Performance

Table 6.

Parameter Conditions Min Typ Max Unit

POWER SUPPLY

Operating Range 3.0 5.25 V
Quiescent Current per Amplifier 32.8 34.5 36.0 mA
T
Powered down 0.16 0.20 0.26 mA
Power Supply Rejection Ratio ∆V

POWER-DOWN (PD)

PD Input Voltage
Enabled ≥2 V
Turn-Off Time 500 ns
Turn-On Time 100 ns
PD Pin Bias Current per Amplifier

Enabled
Disabled

OPERATING TEMPERATURE RANGE −40 +105 °C

Performance

OUT, cm

= V

OS, cm

OUT, dm

OUT, cm

to T

MIN

OUT, dm

variation 16 μA/°C

MAX

/∆VS, ∆VS = 1 V −84 −72 dB

OUT, cm

/∆V

/∆V

OCM

OCM

, V

= V

= 1.67 V −3.7 ±0.5 +3.7 mV

DIN−

= ±1 V −75 −73 dB
= ±1 V 0.97 0.98 0.99 V/V

, ∆V
, ∆V

DIN+

OCM

OCM

Powered down ≤1 V

PD = 3.3 V
PD = 0 V

26 μA

−137 μA

Rev. 0 | Page 6 of 24

ADA4939-1/ADA4939-2

ABSOLUTE MAXIMUM RATINGS

Table 7.

Parameter Rating

Supply Voltage 5.5 V
Power Dissipation See Figure 4

Input Current, +IN, −IN,

PD

±5 mA

Storage Temperature Range −65°C to +125°C
Operating Temperature Range

ADA4939-1 −40°C to +105°C

ADA4939-2 −40°C to +105°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

THERMAL RESISTANCE

θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 2s2p circuit board, as described
in EIA/JESD 51-7.

The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (V

) times the quiescent current (IS).

S

The power dissipated due to the load drive depends upon the
particular application. The power due to load drive is calculated
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.

Airflow increases heat dissipation, effectively reducing θ
addition, more metal directly in contact with the package leads/
exposed pad from metal traces, through holes, ground, and power
planes reduces θ

.

JA

Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the single 16-lead
LFCSP (98°C/W) and the dual 24-lead LFCSP (67°C/W) on a
JEDEC standard four-layer board with the exposed pad
soldered to a PCB pad that is connected to a solid plane.

3.0

2.5

ADA4939-2

2.0

) is the sum of the

D

JA

. In

Table 8. Thermal Resistance

Package Type θ

Unit

JA

ADA4939-1, 16-Lead LFCSP (Exposed Pad) 98 °C/W
ADA4939-2, 24-Lead LFCSP (Exposed Pad) 67 °C/W

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the ADA4939 package
is limited by the associated rise in junction temperature (T
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the ADA4939. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.

) on

J

1.5

ADA4939-1

1.0

0.5

MAXIMUM POWER DISSIPATION (W)

0

–40 100806040200–20

Figure 4. Maximum Power Dissipation vs. Ambient Temperature for

AMBIENT TEM PERATURE (°C)

a Four-Layer Board

ESD CAUTION

07429-004

Rev. 0 | Page 7 of 24

ADA4939-1/ADA4939-2

+

–

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

S

S

S

1–FB

2+IN

ADA4939-1

3–IN

(Not to Scale)

4+FB

–V

–V

15

16

PIN 1
INDICATO R

TOP VIEW

5

6

S

S

+V

+V

S

–V

–V

14

13

12 PD

11 –OUT

10 +OUT

9V

OCM

8

7

S

S

+V

+V

07429-005

–IN1

FB1
+V
+V

FB2

+IN2

S1
S1

1
2
3

ADA4939-2

4
5

(Not to Scale)

6

FB1

+IN1

22

23

24

PIN 1
INDICATOR

TOP VIEW

9

7

8

S2

N2
–I

+V

+FB2

–OUT1

–VS1–VS1–

PD1

20

19

21

+OUT1

18
17

V

OCM1

16

–V

S2

–V

15

S2

14

PD2
–OUT2

13

11

12

10

S2

+V

OCM2

V

+OUT2

7429-006

Figure 5. ADA4939-1 Pin Configuration

Figure 6. ADA4939-2 Pin Configuration

Table 9. ADA4939-1 Pin Function Descriptions

Pin No. Mnemonic Description

1 −FB Negative Output for Feedback Component Connection
2 +IN Positive Input Summing Node
3 −IN Negative Input Summing Node
4 +FB Positive Output for Feedback Component Connection
5 to 8 +V
9 V

S

OCM

Positive Supply Voltage

Output Common-Mode Voltage
10 +OUT Positive Output for Load Connection
11 −OUT Negative Output for Load Connection
12

PD

13 to 16 −V

S

Power-Down Pin

Negative Supply Voltage

Table 10. ADA4939-2 Pin Function Descriptions

Pin No. Mnemonic Description

1 −IN1 Negative Input Summing Node 1
2 +FB1 Positive Output Feedback 1
3, 4 +V

S1

Positive Supply Voltage 1
5 −FB2 Negative Output Feedback 2
6 +IN2 Positive Input Summing Node 2
7 −IN2 Negative Input Summing Node 2
8 +FB2 Positive Output Feedback 2
9, 10 +V
11 V

S2

OCM2

Positive Supply Voltage 2

Output Common-Mode Voltage 2
12 +OUT2 Positive Output 2
13 −OUT2 Negative Output 2
14

PD2
15, 16 −V
17 V

S2

OCM1

Power-Down Pin 2
Negative Supply Voltage 2

Output Common-Mode Voltage 1
18 +OUT1 Positive Output 1
19 −OUT1 Negative Output 1
20

PD1

21, 22 −V

S1

Power-Down Pin 1

Negative Supply Voltage 1
23 −FB1 Negative Output Feedback 1
24 +IN1 Positive Input Summing Node 1

Rev. 0 | Page 8 of 24

ADA4939-1/ADA4939-2

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, +VS = 5 V, −VS = 0 V, V
Refer to

Figure 39 for test setup. Refer to Figure 42 for signal definitions.

2

V

= 100mV p-p

OUT, dm

0

= +VS /2, RG = 200 , RF = 402 , RT = 60.4 Ω, G = 1, R

OCM

2

V

0

OUT, dm

= 1 kΩ, unless otherwise noted.

L, dm

= 2V p-p

–2

–4

–6

–8

–10

–12

NORMALIZE D CLOSED-LOOP GAIN (dB)

–14

G = +2.00
G = +3.16
G = +5.00

1 10 100 1k

RG = 200Ω, RT = 60.4Ω

= 127Ω, RT = 66.3Ω

R

G

= 80.6Ω, RT = 76.8Ω

R

G

FREQUENCY (MHz)

Figure 7. Small Signal Frequency Response for Various Gains

3

V

= 100mV p-p

OUT, dm

2

1

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

–10

NORMALIZE D CLOSED-LOOP GAIN (dB)

–11

–12

VS = 3.3V
VS = 5.0V

1 10 100 1k

FREQUENCY (MHz)

Figure 8. Small Signal Frequency Response for Various Supplies

3

V

= 100mV p-p

OUT, dm

2

1

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

–10

NORMALIZE D CLOSED-LOOP GAIN (dB)

–11

–12

–40°C
+25°C
+105°C

1 10 100 1k

FREQUENCY (MHz)

Figure 9. Small Signal Frequency Response for Various Temperatures

–2

–4

–6

–8

–10

–12

NORMALIZE D CLOSED-LOOP GAIN (dB)

–14

07429-007

G = +2.00
G = +3.16
G = +5.00

1 10 100 1k

RG = 200Ω, RT = 60.4Ω

= 127Ω, RT = 66.3Ω

R

G

= 80.6Ω, RT = 76.8Ω

R

G

FREQUENCY (MHz)

07429-010

Figure 10. Large Signal Frequency Response for Various Gains

2

V

= 2V p-p

OUT, dm

0

–2

–4

–6

–8

–10

NORMALIZE D CLOSED-LOOP GAIN (dB)

–12

07429-008

VS = 3.3V
VS = 5.0V

1 10 100 1k

FREQUENCY (MHz)

07429-011

Figure 11. Large Signal Frequency Response for Various Supplies

3

V

= 2V p-p

OUT, dm

2

1

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

–10

NORMALIZE D CLOSED-LOOP GAIN (dB)

–11

–12

07429-009

–40°C
+25°C
+105°C

1 10 100 1k

FREQUENCY (MHz)

07429-012

Figure 12. Large Signal Frequency Response for Various Temperatures

Rev. 0 | Page 9 of 24

ADA4939-1/ADA4939-2

–

3

V

= 100mV p-p

OUT, dm

2

1

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

–10

NORMALIZE D CLOSED-LOOP GAIN (dB)

–11

–12

RL = 1kΩ
RL = 200Ω

1 10 100 1k

FREQUENCY (MHz)

Figure 13. Small Signal Frequency Response for Various Loads

6

V

= 100mV p-p

OUT, dm

3

0

GAIN (dB)

–3

OCM

V

–6

V

= 1.0V

OCM

V

= 3.9V

OCM

V

= 2.5V

–9

Figure 14. V

OCM

1 10 100 1k

Small Signal Frequency Response at Various DC Levels

OCM

FREQUENCY (MHz )

0.5
V

= 100mV p-p

OUT, dm

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

NORMALIZE D CLOSED-LOOP GAIN (dB)

–0.4

–0.5

RL = 1kΩ
RL = 200Ω

RL = 1kΩ OUT1
RL = 1kΩ OUT2

RL = 200Ω OUT1
RL = 200Ω OUT2

1 10 100 1k

FREQUENCY (MHz )

07429-013

07429-019

07429-020

3

V

= 2V p-p

OUT, dm

2

1

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

–10

NORMALIZE D CLOSED-LOOP GAIN (dB)

–11

–12

RL = 1kΩ
RL = 200Ω

1 10 100 1k

FREQUENCY (MHz)

Figure 16. Large Signal Frequency Response for Various Loads

–55

V

= 2V p-p

OUT, dm

HARMONIC DIST ORTIO N (dBc)

–60

–65

–70

–75

–80

–85

–90

–95

–100

–105

–110

–115

HD2, G = 2
HD3, G = 2
HD2, G = 3.16
HD3, G = 3.16
HD2, G = 5
HD3, G = 5

1 10 100

FREQUENCY (MHz)

Figure 17. Harmonic Distortion vs. Frequency at Various Gains

HARMONIC DIST ORTIO N (dBc)

60

–65

–70

–75

–80

–85

–90

–95

–100

–105

–110

= 2V p-p

V

OUT, dm

= ±2.5V

V

S

HD2, R
HD3, R
HD2, R
HD3, R

1 10 100

L, dm

L, dm

L, dm

L, dm

= 1kΩ
= 1kΩ
= 200Ω
= 200Ω

FREQUENCY (MHz)

07429-016

07429-022

07429-023

Figure 15. 0.1 dB Flatness Small Signal Response for Various Loads

Figure 18. Harmonic Distortion vs. Frequency at Various Loads

Rev. 0 | Page 10 of 24

ADA4939-1/ADA4939-2

–

–

–

–

–

60

–65

–70

–75

–80

–85

–90

–95

HARMONIC DIST ORTIO N (dBc)

–100

–105

–110

1 10 100

= 2V p-p

V

OUT, dm

HD2, VS (SPLIT SUPPLY) = ±2.5V
HD3, VS (SPLIT SUPPLY) = ±2.5V
HD2, VS (SPLIT SUPPLY) = ±1.65V
HD3, VS (SPLIT SUPPLY) = ±1.65V

FREQUENCY (MHz)

07429-062

DISTORTION (dBc)

40

–50

–60

–70

–80

–90

–100

–110

–120

–130

07654321

V

OUT, dm

(V p-p)

HD2, VS = 5.0
HD3, VS = 5.0
HD2, VS = 3.3
HD3, VS = 3.3

07429-024

Figure 19. Harmonic Distortion vs. Frequency at Various Supplies

40

–50

–60

–70

–80

–90

DISTORTION (dBc)

–100

–110

–120

1.0 4. 03.83.63.43. 23.02.82. 62.42.22.01.81.61.41.2

Figure 20. Harmonic Distortion vs. V

V

OUT, dm

V

OCM

= 2V p-p

HD2, f = 10MHz
HD3, f = 10MHz
HD2, f = 70MHz
HD3, f = 70MHz

(V)

at Various Frequencies

OCM

40

–50

–60

–70

–80

–90

–100

DISTORTION (dBc)

–110

–120

–130

1.21.41.61.82

V

OUT, dm

V

OCM

= 2V p-p

(V)

HD2, f = 10MHz
HD3, f = 10MHz
HD2, f = 70MHz
HD3, f = 70MHz

07429-025

.0

07429-026

Figure 22. Harmonic Distortion vs. V

10

V

= 2V p-p

OUT, dm

0

V

= ±2.5V

S

–10

–20

–30

–40

–50

–60

–70

–80

NORMALIZ ED SPECTRUM (d Bc)

–90

–100

–110

69.5 70.570.470.370.270.170.069. 969.869.769.6

FREQUENCY (MHz )

Figure 23. 70 MHz Intermodulation Distortion

30

R

= 200Ω

L, dm

–35

–40

–45

–50

CMRR (dB)

–55

–60

–65

–70

110100

FREQUENCY (MHz )

and Supply Voltage, f = 10 MHz

OUT, dm

07429-028

1k

07429-029

Figure 21. Harmonic Distortion vs. V

at Various Frequencies

OCM

Figure 24. CMRR vs. Frequency

Rev. 0 | Page 11 of 24

ADA4939-1/ADA4939-2

–

–

–

–70

–80

60

V

=HD2, = 1V p-p

OUT, dm

V

=HD3, = 1V p-p

OUT, dm

V

=HD2, = 2V p-p

OUT, dm

V

=HD3, = 2V p-p

OUT, dm

VS = ±1.65V

–35

–40

–45

30

R

= 200Ω

L, dm

–90

–100

HARMONIC DIST ORTIO N (dBc)

–110

–120

1 10 100

FREQUENCY (MHz)

07429-027

Figure 25. Harmonic Distortion vs. Frequency at Various Output Voltages

30

R

= 200Ω

L, dm

–40

–50

–60

–70

PSRR (dB)

–80

–90

–100

110100

FREQUENCY (MHz )

Figure 26. PSRR vs. Frequency, R

= 200 Ω

L

1k

–50

–55

OUTPUT BALANCE (dB)

–60

–65

–70

110100

FREQUENCY (MHz )

1k

07429-030

Figure 28. Output Balance vs. Frequency

70

60

50

40

30

GAIN (dB)

20

10

0

–10

0.01 10k1k1001010.1

07429-031

PHASE

GAIN

FREQUENCY (MHz)

100

50

0

–50

–100

–150

–200

–250

–300

–350

PHASE (Degrees)

07429-034

Figure 29. Open-Loop Gain and Phase vs. Frequency

0

R

= 200Ω

L, dm

–5

–10

–15

–20

–25

–30

–35

S-PARAMETERS (dB)

–40

–45

–50

1 10 100 1k

FREQUENCY (MHz)

Figure 27. Return Loss (S11, S22) vs. Frequency

S22

S11

07429-032

Rev. 0 | Page 12 of 24

VOLTAGE (V)

8

6

4

2

0

–2

–4

–6

–8

065040302010

V

OUT

VIN × 3.16V

TIME (ns)

Figure 30. Overdrive Recovery, G = 3.16

0

07429-035

ADA4939-1/ADA4939-2

–

–

60

V

= 2V p-p

OUT, dm

V

= ±2.5V

–65

S

–70

–75

–80

–85

–90

–95

–100

SPURIOUS-F REE DYNAMIC RANGE (dBc)

–105

1 10 100

FREQUENCY (MHz)

R

L

= 200Ω

RL = 1kΩ

07429-033

Figure 31. Spurious-Free Dynamic Range vs. Frequency at Various Loads

0.12

40

R

= 200Ω

L, dm

–50

–60

–70

–80

–90

–100

CROSSTALK (d B)

–110

–120

–130

–140

1110010

INPUT AMP 1 T O OUTPUT AMP 2

INPUT AMP 2 TO OUTPUT AMP 1

FREQUENCY (MHz)

Figure 34. Crosstalk vs. Frequency for ADA4939-2

4

k

07429-044

0.10

0.08

0.06

0.04

OUTPUT VOL TAGE (V)

0.02

0

–0.02

01

TIME (ns)

0987654321

07429-038

Figure 32. Small Signal Pulse Response

3

2

1

0

–1

OUTPUT VOL TAGE (V)

–2

–3

–4

010987654321

Figure 35. Large Signal Pulse Response

2.60

2.55

2.50

4.5

4.0

3.5

3.0

2.5

2.0

TIME (ns)

07429-041

2.45

OUTPUT COMMON-MODE VOLTAGE (V)

2.40

02

Figure 33. V

TIME (ns)

Small Signal Pulse Response

OCM

018161412108642

07429-039

1.5

1.0

OUTPUT COMMON-MODE VOLTAGE (V)

0.5
02018161412108642

Figure 36. V

TIME (ns)

Large Signal Pulse Response

OCM

07429-042

Rev. 0 | Page 13 of 24

ADA4939-1/ADA4939-2

3.5

3.0

V

2.5

2.0

1.5

VOLTAGE (V)

1.0

0.5

0

OUT, dm

PD

R

L, dm

= 200Ω

1k

100

10

INPUT VOLTAGE NO ISE (nV/ Hz)

–0.5

0 1000900800700600500400300200100

Figure 37.

TIME (ns)

PD

Response Time

07429-043

1

10 10M1M100k10k1k100

FREQUENCY (Hz)

Figure 38. Voltage Noise Spectral Density, RTI

07429-045

Rev. 0 | Page 14 of 24

ADA4939-1/ADA4939-2

Ω

Ω

TEST CIRCUITS

402

5V

0.1µF

200Ω50Ω

V

IN

60.4Ω

V

OCM

200Ω

0.1µF

ADA4939

402Ω

1kΩ

07429-046

Figure 39. Equivalent Basic Test Circuit, G = 2

NETWORK
ANALYZER

OUTPUT

AC-COUPLED

V

IN

200Ω50Ω

V

60.4Ω

OCM

200Ω

0.1µF

60.4Ω

Figure 40. Test Circuit for Output Balance, CMRR

402Ω

+2.5V

ADA4939

–2.5V

402Ω

49.9Ω

49.9Ω

49.9Ω

49.9Ω

NETWORK
ANALYZER

INPUT

AC-COUPLED

50Ω

07429-047

402

5V

442Ω

442Ω

200Ω

0.1µF

LOW-PASS

FILTER

V

IN

200Ω50Ω

V

60.4Ω 261Ω

OCM

200Ω

0.1µF

ADA4939

402Ω

0.1µF

0.1µF

50Ω

2:1

CT

DUAL

FILTER

07429-048

Figure 41. Test Circuit for Distortion Measurements

Rev. 0 | Page 15 of 24

ADA4939-1/ADA4939-2

–

V

OPERATIONAL DESCRIPTION

DEFINITION OF TERMS

FB

R

F

R

G

+D

–D

IN

OCM

IN

+FB

+IN

ADA4939

–IN

R

G

R

F

Figure 42. Circuit Definitions

Differential Voltage

Differential voltage refers to the difference between two
node voltages. For example, the output differential voltage (or
equivalently, output differential-mode voltage) is defined as

V

where V

OUT, dm

+OUT

= (V

and V

− V

+OUT

−OUT

refer to the voltages at the +OUT and

−OUT

−OUT terminals with respect to a common reference.

–OUT

V

R

OUT, dm

L, dm

+OUT

07429-049

)

Common-Mode Voltage

Common-mode voltage refers to the average of two node
voltages. The output common-mode voltage is defined as

V

OUT, cm

= (V

+OUT

+ V

−OUT

)/2

Balance

Output balance is a measure of how close the differential signals
are to being equal in amplitude and opposite in phase. Output
balance is most easily determined by placing a well-matched
resistor divider between the differential voltage nodes and
comparing the magnitude of the signal at the divider midpoint
with the magnitude of the differential signal (see

Figure 39). By
this definition, output balance is the magnitude of the output
common-mode voltage divided by the magnitude of the output
differential mode voltage.

ErrorBalanceOutput

V

dmOUT

,

V

cmOUT

,

=

Rev. 0 | Page 16 of 24

ADA4939-1/ADA4939-2

V

V

THEORY OF OPERATION

The ADA4939 differs from conventional op amps in that it has
two outputs whose voltages move in opposite directions and an
additional input, V

. Like an op amp, it relies on high open-

OCM

loop gain and negative feedback to force these outputs to the
desired voltages. The ADA4939 behaves much like a standard
voltage feedback op amp and facilitates single-ended-to-differential
conversions, common-mode level shifting, and amplifications of
differential signals. Like an op amp, the ADA4939 has high input
impedance and low output impedance. Because it uses voltage
feedback, the ADA4939 manifests a nominally constant gain­bandwidth product.

Two feedback loops are employed to control the differential and
common-mode output voltages. The differential feedback, set
with external resistors, controls only the differential output voltage.
The common-mode feedback controls only the common-mode
output voltage. This architecture makes it easy to set the output
common-mode level to any arbitrary value within the specified
limits. The output common-mode voltage is forced, by the internal
common-mode feedback loop, to be equal to the voltage applied
to the V

OCM

input.

The internal common-mode feedback loop produces outputs
that are highly balanced over a wide frequency range without
requiring tightly matched external components. This results in
differential outputs that are very close to the ideal of being
identical in amplitude and are exactly 180° apart in phase.

ANALYZING AN APPLICATION CIRCUIT

The ADA4939 uses high open-loop gain and negative feedback
to force its differential and common-mode output voltages in
such a way as to minimize the differential and common-mode
error voltages. The differential error voltage is defined as the
voltage between the differential inputs labeled +IN and −IN
(see

Figure 42). For most purposes, this voltage can be assumed
to be zero. Similarly, the difference between the actual output
common-mode voltage and the voltage applied to V
be assumed to be zero. Starting from these two assumptions,
any application circuit can be analyzed.

can also

OCM

SETTING THE CLOSED-LOOP GAIN

The differential-mode gain of the circuit in Figure 42 can be
determined by

V

V

This presumes that the input resistors (R
(R

) on each side are equal.

F

R

,

dmOUT

F

=

R

,

dmIN

G

) and feedback resistors

G

STABLE FOR GAINS ≥2

The ADA4939 frequency response exhibits excessive peaking
for differential gains <2; therefore, the part should be operated
with differential gains ≥2.

ESTIMATING THE OUTPUT NOISE VOLTAGE

The differential output noise of the ADA4939 can be estimated
using the noise model in
voltage density, v
noise currents, i

nIN

nIN−

ground. The output voltage due to v
v

by the noise gain, GN (defined in the GN equation that

nIN

follows). The noise currents are uncorrelated with the same
mean-square value, and each produces an output voltage that is
equal to the noise current multiplied by the associated feedback
resistance. The noise voltage density at the V
When the feedback networks have the same feedback factor, as
in most cases, the output noise due to v
Each of the four resistors contributes (4kTR
from the feedback resistors appears directly at the output, and
the noise from the gain resistors appears at the output multiplied
by R

. Table 11 summarizes the input noise sources, the

F/RG

multiplication factors, and the output-referred noise density terms.

nRG1

Figure 43. The input-referred noise
, is modeled as a differential input, and the
and i

R

G1

i

nIN+

i

nIN–

, appear between each input and

nIN+

is obtained by multiplying

nIN

pin is v

OCM

is common-mode.

nCM

1/2

)

. The noise

xx

nRF1

R

F1

+

V

nIN

ADA4939

V

nOD

nCM

.

V

OCM

V

V

nRG2

R

G2

R

F2

Figure 43. Noise Model

V

nRF2

nCM

07429-050

Rev. 0 | Page 17 of 24

ADA4939-1/ADA4939-2

Table 11. Output Noise Voltage Density Calculations for Matched Feedback Networks

Input Noise

Input Noise Contribution Input Noise Term

Differential Input v
Inverting Input i
Noninverting Input i
V

Input v

OCM

Gain Resistor R
Gain Resistor R
Feedback Resistor R
Feedback Resistor R

G1

G2

F1

F2

nIN

i

nIN

i

nIN

nCM

v

nRG1

v

nRG2

v

nRF1

v

nRF2

Voltage Density

v

nIN

× (RF2) 1 v

nIN

× (RF1) 1 v

nIN

v

nCM

1/2

(4kTRG1)

1/2

(4kTRG2)

1/2

(4kTRF1)

1/2

(4kTRF2)

Table 12. Differential Input, DC-Coupled

Nominal Gain (dB) RF (Ω) RG (Ω) R

(Ω) Differential Output Noise Density (nV/√Hz)

IN, dm

6 402 200 400 9.7
10 402 127 254 12.4
14 402 80.6 161 16.6

Table 13. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω

Nominal Gain (dB) RF (Ω) RG1 (Ω) RT (Ω) R

IN, cm

(Ω) R

(Ω)1Differential Output Noise Density (nV/√Hz)

G2

6 402 200 60.4 301 228 9.1
10 402 127 66.5 205 155 11.1
14 402 80.6 76.8 138 111 13.5

1

RG2 = RG1 + (RS||RT).

Similar to the case of a conventional op amp, the output noise
voltage densities can be estimated by multiplying the input­referred terms at +IN and −IN by the appropriate output factor,

where:

2

=

N

()

β+=

1

F1

When the feedback factors are matched, R

is the circuit noise gain.

ββG+

21

R

G1

RR

G1

and

β+=

2

R

G2

are the feedback factors.

RR

F2

G2

= RF2/RG2, β1 =

F1/RG1

β2 = β, and the noise gain becomes

R

1

G +== 1

N

β

Note that the output noise from V
The total differential output noise density, v

F

R

G

goes to zero in this case.

OCM

, is the root-sum-

nOD

square of the individual output noise terms.

8

2

=

vv

∑

nOinOD

1i

=

Table 12 and Table 1 3 list several common gain settings,
associated resistor values, input impedance, and output noise
density for both balanced and unbalanced input configurations.

Rev. 0 | Page 18 of 24

Output
Multiplication Factor

G

N

0 v
RF1/R

G1

RF2/R

G2

1 v
1 v

Differential Output Noise
Voltage Density Term

v

= GN(v

nO1

= (i

nO2

= (i

nO3

= 0

nO4

v

= (RF1/RG1)(4kTRG1)

nO5

v

= (RF2/RG2)(4kTRG2)

nO6

= (4kTRF1)

nO7

= (4kTRF2)

nO8

nIN

nIN

)

nIN

)(RF2)
)(RF1)

1/2

1/2

1/2

1/2

IMPACT OF MISMATCHES IN THE FEEDBACK NETWORKS

As previously mentioned, even if the external feedback networks
(R

) are mismatched, the internal common-mode feedback

F/RG

loop still forces the outputs to remain balanced. The amplitudes
of the signals at each output remain equal and 180° out of phase.
The input-to-output differential mode gain varies proportionately
to the feedback mismatch, but the output balance is unaffected.

The gain from the V

2(β1 − β2)/(β1 + β2)

When β1 = β2, this term goes to zero and there is no differential
output voltage due to the voltage on the V
noise). The extreme case occurs when one loop is open and the
other has 100% feedback; in this case, the gain from V

is either +2 or −2, depending on which loop is closed. The

to V

O, dm

feedback loops are nominally matched to within 1% in most
applications, and the output noise and offsets due to the V
input are negligible. If the loops are intentionally mismatched by a
large amount, it is necessary to include the gain term from V
to V

and account for the extra noise. For example, if β1 = 0.5

O, dm

and β2 = 0.25, the gain from V
is set to 2.5 V, a differential offset voltage is present at the output of
(2.5 V)(0.67) = 1.67 V. The differential output noise contribution is
(7.5 nV/√Hz)(0.67) = 5 nV/√Hz. Both of these results are
undesirable in most applications; therefore, it is best to use
nominally matched feedback factors.

pin to V

OCM

OCM

is equal to

O, dm

to V

O, dm

input (including

OCM

OCM

is 0.67. If the V

input

OCM

OCM

pin

OCM

ADA4939-1/ADA4939-2

Mismatched feedback networks also result in a degradation of
the ability of the circuit to reject input common-mode signals,
much the same as for a four-resistor difference amplifier made
from a conventional op amp.

As a practical summarization of the above issues, resistors of 1%
tolerance produce a worst-case input CMRR of approximately
40 dB, a worst-case differential-mode output offset of 25 mV
due to a 2.5 V V

input, negligible V

OCM

noise contribution,

OCM

and no significant degradation in output balance error.

CALCULATING THE INPUT IMPEDANCE FOR AN APPLICATION CIRCUIT

The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in

Figure 44, the input impedance (R

and −DIN) is simply R

(+D

IN

R

+D

–D

G

IN

IN

V

R

G

Figure 44. ADA4939 Configured for Balanced (Differential) Inputs

IN, dm

ADA4939

+IN

OCM

–IN

= 2 × RG.

R

F

+V

S

R

F

For an unbalanced, single-ended input signal (see Figure 45),
the input impedance is

F

+×

G

⎞
⎟

⎟
⎟
⎟

RR

F

⎠

R

F

+V

S

ADA4939

⎛
⎜

,

SEIN

RIN, SE

⎜

=

⎜
⎜

⎝

R

R

G

1

R

−

()

2

R

G

V

OCM

R

G

) between the inputs

IN, dm

V

OUT, dm

RLV

OUT, dm

07429-051

The input impedance of the circuit is effectively higher than it
would be for a conventional op amp connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the input resistor R

. The common-mode

G

voltage at the amplifier input terminals can be easily determined by
noting that the voltage at the inverting input is equal to the
noninverting output voltage divided down by the voltage divider
formed by R

and RG in the lower loop. This voltage is present at

F

both input terminals due to negative voltage feedback and is in
phase with the input signal, thus reducing the effective voltage
across R

in the upper loop and partially bootstrapping RG.

G

Terminating a Single-Ended Input

This section deals with how to properly terminate a single­ended input to the ADA4939 with a gain of 2, R

= 200 Ω. An example using an input source with a terminated

R

G

= 400 Ω, and

F

output voltage of 1 V p-p and source resistance of 50 Ω illustrates
the four simple steps that must be followed. Note that because
the terminated output voltage of the source is 1 V p-p, the open
circuit output voltage of the source is 2 V p-p. The source shown

Figure 46 indicates this open-circuit voltage.

in

1.

The input impedance must be calculated using the formula

⎛

⎞

⎜

⎟

⎜

⎟

=

⎜

⎟

F

+×

RR

R

200Ω

V

OCM

R

200Ω

⎜

⎟

)(2

F

⎠

⎝

G

G

−

1

R

F

400Ω

+V

ADA4939

–V

R

F

400Ω

200

400

S

S

R

IN

2V p-p

⎛
⎜

⎜

=

⎜
⎜

⎝

V

S

1

R

50Ω

R

G

R

−

G

R

IN

300Ω

S

Figure 46. Calculating Single-Ended Input Impedance R

⎞
⎟

⎟

300

=

⎟
⎟

+×

)400200(2

⎠

RLV

OUT, dm

07429-053

IN

–V

S

R

F

Figure 45. ADA4939 with Unbalanced (Single-Ended) Input

07429-052

Rev. 0 | Page 19 of 24

ADA4939-1/ADA4939-2

2

p

=

2. In order to match the 50 Ω source resistance, the termi-

nation resistor, R
The closest standard 1% value for R

R

50Ω

R

S

50Ω

V

S

2V p-p

Figure 47. Adding Termination Resistor R

, is calculated using RT||300 Ω = 50 Ω.

T

is 60.4 Ω.

T

R

F

IN

60.4Ω

R

G

200Ω

R

T

V

OCM

R

G

200Ω

400Ω

+V

S

ADA4939

–V

S

R

F

400Ω

T

RLV

OUT, dm

3. It can be seen from Figure 47 that the effective RG in the

upper feedback loop is now greater than the R

in the

G

lower loop due to the addition of the termination resistors.
To compensate for the imbalance of the gain resistors,
a correction resistor (R
lower loop. R

is equal to the Thevenin equivalent of the

TS

source resistance R
is equal to R

||RT.

S

R

50Ω

V

S

V p-

Figure 48. Calculating the Thevenin Equivalent

) is added in series with RG in the

TS

and the termination resistance RT and

S

S

R

T

60.4Ω

1.09V p-p

R

TH

27.4Ω

V

TH

7429-055

RTS = RTH = RS||RT = 27.4 Ω. Note that VTH is greater than
1 V p-p, which was obtained with R

= 50 Ω. The modified

T

circuit with the Thevenin equivalent of the terminated source
and R

in the lower feedback loop is shown in Figure 49.

TS

R

F

400Ω

+V

S

R

R

TH

G

27.4Ω

R

27.4Ω

200Ω

V

OCM

R

G

200Ω

TS

ADA4939

–V

S

R

F

400Ω

V

R

OUT, dm

L

V

TH

1.09V p-p

Figure 49. Thevenin Equivalent and Matched Gain Resistors

Figure 49 presents a tractable circuit with matched
feedback loops that can be easily evaluated.

07429-054

07429-056

It is useful to point out two effects that occur with a
terminated input. The first is that the value of R

is increased

G

in both loops, lowering the overall closed-loop gain. The
second is that V

= 50 Ω. These two effects have opposite impacts on

be if R

T

is a little larger than 1 V p-p, as it would

TH

the output voltage, and for large resistor values in the feedback
loops (~1 kΩ), the effects essentially cancel each other out.
For small R

and RG, however, the diminished closed-loop

F

gain is not canceled completely by the increased V
can be seen by evaluating

Figure 49.

The desired differential output in this example is 2 V p-p
because the terminated input signal was 1 V p-p and the
closed-loop gain = 2. The actual differential output voltage,
however, is equal to (1.09 V p-p)(400/227.4) = 1.92 V p-p.
To obtain the desired output voltage of 2 V p-p, a final gain
adjustment can be made by increasing R

without modifying

F

any of the input circuitry. This is discussed in Step 4.

4.

The feedback resistor value is modified as a final gain

adjustment to obtain the desired output voltage.
To make the output voltage V

= 2 V p-p, RF must be

OUT

calculated using the following formula:

R

F

()

()

V

TH

+

G

,

dmOUT

()( )

RRVDesired

V

PP

TS

−

=

09.1

V

4.2272

Ω

PP

−

The closest standard 1 % values to 417 Ω are 412 Ω and
422 Ω. Choosing 422 Ω gives a differential output voltage
of 2.02 V p-p.

R

OCM

R

G

G

Figure 50.

R

F

422Ω

+V

S

ADA4939

–V

S

R

F

422Ω

R

L

The final circuit is shown in

1V p-p

R

S

50Ω

V

S

2V p-p

Figure 50. Terminated Single-Ended-to-Differential System with G = 2

60.4Ω

27.4Ω

200Ω

R

T

V

200Ω

R

TS

. This

TH

Ω=

417

V

OUT, dm

2.02V p-p

07429-057

Rev. 0 | Page 20 of 24

ADA4939-1/ADA4939-2

INPUT COMMON-MODE VOLTAGE RANGE

The ADA4939 input common-mode range is centered between the
two supply rails, in contrast to other ADC drivers with level-shifted
input ranges, such as the

ADA4937. The centered input common-

mode range is best suited to ac-coupled, differential-to-differential
and dual supply applications.

For 5 V single-supply operation, the input common-mode
range at the summing nodes of the amplifier is specified as

1.1 V to 3.9 V and is specified as 0.9 V to 2.4 V with a 3.3 V
supply. To avoid nonlinearities, the voltage swing at the +IN
and −IN terminals must be confined to these ranges.

INPUT AND OUTPUT CAPACITIVE AC COUPLING

Input ac coupling capacitors can be inserted between the source
and R

. This ac coupling blocks the flow of the dc common-

G

mode feedback current and causes the ADA4939 dc input
common-mode voltage to equal the dc output common-mode
voltage. These ac coupling capacitors must be placed in both
loops to keep the feedback factors matched.

Output ac coupling capacitors can be placed in series between
each output and its respective load. See

Figure 54 for an

example that uses input and output capacitive ac coupling.

MINIMUM RG VALUE OF 50 Ω

Due to the wide bandwidth of the ADA4939, the value of RG must
be greater than or equal to 50 Ω to provide sufficient damping in
the amplifier front end. In the terminated case, R
Thevenin resistance of the source and load terminations.

includes the

G

SETTING THE OUTPUT COMMON-MODE VOLTAGE

The V
divider comprising two 20 kΩ resistors at a voltage approximately
equal to the midsupply point, [(+V
internal divider, the V
on the externally applied voltage and its associated source
resistance. Relying on the internal bias results in an output
common-mode voltage that is within about 100 mV of the
expected value.

In cases where more accurate control of the output common­mode level is required, it is recommended that an external
source or resistor divider be used with source resistance less
than 100 Ω. The output common-mode offset listed in the
Specifications section assumes that the V
by a low impedance voltage source.

It is also possible to connect the V
level (CML) output of an ADC. However, care must be taken to
ensure that the output has sufficient drive capability. The input
impedance of the V
ADA4939 devices share one reference output, it is recommended
that a buffer be used.

pin of the ADA4939 is internally biased with a voltage

OCM

) + (−VS)]/2. Because of this

S

pin sources and sinks current, depending

OCM

input is driven

OCM

input to a common-mode

OCM

pin is approximately 10 kΩ. If multiple

OCM

Rev. 0 | Page 21 of 24

ADA4939-1/ADA4939-2

LAYOUT, GROUNDING, AND BYPASSING

As a high speed device, the ADA4939 is sensitive to the
PCB environment in which it operates. Realizing its superior
performance requires attention to the details of high speed
PCB design. This section shows a detailed example of how the
ADA4939-1 was addressed.

The first requirement is a solid ground plane that covers as
much of the board area around the ADA4939-1 as possible.
However, the area near the feedback resistors (R
(R

), and the input summing nodes (Pin 2 and Pin 3) should be

G

cleared of all ground and power planes (see

), gain resistors

F

Figure 51). Clearing
the ground and power planes minimizes any stray capacitance at
these nodes and prevents peaking of the response of the amplifier
at high frequencies.

The thermal resistance, θ

, is specified for the device, including

JA

the exposed pad, soldered to a high thermal conductivity four-layer
circuit board, as described in EIA/JESD 51-7.

The power supply pins should be bypassed as close to the device
as possible and directly to a nearby ground plane. High frequency
ceramic chip capacitors should be used. It is recommended that
two parallel bypass capacitors (1000 pF and 0.1 µF) be used for
each supply. The 1000 pF capacitor should be placed closer to
the device. Further away, low frequency bypassing should be
provided, using 10 µF tantalum capacitors from each supply
to ground.

Signal routing should be short and direct to avoid parasitic
effects. Wherever complementary signals exist, a symmetrical
layout should be provided to maximize balanced performance.
When routing differential signals over a long distance, PCB
traces should be close together, and any differential wiring
should be twisted such that loop area is minimized. Doing this
reduces radiated energy and makes the circuit less susceptible
to interference.

1.30

0.80

Figure 51. Ground and Power Plane Voiding in Vicinity of R

TOP METAL

GROUND PLANE

POWER PL ANE

and R

F

1.30

0.80

7429-058

G

Figure 52. Recommended PCB Thermal Attach Pad Dimensions (Millimeters)

1.30

0.30

PLATED

VIA HOL E

07429-059

BOTTOM METAL

Figure 53. Cross-Section of Four-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters)

07429-060

Rev. 0 | Page 22 of 24

ADA4939-1/ADA4939-2

HIGH PERFORMANCE ADC DRIVING

The ADA4939 is ideally suited for broadband ac-coupled and
differential-to-differential applications on a single supply.

The circuit in
ADA4939 driving an
coupling on the ADA4939 input and output. (The

Figure 54 shows a front-end connection for an

AD9445, 14-bit, 105 MSPS ADC, with ac

AD9445
achieves its optimum performance when driven differentially.)
The ADA4939 eliminates the need for a transformer to drive
the ADC and performs a single-ended-to-differential conversion
and buffering of the driving signal.

The ADA4939 is configured with a single 5 V supply and gain
of 2 for a single-ended input to differential output. The 60.4 Ω
termination resistor, in parallel with the single-ended input
impedance of approximately 300 Ω, provides a 50 Ω termination
for the source. The additional 27.4 Ω (227.4 Ω total) at the
inverting input balances the parallel impedance of the 50 Ω
source and the termination resistor driving the noninverting input.

412Ω

5V

50Ω

SIGNAL
GENERATOR

60.4Ω

200Ω

200Ω

0.1µF0.1µF

27.4Ω

V

OCM

+

ADA4939

412Ω

In this example, the signal generator has a 1 V p-p symmetric,
ground-referenced bipolar output when terminated in 50 Ω.
The V

pin of the ADA4939 is bypassed for noise reduction

OCM

and left floating such that the internal divider sets the output
common-mode voltage nominally at midsupply. Because the
inputs are ac-coupled, no dc common-mode current flows in
the feedback loops, and a nominal dc level of midsupply is
present at the amplifier input terminals. Besides placing the
amplifier inputs at their optimum levels, the ac coupling technique
lightens the load on the amplifier and dissipates less power than
applications with dc-coupled inputs. With an output common­mode voltage of nominally 2.5 V, each ADA4937 output swings
between 2.0 V and 3.0 V, providing a gain of 2 and a 2 V p-p
differential signal to the ADC input.

The output of the amplifier is ac-coupled to the ADC through a
second-order, low-pass filter with a cutoff frequency of 100 MHz.
This reduces the noise bandwidth of the amplifier and isolates
the driver outputs from the ADC inputs.

The

AD9445 is configured for a 2 V p-p full-scale input by

connecting the SENSE pin to AGND, as shown in

3.3V (A)

0.1µF0.1µF

0.1µF

24.3Ω

24.3Ω

30nH

30nH

VIN–

47pF

VIN+

5V (A)

AVDD2

BUFFER T/H

CLOCK/

TIMING

AVDD1

3.3V (D)

DRVDD

ADC

REF

AD9445

14

SENSEAGND

Figure 54.

07429-061

Figure 54. ADA4939 Driving an AD9445 ADC with AC-Coupled Input and Output

Rev. 0 | Page 23 of 24

ADA4939-1/ADA4939-2

R

OUTLINE DIMENSIONS

0.50

0.40

PIN 1

INDICATO

1.00

0.85

0.80

SEATING

PLANE

12° MAX

3.00

BSC SQ

TOP

VIEW

0.30

0.23

0.18

*

COMPLIANT
EXCEPT FOR EXPOSED PAD DIMENSION.

2.75

BSC SQ

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

TO

JEDEC STANDARDS MO-220-VEED-2

0.45

0.50

BSC

1.50 REF

0.60 MAX

12

13

(BOTTOM VIEW)

9

8

Figure 55. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

3 mm × 3 mm Body, Very Thin Quad (CP-16-2)

Dimensions shown in millimeters

4.00

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING
PLANE

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

COMPLIANT TOJEDEC STANDARDS MO-220-VGGD-2

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARITY

0.08

18

13

Figure 56. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad (CP-24-1)

Dimensions shown in millimeters

EXPOSED

PAD

0.60 MAX

19

EXPOSED

PAD

(BOTTOM VIEW)

12

0.30

16

1

4

5

PIN 1
INDICATOR

*

1.45

1.30 SQ

1.15

0.25 MIN

PIN 1
INDICATOR

1

24

2.25

2.10 SQ

1.95

6

7

0.25 MIN

2.50 REF

ORDERING GUIDE

Model Temperature Range Package Description Package Option Ordering Quantity Branding

ADA4939-1YCPZ-R2
ADA4939-1YCPZ-RL
ADA4939-1YCPZ-R7
ADA4939-2YCPZ-R2
ADA4939-2YCPZ-RL
ADA4939-2YCPZ-R7

1

Z = RoHS Compliant Part.

©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07429-0-5/08(0)

1

1

1

1

1

1

−40°C to +105°C 16-Lead LFCSP_VQ CP-16-2 250 H1E

−40°C to +105°C 16-Lead LFCSP_VQ CP-16-2 5,000 H1E

−40°C to +105°C 16-Lead LFCSP_VQ CP-16-2 1,500 H1E

−40°C to +105°C 24-Lead LFCSP_VQ CP-24-1 250

−40°C to +105°C 24-Lead LFCSP_VQ CP-24-1 5,000

−40°C to +105°C 24-Lead LFCSP_VQ CP-24-1 1,500

Rev. 0 | Page 24 of 24