ANALOG DEVICES ADA4899-1 Service Manual

Unity-Gain Stable, Ultralow Distortion,

–

www.BDTIC.com/ADI

1 nV/√Hz Voltage Noise, High Speed Op Amp

FEATURES

Unity-gain stable
Ultralow noise: 1 nV/√Hz, 2.6 pA/√Hz
Ultralow distortion −117 dBc at 1 MHz
High speed

−3 dB bandwidth: 600 MHz (G = +1)

Slew rate: 310 V/μs
Offset voltage: 230 μV maximum
Low input bias current: 100 nA
Wide supply voltage range: 5 V to 12 V
Supply current: 14.7 mA
High performance pinout
Disable mode

APPLICATIONS

Analog-to-digital drivers
Instrumentation
Filters
IF and baseband amplifiers
DAC buffers
Optical electronics

ADA4899-1

CONNECTION DIAGRAMS

ADA4899-1

DISABLE

FEEDBACK

1

2

3

–IN

4

+IN

NC = NO CONNECT

Figure 1. 8-Lead LFCSP_VD (CP-8-2)

ADA4899-1

–V

–IN

+IN

1

2

3

4

S

FEEDBACK

Figure 2. 8-Lead SOIC_N_EP (RD-8-1)

8

+V

7

V

6

NC

5

–V

8

DISABLE

7

+V

6

V

5

–V

OUT

OUT

S

S

S

S

05720-001

05720-002

GENERAL DESCRIPTION

The ADA4899-1 is an ultralow noise (1 nV/√Hz) and distortion
(<−117 dBc @1 MHz) unity-gain stable voltage feedback op
amp, the combination of which makes it ideal for 16-bit and
18-bit systems. The ADA4899-1 features a linear, low noise
input stage and internal compensation that achieves high slew
rates and low noise even at unity gain. The Analog Devices, Inc.
proprietary next-generation XFCB process and innovative
circuit design enable such high performance amplifiers.

The ADA4899-1 drives 100 Ω loads at breakthrough performance
l

evels with only 15 mA of supply current. With the wide supply
voltage range (4.5 V to 12 V), low offset voltage (230 μV maxi­mum), wide bandwidth (600 MHz), and slew rate (310 V/μs),
the ADA4899-1 is designed to work in the most demanding
applications. The ADA4899-1 also features an input bias current
cancellation mode that reduces input bias current by a factor of 60.

The ADA4899-1 is available in a 3 mm × 3 mm LFCSP and an

-lead SOIC package. Both packages feature an exposed metal

8
paddle that improves heat transfer to the ground plane, which is
a significant improvement over traditional plastic packages. The
ADA4899-1 is rated to work over the extended industrial
temperature range, −40°C to +125°C.

40

G = +1

= ±5V

V

S

–50

= 1kΩ

R

L

= 2V p-p

V

OUT

–60

–70

–80

HD3

05720-071

1001010.1

HARMONIC DISTORTION (dBc)

–90

–100

–110

–120

–130

HD2

FREQUENCY (MHz )

Figure 3. Harmonic Distortion vs. Frequency

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005–2007 Analog Devices, Inc. All rights reserved.

ADA4899-1

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Connection Diagrams...................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications with ±5 V Supply..................................................... 3

Specifications with +5 V Supply..................................................... 4

Absolute Maximum Ratings............................................................ 5

Maximum Power Dissipation ..................................................... 5

ESD Caution.................................................................................. 5

Typical Performance Characteristics............................................. 6

Test Circ uit s .....................................................................................12

Theory of Operation ...................................................................... 13

REVISION HISTORY

6/07—Rev. A to Rev. B

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Changes to Figure 21 and Figure 22............................................... 8

Changes to Packaging Innovation Section.................................. 13

Changes to Figure 49 and Figure 50............................................. 15

Updated Outline Dimensions....................................................... 18

4/06—Rev. 0 to Rev. A

hanges to Figure 2.......................................................................... 1

C

10/05—Revision 0: Initial Version

Packaging Innovation ................................................................ 13

DISABLE

Applications..................................................................................... 14

Unity Gain Operation................................................................ 14

Recommended Values for Various Gains................................ 14

Noise ............................................................................................ 15

ADC Driver................................................................................. 15

DISABLE

ADA4899-1 Mux........................................................................ 16

Circuit Considerations .............................................................. 16

Outline Dimensions .......................................................................18

Ordering Guide .......................................................................... 18

Pin ..............................................................................13

Pin Operation ........................................................... 16

Rev. B | Page 2 of 20

ADA4899-1

www.BDTIC.com/ADI

SPECIFICATIONS WITH ±5 V SUPPLY

TA = 25°C, G = +1, RL = 1 kΩ to ground, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth V

V

Bandwidth for 0.1 dB Flatness G = +2, V
Slew Rate V
Settling Time to 0.1% V

NOISE/DISTORTION PERFORMANCE

Harmonic Distortion, HD2/HD3 (dBc) fC = 500 kHz, V

f

Input Voltage Noise f = 100 kHz 1.0 nV/√Hz
Input Current Noise

DC PERFORMANCE

Input Offset Voltage 35 230 μV
Input Offset Voltage Drift 5 μV/°C
Input Bias Current

Input Bias Current Drift 3 nA/°C
Input Bias Offset Current 0.05 0.7 μA
Open-Loop Gain 82 85 dB

INPUT CHARACTERISTICS

Input Resistance Differential mode 4 kΩ
Common mode 7.3 MΩ
Input Capacitance 4.4 pF
Input Common-Mode Voltage Range −3.7 to +3.7 V
Common-Mode Rejection Ratio 98 130 dB

DISABLE PIN

DISABLE Input Threshold Voltage
Turn-Off Time

Turn-On Time

Input Bias Current

OUTPUT CHARACTERISTICS

Output Overdrive Recovery Time (Rise/Fall) VIN = −2.5 V to +2.5 V, G = +2 30/50 ns
Output Voltage Swing RL = 1 kΩ −3.65 to +3.65 −3.7 to +3.7 V
R
Short-Circuit Current Sinking/sourcing 160/200 mA
Off Isolation

POWER SUPPLY

Operating Range 4.5 12 V
Quiescent Current 14.7 16.2 mA
Quiescent Current (Disabled)

Positive Power Supply Rejection Ratio +VS = 4 V to 6 V (input referred) 84 90 dB
Negative Power Supply Rejection Ratio −VS = −6 V to −4 V (input referred) 87 93 dB

= 25 mV p-p 600 MHz

OUT

= 2 V p-p 80 MHz

OUT

= 2 V p-p 35 MHz

OUT

= 5 V step 310 V/μs

OUT

= 2 V step 50 ns

OUT

= 2 V p-p −123/−123 dBc

OUT

= 10 MHz, V

C

f = 100 kHz, DISABLE
f = 100 kHz, DISABLE

DISABLE pin floating
DISABLE

pin = +V

= 2 V p-p −80/−86 dBc

OUT

pin floating
pin = +V

S

2.6 pA/√Hz

5.2 pA/√Hz

−6 −12 μA

S

−0.1 −1 μA

Output disabled <2.4 V
50% of DISABLE

VIN = 0.5 V

50% of DISABLE

voltage to 10% of V

voltage to 90% of V

100 ns

,

OUT

40 ns

,

OUT

VIN = 0.5 V
DISABLE
DISABLE

f = 1 MHz, DISABLE

DISABLE

= +VS (enabled)
= −VS (disabled)

= 100 Ω −3.13 to +3.15 −3.25 to +3.25 V

L

= −V

S

= −V

S

17 21 μA

−35 −44 μA

−48 dB

1.8 2.1 mA

Rev. B | Page 3 of 20

ADA4899-1

www.BDTIC.com/ADI

SPECIFICATIONS WITH +5 V SUPPLY

VS = 5 V @ TA = 25°C, G = +1, RL = 1 kΩ to midsupply, unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth V

V

Bandwidth for 0.1 dB Flatness G = +2, V
Slew Rate V
Settling Time to 0.1% V

NOISE/DISTORTION PERFORMANCE

Harmonic Distortion, HD2/HD3 (dBc) fC = 500 kHz, V

f

Input Voltage Noise f = 100 kHz 1.0 nV/√Hz
Input Current Noise

DC PERFORMANCE

Input Offset Voltage 5 210 μV
Input Offset Voltage Drift 5 μV/°C
Input Bias Current

Input Bias Offset Current 0.05 μA
Input Bias Offset Current Drift 2.5 nA/°C
Open-Loop Gain 76 80 dB

INPUT CHARACTERISTICS

Input Resistance Differential mode 4 kΩ
Common mode 7.7 MΩ
Input Capacitance 4.4 pF
Input Common-Mode Voltage Range 1.3 to 3.7 V
Common-Mode Rejection Ratio 90 114 dB

DISABLE PIN

DISABLE Input Threshold Voltage
Turn-Off Time

Turn-On Time

Input Bias Current

OUTPUT CHARACTERISTICS

Overdrive Recovery Time (Rise/Fall) VIN = 0 V to 2.5 V, G = +2 50/70 ns
Output Voltage Swing RL = 1 kΩ 1.25 to 3.75 1.2 to 3.8 V
R
Short-Circuit Current Sinking/sourcing 60/80 mA
Off Isolation

POWER SUPPLY

Operating Range 4.5 12 V
Quiescent Current 14.3 16 mA
Quiescent Current (Disabled)

Positive Power Supply Rejection Ratio +VS = 4.5 V to 5.5 V, −VS = 0 V (input referred) 84 90 dB
Negative Power Supply Rejection Ratio +VS = 5 V, −VS = −0.5 V to +0.5 V (input referred) 86 90 dB

= 25 mV p-p 535 MHz

OUT

= 2 V p-p 60 MHz

OUT

= 2 V p-p 25 MHz

OUT

= 2 V step 185 V/μs

OUT

= 2 V step 50 ns

OUT

= 1 V p-p −100/−113 dBc

OUT

= 10 MHz, V

C

f = 100 kHz, DISABLE
f = 100 kHz, DISABLE

DISABLE
DISABLE

pin floating
pin = +V

= 1 V p-p −89/−100 dBc

OUT

pin floating
pin = +V

S

2.6 pA/√Hz

5.2 pA/√Hz

−6 −12 μA

S

−0.2 −1.5 μA

Output disabled <2.4 V
50% of DISABLE

voltage to 10% of V

OUT

,

100 ns

VIN = 0.5 V

50% of DISABLE

voltage to 90% of V

OUT

,

60 ns

VIN = 0.5 V
DISABLE
DISABLE

f = 1 MHz, DISABLE

DISABLE

= +VS (enabled)
= −VS (disabled)

= 100 Ω 1.4 to 3.6 1.35 to 3.65 V

L

= −V

S

= −V

S

16 18 μA

−33 −42 μA

−48 dB

1.5 1.7 mA

Rev. B | Page 4 of 20

ADA4899-1

(

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage 12.6 V
Power Dissipation See Figure 4
Differential Input Voltage ±1.2 V
Differential Input Current ±10 mA
Storage Temperature Range –65°C to +150°C
Operating Temperature Range –40°C to +125°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the ADA4899-1
package is limited by the associated rise in junction temperature
(T

) on the die. The plastic encapsulating the die locally reaches

J

the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4899-1.
Exceeding a junction temperature of 150°C for an extended
period can result in changes in silicon devices, potentially
causing failure.

The still-air thermal properties of the package and PCB (θ
the ambient temperature (T
the package (P

) determine the junction temperature of the die.

D

), and the total power dissipated in

A

The junction temperature is calculated as

T

= TA + (PD × θJA)

J

The power dissipated in the package (P

) is the sum of the

D

quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
quiescent current (I
midsupply, the total drive power is V

). Assuming the load (RL) is referenced to

S

/2 × I

S

dissipated in the package and some in the load (V

) times the

S

, some of which is

OUT

OUT

× I

OUT

),

JA

).

The difference between the total drive power and the load

ower is the drive power dissipated in the package.

p

P

= Quiescent Power + (Total Drive Power – Load Power)

D

⎛

()

D

⎜

IVP

SS

⎜
⎝

V

2

⎞

V

OUTS

⎟

×+×=

⎟

R

L

⎠

RMS output voltages should be considered. If R
V

–, as in single-supply operation, the total drive power is VS ×

S

. If the rms signal levels are indeterminate, consider the

I

OUT

worst case, when V

()

D

= VS/4 for RL to midsupply

OUT

2

)

4

/V

S

+×=

IVP

SS

R

L

In single-supply operation with R
is V

= VS/2.

OUT

Airflow increases heat dissipation, effectively reducing θ

2

V

OUT

–

referenced to VS–, worst case

L

R

L

is referenced to

L

. In

JA

addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θ

. Soldering the exposed paddle to the ground

JA

plane significantly reduces the overall thermal resistance of the
package.

Figure 4 shows the maximum safe power dissipation in the

ackage vs. the ambient temperature for the exposed paddle

p
(EPAD) 8-lead SOIC (70°C/W) and 8-lead LFCSP (70°C/W)
packages on a JEDEC standard 4-layer board. θ

values are

JA

approximations.

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

MAXIMUM POWER DISSIPATION (W)

0.0

Figure 4. Maximum Power Dissipation vs. Ambient Temperature

LFCSP AND SOIC

120–40–200 20406080100

AMBIENT TEMPERATURE (°C)

ESD CAUTION

05720-003

Rev. B | Page 5 of 20

ADA4899-1

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

3

0

VS = ±5V
R

= 1kΩ

L

V

= 25mV p-p

OUT

G = +1

G = –1

3

0

G = +1
R

= 100Ω

L

V

OUT

= 25mV p-p

–3

–6

–9

NORMALIZ ED CLOSED-L OOP GAI N (dB)

–12

G = +10

FREQUENCY (MHz)

Figure 5. Small Signal Frequency Response for Various Gains, R

G = +2

G = +5

= 1 kΩ

L

3

VS = ±5V
R

= 100Ω

L

V

= 25mV p-p

OUT

0

–3

–6

–9

NORMALIZ ED CLOSED- LOOP G AIN (dB)

–12

G = +10

FREQUENCY (MHz)

Figure 6. Small Signal Frequency Response for Various Gains, R

G = +2

G = +5

G = +1

G = –1

= 100 Ω

L

3

0

G = +1
V

= ±5V

S

R

= 1kΩ

–3

L

V

= 25mV p-p

OUT

–6

CLOSED-LOOP GAIN (dB)

–9

–12

FREQUENCY (MHz)

T = +125°C

T = –40°C

Figure 7. Small Signal Frequency Response for Various Temperatures

–3

–6

CLOSED-LOOP GAIN (dB)

–9

05720-004

10001 10010

–12

FREQUENCY (MHz)

V

= +5V

S

VS = ±5V

05720-007

100010 100

Figure 8. Small Signal Frequency Response for Various Supply Voltages

6

G = +1
R

= 1kΩ

L

V

= 25mV p-p

OUT

3

0

–3

–6

CLOSED-LOOP GAIN (dB)

–9

05720-005

10001 10010

–12

CL = 15pF
R

= 10Ω

SNUB

C

= 2pF

L

FREQUENCY (MHz)

C

= 0pF

L

C

L

C

= 15pF

= 5pF

L

05720-032

100010010

Figure 9. Small Signal Frequency Response for Capacitive Loads

5.0
VS = ±5V

V

= 25mV p-p

OUT

4.5

G = +1

4.0

R

= 1kΩ

L

3.5

3.0

2.5

2.0

PEAKING (d B)

1.5

1.0

0.5

05720-006

100010 100

0

G = +1
R

= 100Ω

L

G = +2
R

= 1kΩ

L

CAPACITIVE L OAD (pF)

G = +1
R

= 1kΩ

L

R

SNUB

= 10Ω

05720-031

454035302520151050

Figure 10. Small Signal Frequency Response Peaking vs.

citive Load for Various Gains

Capa

Rev. B | Page 6 of 20

ADA4899-1

www.BDTIC.com/ADI

0.1

0

CLOSED-LOOP GAIN (dB)

–0.1

–0.2

–0.3

–0.4

–0.5

G = +2
V

= ±5V

S

R

= 150Ω

L

V

= 100mV p-p

OUT

V

= 2V p-p

OUT

FREQUENCY (MHz )

Figure 11. 0.1 dB Flatness for Various Output Voltages

3

G = +1
R

= 1kΩ

L

V

= 2V p-p

OUT

0

VS = ±5V

–3

V

= +5V

S

–6

CLOSED-LOOP GAIN (dB)

–9

05720-010

100110

3

G = +1
V

= ±5V

S

R

= 100Ω

L

0

V

= 1V p-p

V

= 4V p-p

–3

–6

CLOSED-LOOP GAIN (dB)

–9

–12

OUT

V

OUT

= 7V p-p

FREQUENCY (MHz)

OUT

05720-009

10001 10 100

Figure 14. Large Signal Frequency Response for Various Output Voltages

100

80

60

40

20

OPEN-LOOP GAIN (dB)

0

VS = ±5V
R

= 100Ω

L

180

150

120

90

60

30

OPEN-LOOP PHASE (Degrees)

–12

FREQUENCY (MHz)

05720-011

100010 100

Figure 12. Large Signal Frequency Response for Various Supply Voltages

10

1

VOLTAGE NOISE (nV/ Hz)

0.1

FREQUENCY (Hz)

05720-027

100M10M1M100k10k1k10010

Figure 13. Voltage Noise vs. Frequency

05720-030

–20

Figure 15. Open-Loop Gain

FREQUENCY (MHz)

/Phase vs. Frequency

0

10001001010.10.010.001

1k

100

10

CURRENT NOISE (pA/ Hz)

DISABLE = NC

1

DISABLE = 5V

FREQUENCY (Hz)

05720-028

100M10M1M100k10k1k10010

Figure 16. Input Current Noise vs. Frequency

Rev. B | Page 7 of 20

ADA4899-1

–

–

–

–

–

–

www.BDTIC.com/ADI

HARMONIC DISTORTION (dBc)

40

G = +1

= ±5V

V

S

–50

= 1kΩ

R

L

= 2V p-p

V

OUT

–60

–70

–80

–90

–100

–110

–120

–130

HD2

FREQUENCY (MHz )

Figure 17. Harmonic Distortion vs. Frequency

HD3

05720-021

1001010.1

HARMONIC DISTORTION (dBc)

40

G = +5

= 1kΩ

R

L

–50

= ±5V

V

S

= 2V p-p

V

OUT

–60

–70

–80

–90

–100

–110

–120

HD2

HD3

FREQUENCY (MHz)

Figure 20. Harmonic Distortion vs. Frequency

05720-024

1001010.1

40

G = +1

= 1kΩ

R

L

–50

f = 5MHz

–60

–70

HARMONIC DISTORTION (dBc)

–80

–90

–100

–110

–120

OUTPUT AMPLITUDE (V p -p)

HD2

HD3

Figure 18. Harmonic Distortion vs. Output Amplitude

40

G = +1

= 1kΩ

R

L

–50

= 5V

V

S

HARMONIC DISTORTION (dBc)

–60

–70

–80

–90

–100

–110

–120

V

= 2V p-p

OUT

V

FREQUENCY (MHz )

OUT

= 1V p-p

HD3

HD2

HD2

Figure 19. Harmonic Distortion vs. Frequency

HD3

40

G = +5

= ±5V

V

S

–50

= 100Ω

R

L

= 2V p-p

V

OUT

–60

–70

HD2
SOIC

–80

–V

ON PIN 5

S

–90

–100

HARMONIC DISTORTION (dBc)

–110

05720-022

87654321

–120

HD2
SOIC
–V

ON PIN 4

S

HD2
LFCSP

HD3
LFCSP

FREQUENCY (MHz )

HD3
SOIC
–V

ON PIN 4 OR PIN 5

S

05720-043

1001010.1

Figure 21. Harmonic Distortion vs. Frequency for

V

arious Pinouts and Packages

40

G = +1

= ±5V

V

S

–50

= 100Ω

R

L

= 2V p-p

V

OUT

–60

–70

–80

–90

–100

HARMONIC DISTORTION (dBc)

–110

05720-023

1001010.1

–120

HD2
LFCSP

HD2
SOIC

FREQUENCY (MHz )

HD3
LFCSP OR SOIC

05720-044

1001010.1

Figure 22. Harmonic Distortion vs. Frequency for Both Packages

Rev. B | Page 8 of 20

ADA4899-1

www.BDTIC.com/ADI

0.10

–0.02

–0.04

OUTPUT VOL TAGE (V)

–0.06

–0.08

–0.10

0.08

0.06

0.04

0.02

0

G = +1

= ±5V

V

S

= 1kΩ

R

L

CL = 15pF

C

L

TIME (ns)

Figure 23. Small Signal Transient Response for

V

arious Capacitive Loads (Rising Edge)

0.08
RL = 1kΩ

= ±5V

V

S

0.06

0.04

0.02

G = +2

G = +5

G = +10

0

C

= 0pF

= 5pF

L

C
R

L
SNUB

= 15pF

= 10Ω

05720-041

151050

0.10
G = +1

= ±5V

V

S

0.08

= 1kΩ

R

L

0.06

0.04

0.02

0

–0.02

–0.04

OUTPUT VOL TAGE (V)

–0.06

–0.08

–0.10

C

L

TIME (ns)

Figure 26. Small Signal Transient Response for

V

arious Capacitive Loads (Falling Edge)

1.5

1.0

0.5

0

RL = 1kΩ

= ±5V

V

S

G = +2

G = +10

G = +5

= 0pF

CL = 15pF

= 5pF

C

L

C
R

L
SNUB

= 15pF

= 10Ω

05720-042

151050

–0.02

OUTPUT VOL TAGE (V)

–0.04

–0.06

–0.08

TIME (ns)

Figure 24. Small Signal Transient Response for Various Gains

1.5
G = +1

= 100Ω

R

L

1.0

= ±5V

V

S

0.5

= +5V

V

S

0

–0.5

OUTPUT VOL TAGE (V)

–1.0

–1.5

TIME (ns)

Figure 25. Large Signal Transient Response for

rious Supply Voltages, R

Va

= 100 Ω

L

–0.5

OUTPUT VOL TAGE (V)

–1.0

05720-019

1009080706050403020100

–1.5

TIME (ns)

05720-013

1009080706050403020100

Figure 27. Large Signal Transient Response for Various Gains

1.5
G = +1

= 1kΩ

R

L

1.0

= ±5V

V

S

0.5

V

= +5V

0

–0.5

OUTPUT VOL TAGE (V)

–1.0

05720-017

1009080706050403020100

–1.5

S

TIME (ns)

05720-018

1009080706050403020100

Figure 28. Large Signal Transient Response for

rious Supply Voltages, R

Va

= 1 kΩ

L

Rev. B | Page 9 of 20

ADA4899-1

–

www.BDTIC.com/ADI

= ±5V
= 1kΩ

0.3

0.2

0.1

0

–0.1

OUTPUT SETTLING (%)

–0.2

05720-025

–0.3

1500 25 50 75 100 125

OUTPUT IMPEDANCE (Ω)

0.01

0.001

10

1

0.1

G = +1

= ±5V

V

S

DISABLE = NC

Figure 32. Output Imped

FREQUENCY (MHz)

ance vs. Frequency

05720-015

10001001010.10.010.001

0.3

0.2

0.1

100k

10k

G = +1

= ±5V

V

S

DISABLE = –5V

VOLTAGE (V)

1.5

1.0

0.5

–0.5

–1.0

–1.5

1.5

1.0

0.5

INPUT

0

OUTPUT

TIME (ns)

ERROR

G = +1
V

S

R

L

Figure 29. Settling Time, G = +1

INPUT

= ±5V
= 1kΩ

0

–0.1

OUTPUT SETTLING (%)

–0.2

05720-026

–0.3

1500 25 50 75 100 125

1k

OUTPUT IMPEDANCE (Ω)

100

10

Figure 33. Output Impedance v

FREQUENCY (MHz)

s. Frequency (Disabled)

05720-014

10001001010.1

20

G = +1

= 1kΩ

R

–30

L

= 1kΩ

R

F

–40

–50

–60

–70

–80

–90

–100

VS = +5V

–110

COMMON-MO DE REJECTIO N (dB)

–120

V

–130

05720-016

10001001010.1

–140

= ±5V

S

FREQUENCY (Hz)

05720-020

1G100M10M1M100k10k1k10010

0

VOLTAGE (V)

–0.5

–1.0

–1.5

OUTPUT

TIME (ns)

ERROR

G = +5
V

S

R

L

Figure 30. Settling Time, G = +5

100k

INPUT IMPEDANCE (Ω)

10k

1k

100

10

FREQUENCY (MHz)

G = +1

= ±5V

V

S

DISABLE = NC

Figure 31. Input Impedance vs. Frequency

Rev. B | Page 10 of 20

Figure 34. Common-Mode Rejection vs. Frequency

ADA4899-1

–

www.BDTIC.com/ADI

–10

–20

–30

–40

–50

–60

–70

SUPPLY REJE CTION (d B)

–80

–90

–100

22

–28

–34

0

VS = ±5V
DISABLE = –5V

–PSR

+PSR

FREQUENCY (MHz)

Figure 35. Power Supply Rejection

500

400

300

COUNT

200

100

05720-029

10001001010.10.010.001

0

VOLTAGE OF FSET (µV)

Figure 38. Input Offset Voltage Distribution (V

500

400

N: 4651
MEAN: –4.92µV
SD: 29.22µV

= 5V

V

S

= 5 V)

S

N: 4655
MEAN: –34.62µ V
SD: 28.94µV

= ±5V

V

S

05720-034

200–200 –150 –100 –50 0 50 100 150

ISOLAT ION (dB)

COUNT

–40

–46

–52

–58

–64

–70

700

600

500

400

300

200

100

Figure 36. Off Isolation vs. Fr

0

FREQUENCY (MHz)

equency

INPUT BIAS CURRENT (µA)

N: 4653
MEAN: –0.083µA
SD: 0.13µA

= ±5V

V

S

0.9–0.9 –0.6 –0. 3 0 0.3 0.6

05720-012

10000.1 1 10 100

05720-033

300

COUNT

200

100

0

VOLTAGE OFFSET (µV)

Figure 39. Input Offset Voltage Distribution (V

= ±5 V)

S

05720-035

200–200 –150 –100 –50 0 50 100 150

Figure 37. Input Bias Current Distribution

Rev. B | Page 11 of 20

ADA4899-1

V

V

V

V

T

V

V

V

www.BDTIC.com/ADI

TEST CIRCUITS

+

S

10µF

R

G

+

S

R

10µF

F

24.9Ω

IN

10µF

49.9Ω

0.1µF

–V

S

Figure 40. Typical Noninverting Load

+

S

10µF

AC

49.9Ω

0.1µF

–V

S

1kΩ10Ω

10Ω

Figure 41. Positive Power Supply Rejection

+

S

10µF

1kΩ

1kΩ

V

IN

53.6Ω

1kΩ

1kΩ

10µF

0.1µF

R

L

Configuration

V

R

L

0.1µF

0.1µF

V

OUT

OUT

0.1µF

R

IN

R

10µF

T

–V

05720-045

S

SNUB

0.1µF

V

OU

R

C

L

L

05720-040

Figure 43. Typical Capacitive Load Configuration

+

S

10µF

1kΩ10Ω

10Ω

05720-038

AC

0.1µF

V

OUT

R

L

49.9Ω

–V

S

05720-039

Figure 44. Negative Power Supply Rejection

V

OUT

R

L

–V

S

05720-036

Figure 42. Common-Mode Rejection

Rev. B | Page 12 of 20

ADA4899-1

www.BDTIC.com/ADI

THEORY OF OPERATION

The ADA4899-1 is a voltage feedback op amp that combines
unity-gain stability with a 1 nV/√Hz input noise. It employs a
highly linear input stage that can maintain greater than −80 dBc
(@ 2 V p-p) distortion out to 10 MHz while in a unity-gain
configuration. This rare combination of low gain stability,
input-referred noise, and extremely low distortion is the result
of Analog Devices proprietary op amp architecture and high
speed complementary bipolar processing technology.

The simplified ADA4899-1 topology, shown in Figure 45, is a
sin

gle gain stage with a unity-gain output buffer. It has over
80 dB of open-loop gain and maintains precision specifications
such as CMRR, PSRR, and offset to levels that are normally
associated with topologies having two or more gain stages.

R1 R

Figure 45. ADA4899-1 Topology

A pair of internally connected diodes limits the differential
voltage between the noninverting input and the inverting input
of the ADA4899-1. Each set of diodes has two series diodes
connected in antiparallel, which limits the differential voltage
between the inputs to approximately ±1.2 V. All of the ADA4899-1
pins are ESD protected with voltage-limiting diodes connected
between both rails. The protection diodes can handle 10 mA.
Currents should be limited through these diodes to 10 mA or less
by using a series limiting resistor.

BUFFERgm

C

C

V

OUT

L

05720-060

PACKAGING INNOVATION

The ADA4899-1 is available in both a SOIC and an LFCSP, each
of which has a thermal pad that allows the device to run cooler,
thereby increasing reliability. To help avoid routing around the
pad when laying out the board, both packages have a dedicated
feedback pin on the opposite side of the package for ease in
connecting the feedback network to the inverting input. The
secondary output pin also isolates the interaction of any
capacitive load on the output and the self-inductance of the
package and bond wire from the feedback loop. When using the
dedicated feedback pin, inductance in the primary output helps to
isolate capacitive loads from the output impedance of the
amplifier.

Both the SOIC and LFCSP have modified pinouts to improve

avy load second harmonic distortion performance. The intent

he
of both is to isolate the negative supply pin from the noninverting
input. The LFCSP accomplishes this by rotating the standard
8-lead package pinout counterclockwise by one pin, which puts
the supply and output pins on the right side of the package and
the input pins on the left side of the package. The SOIC is
slightly different with the intent of both isolating the inputs
from the supply pins and giving the user the option of using the
ADA4899-1 in a standard SOIC board layout with little or no
modification. Taking the unused Pin 5 and making it a second
negative supply pin allows for both an input isolated layout and
a traditional layout to be supported.

DISABLE PIN

A three-state input pin is provided on the ADA4899-1 for a
high impedance disable and an optional input bias current
cancellation circuit. The high impedance output allows several
ADA4899-1s to drive the same ADC or output line time
interleaved. Pulling the
impedance state (see Tab le 7 for threshold levels). When the
DISABLE

normally. With the
positive supply, an optional input bias current cancellation
circuit is turned on, which lowers the input bias current to less
than 200 nA. In this mode, the user can drive the ADA4899-1
from a high dc source impedance and still maintain minimal
output-referred offset without having to use impedance
matching techniques. In addition, the ADA4899-1 can be
ac-coupled while setting the bias point on the input with a high
dc impedance network. The input bias current cancellation
circuit doubles the input-referred current noise, but this effect is
minimal as long as the wideband impedances are kept low (see
Figure 16).

pin is left floating (open), the ADA4899-1 operates

DISABLE

DISABLE

pin low activates the high

pin pulled within 0.7 V of the

Rev. B | Page 13 of 20

ADA4899-1

V

V

www.BDTIC.com/ADI

APPLICATIONS

UNITY-GAIN OPERATION

The ADA4899-1 schematic for unity-gain configuration is
nearly a textbook example (see Figure 46). The only exception is

he small 24.9 Ω series resistor at the noninverting input. The

t
series resistor is only required in unity-gain configurations;
higher gains negate the need for the resistor. In
s

een that the overall noise contribution of the amplifier and the

24.9 Ω resistor is equivalent to the noise of a single 87 Ω resistor.
Figure 47 shows the small signal frequency response for the

uni

ty-gain amplifier shown in Figure 46.

+

S

0.1µF

24.9Ω

IN

0.1µF

–V

S

Figure 46. Unity-Gain Schematic

Table 4, it can be

V

OUT

05720-037

3

G = +1
R

= 100Ω

L

0

–3

–6

CLOSED-LOOP GAIN (dB)

–9

–12

Figure 47. Small Signal Frequency Response for Various Output Voltages

200mV p-p

100mV p-p

FREQUE NCY (MHz)

50mV p-p

25mV p-p

05720-063

10000110010 1000

RECOMMENDED VALUES FOR VARIOUS GAINS

Table 4 provides a handy reference for determining various
gains and associated performance. For noise gains greater than
one, the Series Resistor R
are kept low to minimize their contribution to the overall noise
performance of the amplifier.

is not required. Resistors RF and RG

S

Table 4. Conditions: VS = ±5 V, TA = 25°C, RL = 1 kΩ

Gain RF (Ω) RG (Ω) RS (Ω)

−3 dB SS BW (MHz)
(25 mV

p-p)

Slew Rate (V/μs)
(2 V Step)

ADA4899-1 Voltage
Noise (nV/√Hz)

Total Voltage
Noise (nV/√Hz)

+1 0 NA 24.9 605 274 1 1.2

−1 100 100 0 294 265 2 2.7
[phone] 2.7
+5 200 49.9 0 77 227 5 6.5
+10 453 49.9 0 37 161 10 13.3

Rev. B | Page 14 of 20

ADA4899-1

V

A

G

A

G

A

www.BDTIC.com/ADI

NOISE

To analyze the noise performance of an amplifier circuit, first
identify the noise sources, then determine if the source has a
significant contribution to the overall noise performance of the
amplifier. To simplify the noise calculations, noise spectral
densities were used, rather than actual voltages to leave
bandwidth out of the expressions (noise spectral density, which
is generally expressed in nV/
1 Hz bandwidth).

The noise model shown in Figure 48 has six individual noise

ources: the Johnson noise of the three resistors, the op amp

s
voltage noise, and the current noise in each input of the
amplifier. Each noise source has its own contribution to the
noise at the output. Noise is generally specified referred to input
(RTI), but it is often simpler to calculate the noise referred to
the output (RTO) and then divide by the noise gain to obtain
the RTI noise.

V

N, R1

B

4kTR1

V

N, R3

A

4kTR3

RTI NOISE =

RTO NOISE = NG × RTI NOISE

I

R1

R3

I

Figure 48. Op Amp Noise Analysis Model

All resistors have a Johnson noise that is calculated by

)(4kBTR

where:

oltzmann’s Constant (1.38 × 10

k is B
B is the bandwidth in Hz.
T is the absolute temperature in Kelvin.
R is the resistance in ohms.

A simple relationship that is easy to remember is that a 50 Ω

sistor generates a Johnson noise of 1 nV

re
In applications where noise sensitivity is critical, care must be

t

aken not to introduce other significant noise sources to the
amplifier. Each resistor is a noise source. Attention to the
following areas is critical to maintain low noise performance:
design, layout, and component selection. A summary of noise
performance for the amplifier and associated resistors can be

Table 4.

seen in

√Hz, is equivalent to the noise in a

N, R2

R2

GAIN FROM

B TO OUTPUT

R2

R1 + R2

2

+ 4kTR2

J/K).

A TO OUTPUT

N–

V

N+

2

V

N

2

+

I

N+

4kTR2

N

+ 4kTR3 + 4kTR1

R1 × R2

2

R32 + I

N–

R1 + R2 R1 + R2

–23

√Hz at 25°C.

GAIN FROM

NOISE GAIN =

NG = 1 +
R1

V

OUT

= –
R1

2

R1

=

R2

R2

2

5720-070

ADC DRIVER

The ultralow noise and distortion performance of the
ADA4899-1 makes it an excellent candidate for driving 16-bit
ADCs. The schematic for a single-ended input buffer using the
ADA4899-1 and the
in Figure 49. Table 5 shows the performance data of the
AD

A4899-1 and the AD7677.

NALO

+

INPUT

NALO

–

INPUT

Table 5. ADA4899-1, Single-Ended Driver for AD7677
16-Bit, 1 MSPS, f

Parameter Measurement (dB)

Second Harmonic Distortion −116.5
Third Harmonic Distortion −111.9
THD
SFDR
SNR +92.6

The ADA4899-1 configured as a single-ended-to-differential
driver for the AD7677 is shown in Figure 50. Tab le 6 shows the

ssociated performance.

a

+2.5V REF

NALOG

INPUT

Figure 50. Single-Ended-to-Differential ADC Driver

Table 6. ADA4899-1, Single Ended-to-Differential Driver for
AD7677 16-Bit, 1 MSPS, f

Parameter Measurement (dB)

THD −92.7
SFDR +91.8
SNR +90.6

AD7677, a 1 MSPS, 16-bit ADC, is shown

+5V

25Ω

ADA4899-1

–5V

+5V

25Ω

ADA4899-1

–5V

15Ω

2.7nF

15Ω

2.7nF

Figure 49. Single-Ended Input ADC Driver

= 50 kHz

C

−108.6
+101.4

+5V

590Ω

590Ω

+2.5V

REF

ADA4899-1

–5V

590Ω

590Ω

590Ω 15Ω

590Ω

+5V

–5V

= 500 kHz

C

15Ω

ADA4899-1

IN+

IN–

2.7nF

2.7nF

AD7677

IN+

IN–

AD7677

05720-062

05720-061

Rev. B | Page 15 of 20

ADA4899-1

0

V

www.BDTIC.com/ADI

DISABLE PIN OPERATION

The ADA4899-1

DISABLE

enable, disable, and reduction of the input bias current. When
the

DISABLE

pin is brought to within 0.7 V of the positive

supply, the input bias current circuit is enabled, which reduces
the input bias current by a factor of 100. In this state, the input
current noise doubles from 2.6 pA/
outlines the

DISABLE

pin performs three functions:

√Hz to 5.2 pA/√Hz. Tabl e 7

pin operation.

An AD8137 differential amplifier is used as a level translator
that converts the TTL input to a complementary ±3 V output to
drive the

DISABLE

pins of the ADA4899-1s. The transient

response for the 2:1 mux is shown in Figure 52.

1

Table 7.

DISABLE

Pin Truth Table

Supply Voltage ±5 V +5 V

Disable −5 V to +2.4 V 0 V to 2.4 V
Enable Open Open
Low Input Bias Current 4.3 V to 5 V 4.3 V to 5 V

ADA4899-1 MUX

With a true output disable, the ADA4899-1 can be used in
multiplexer applications. The outputs of two ADA4899-1s are
wired together to form a 2:1 mux. Figure 51 shows the 2:1 mux

chematic.

s

+5

0.1µF

2

CH1 = 500mV/DIV
CH2 = 5V/DIV
200ns/DIV

Figure 52. ADA4899-1 2:1 Mux Transient Response

CIRCUIT CONSIDERATIONS

Careful and deliberate attention to detail when laying out the
ADA4899-1 board yields optimal performance. Power supply
bypassing, parasitic capacitance, and component selection all
contribute to the overall performance of the amplifier.

PCB Layout

1MHz

V TO 5V

1V p-p
15MHz

50Ω

ADA4899-1

0.1µF

2kΩ

+5V

0.1µF2.2µF

+

1kΩ50Ω

AD8137

–5V

DISABLE

V

OUT

R
50Ω

50Ω

T

Because the ADA4899-1 can operate up to 600 MHz, it is
essential that RF board layout techniques be employed. All
ground and power planes under the pins of the ADA4899-1
should be cleared of copper to prevent the formation of parasitic
capacitance between the input pins to ground and the output
pins to ground. A single mounting pad on a SOIC footprint can
add as much as 0.2 pF of capacitance to ground if the ground
plane is not cleared from under the mounting pads. The low
distortion pinout of the ADA4899-1 reduces the distance
between the output and the inverting input of the amplifier.
This helps minimize the parasitic inductance and capacitance
of the feedback path, which reduces ringing and second harmonic
distortion.

Power Supply Bypassing

Power supply bypassing for the ADA4899-1 has been optimized
for frequency response and distortion performance. Figure 40

hows the recommended values and location of the bypass

s

1.02kΩ

V

REF

= 2.50V

0.1µF2.2µF

+

–5V

2kΩ

DISABLE

+5V

0.1µF

ADA4899-1

capacitors. Power supply bypassing is critical for stability,

2V p-p

15MHz

Figure 51. ADA4899-1 2:1 Mux Schematic

–5V

0.1µF

05720-064

frequency response, distortion, and PSR performance. The

0.1 μF capacitors shown in
s

upply pins of the ADA4899-1 as possible. The electrolytic
capacitors should be directly adjacent to the 0.1 μF capacitors.
The capacitor between the two supplies helps improve PSR and
distortion performance. In some cases, additional paralleled
capacitors can help improve frequency and transient response.

05720-065

Figure 40 should be as close to the

Rev. B | Page 16 of 20

ADA4899-1

www.BDTIC.com/ADI

Grounding

Ground and power planes should be used where possible.
Ground and power planes reduce the resistance and inductance
of the power planes and ground returns. The returns for the
input, output terminations, bypass capacitors, and R
be kept as close to the ADA4899-1 as possible. The output load
ground and the bypass capacitor grounds should be returned to
the same point on the ground plane to minimize parasitic trace
inductance, ringing, and overshoot and to improve distortion
performance.

The ADA4899-1 packages feature an exposed paddle. For
optimum electrical and thermal performance, solder this
paddle to ground. For more information on high speed circuit
design, see

Boa

A Practical Guide to High-Speed Printed-Circuit-

rd Layout.

should all

G

Rev. B | Page 17 of 20

ADA4899-1

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

5.00 (0.197)

4.00 (0.157)

3.90 (0.154)

3.80 (0.150)

4.90 (0.193)

4.80 (0.189)

85

TOP VIEW

6.20 (0.244)

6.00 (0.236)

41

5.80 (0.228)

2.29 (0.090)

2.29 (0.090)

1.27 (0.05)
BSC

1.75 (0.069)

1.35 (0.053)

0.10 (0.004)
MAX

COPLANARITY

0.10

CONTROLL ING DIMENSIONS ARE IN MILLI METER; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

0.51 (0.020)

0.31 (0.012)

COMPLIANT TO JEDEC STANDARDS MS-012-A A

1.65 (0.065)

1.25 (0.049)

SEATING
PLANE

Figure 53. 8-Lead Standard Small Outline

BOTTOM VIEW

(PINS UP)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.020)

0.25 (0.010)

8°
0°

45°

1.27 (0.050)

0.40 (0.016)

Package with Exposed Pad [SOIC_N_EP]

060506-A

(RD-8-1)

Dimensions shown in millimeters and (inches)

INDICATOR

0.90 MAX

0.85 NOM

3.25

PIN 1

12° MAX

3.00 SQ

2.75

TOP

VIEW

0.70 MAX

0.65 TYP

2.95

2.75 SQ

2.55

0.05 MAX

0.01 NOM

0.20 REF

0.50

BSC

0.30

0.23

0.18

0.60 MAX

8

EXPOSED

(BOTTOM VIEW)

5

Figure 54. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]

mm × 3 mm Body, Very Thin, Dual Lead

3

(CP-8-2)

Dimensions shown in millimeters

PA D

4

0.50

0.40

0.30

1

1.60

1.45

1.30

PIN 1
INDICATOR

1.89

1.74

1.59

022107-A

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding Ordering Quantity

ADA4899-1YRDZ
ADA4899-1YRDZ-R7
ADA4899-1YRDZ-RL
ADA4899-1YCPZ-R2
ADA4899-1YCPZ-R7
ADA4899-1YCPZ-RL

1

Z = RoHS Compliant Part.

1

–40°C to +125°C 8-Lead SOIC_N_EP RD-8-1 1

1

–40°C to +125°C 8-Lead SOIC_N_EP RD-8-1 1,000

1

–40°C to +125°C 8-Lead SOIC_N_EP RD-8-1 2,500

1

–40°C to +125°C 8-Lead LFCSP_VD CP-8-2 250

1

–40°C to +125°C 8-Lead LFCSP_VD CP-8-2 HBC 1,500

1

–40°C to +125°C 8-Lead LFCSP_VD CP-8-2 HBC 5,000

Rev. B | Page 18 of 20

ADA4899-1

www.BDTIC.com/ADI

NOTES

Rev. B | Page 19 of 20

ADA4899-1

www.BDTIC.com/ADI

NOTES

©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05720-0-6/07(B)

Rev. B | Page 20 of 20