ANALOG DEVICES ADA4898-2 Service Manual
High Voltage, Low Noise, Low Distortion,
Unity-Gain Stable, High Speed Op Amp
ADA4898-1/ADA4898-2
Rev. D
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Fax: 781.461.3113 ©2008-2012 Analog Devices, Inc. All rights reserved.
NC
1
–IN
2
+IN
3
–V
S
4
PD
8
+V
S
7
V
OUT
6
NC
5
NC = NO CONNECT
TOP VIEW
(Not to Scale)
ADA4898-1
07037-001
07037-050
V
OUT1
1
–IN1
2
+IN1
3
–V
S
4
+V
S
8
V
OUT2
7
–IN2
6
+IN2
5
ADA4898-2
TOP VIEW
(Not to Scale)
07037-002
FREQUENCY ( Hz )
VOLTAGE NOISE (nV/√Hz)
CURRENT NOISE (pA/√Hz)
1
0.1
1
10
0.1
1
10
10 100 1k 10k 100k
CURRENT
VOLTAGE
Data Sheet
FEATURES
Ultralow noise
0.9 nV/√Hz
2.4 pA/√Hz
1.2 nV/√Hz at 10 Hz
Ultralow distortion: −93 dBc at 500 kHz
Wide supply voltage range: ±5 V to ±16 V
High speed
−3 dB bandwidth: 65 MHz (G = +1)
Slew rate: 55 V/µs
Unity gain stable
Low input offset voltage: 160 µV maximum
Low input offset voltage drift: 1 μV/°C
Low input bias current: −0.1 µA
Low input bias current drift: 2 nA/°C
Supply current: 8 mA
Power-down feature for single 8-lead package
APPLICATIONS
Instrumentation
Active filters
DAC buffers
SAR ADC drivers
Optoelectronics
GENERAL DESCRIPTION
The ADA4898 is an ultralow noise and distortion, unity gain
stable, voltage feedback op amp that is ideal for use in 16-bit and
18-bit systems with power supplies from ±5 V to ±16 V. The
ADA4898 features a linear, low noise input stage and internal
compensation that achieves high slew rates and low noise.
With the wide supply voltage range, low offset voltage, and wide
bandwidth, the ADA4898 is extremely versatile, and it features a
cancellation circuit that reduces input bias current.
The ADA4898 is available in an 8-lead SOIC package that
features an exposed metal paddle to improve power dissipation and
heat transfer to the negative supply plane. This EPA D offers a
significant thermal relief over traditional plastic packages. The
ADA4898 is rated to work over the extended industrial
temperature range of −40°C to +105°C.
Figure 3. Input Voltage Noise and Current Noise vs. Frequency
CONNECTION DIAGRAM
Figure 1. Single 8-Lead ADA4898-1 SOIC_N_EP (RD-8-1)
Figure 2. Dual 8-Lead ADA4898-2 SOIC_N_EP (RD-8-2)
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
ADA4898-1/ADA4898-2 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagram ....................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±15 V Supply ................................................................................. 3
±5 V Supply ................................................................................... 4
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Test Circuits ..................................................................................... 13
Theory of Operation ...................................................................... 14
PD
(Power-Down) Pin for the ADA4898-1 ............................ 14
0.1 Hz to 10 Hz Noise ................................................................ 14
Applications Information .............................................................. 15
Higher Feedback Resistor Gain Operation ............................. 15
Recommended Values for Various Gains ................................ 15
Noise ............................................................................................ 16
Circuit Considerations .............................................................. 16
PCB Layout ................................................................................. 16
Power Supply Bypassing ............................................................ 16
Grounding ................................................................................... 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
5/12—Rev. C to Rev. D
Changes to Figure 2 Caption ........................................................... 1
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
2/10—Rev. B to Rev. C
Added ADA4898-2 ........................................................ Throughout
Changes to Features .......................................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Figure 38, Figure 40, Figure 41 ................................. 14
Changes to Figure 46 ...................................................................... 15
Changes to Figure 47 ...................................................................... 16
Changes to PCB Layout Section ................................................... 17
Changes to Ordering Guide .......................................................... 20
6/09—Rev. A to Rev. B
Changes to General Description Section ...................................... 1
Changes to Specifications Section .................................................. 3
Changes to Figure 29 and Figure 31 ............................................. 11
Added Figure 32 ............................................................................. 12
Added Figure 41 ............................................................................. 13
Changes to
Added Table 6 ................................................................................. 14
Changes to Figure 45 ...................................................................... 15
8/08—Rev. 0 to Rev. A
Changes to General Description Section ....................................... 1
Changes to Table 5 ............................................................................. 6
Changes to Figure 17 ......................................................................... 9
Changes to Figure 28 ...................................................................... 10
Changes to Figure 29 and Figure 32 ............................................ 11
Added 0.1 Hz to 10 Hz Noise Section.......................................... 14
Added Figure 42 and Figure 43; Renumbered Sequentially ..... 14
Changes to Grounding Section..................................................... 16
Updated Outline Dimensions ....................................................... 17
5/08—Revision 0: Initial Release
PD
(Power-Down) Pin Section ................................ 14
Rev. D | Page 2 of 20
Data Sheet ADA4898-1/ADA4898-2
Input Current Noise
f = 1 kHz
2.4 pA/√Hz
Input Offset Voltage
RF = 1 kΩ, see Figure 43
20
125
µV
Input Capacitance
Differential mode
3.2 pF
Input Leakage Current
= +VS
0.1 µA
SPECIFICATIONS
±15 V SUPPLY
TA = 25°C, G = +1, RF = 0 Ω, RG open, RL = 1 kΩ to GND (for G > 1, RF = 100 Ω), unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth V
V
Bandwidth for 0.1 dB Flatness G = +2, V
Slew Rate V
Settling Time to 0.1% V
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion SFDR f = 100 kHz, V
f = 500 kHz, V
f = 1 MHz, V
Input Voltage Noise f = 1 kHz 0.9 nV/√Hz
DC PERFORMANCE
= 100 mV p-p 65 MHz
OUT
= 2 V p-p 14 MHz
OUT
= 2 V p-p 3.3 MHz
OUT
= 5 V step 55 V/µs
OUT
= 5 V step 85 ns
OUT
= 2 V p-p −116 dBc
OUT
= 2 V p-p −93 dBc
OUT
= 2 V p-p −79 dBc
OUT
Input Offset Voltage Drift RF = 1 kΩ, see Figure 43 1 µV/°C
Input Bias Current
RF = 1 kΩ, see Figure 43 −0.1 −0.4 µA
Input Bias Offset Current RF = 1 kΩ, see Figure 43 0.03 0.3 µA
Input Bias Current Drift RF = 1 kΩ, see Figure 43 2 nA/°C
Open-Loop Gain V
= ±5 V 99 103 dB
OUT
INPUT CHARACTERISTICS
Input Resistance Differential mode 5 kΩ
Common mode 30 MΩ
Common mode 2.5 pF
Input Common-Mode Voltage Range See Figure 43 ±11 V
Common-Mode Rejection Ratio VCM = ±2 V −103 −126 dB
(POWER-DOWN) PIN (ADA4898-1)
PD
Input Voltages Chip powered down ≤−14 V
PD
Chip enabled ≥−13 V
Turn On Time V
PD
Turn Off Time V
PD
= 100 mV p-p 100 ns
OUT
= 100 mV p-p 20 μs
OUT
PD
= −VS −0.2 µA
PD
OUTPUT CHARACTERISTICS
Output Voltage Swing RL // (RF + RG) = 500 Ω, see Figure 43 −11.0 to +11.8 −11.7 to +12.1 V
RL // (RF + RG) = 1 kΩ, see Figure 43 −12.5 to +12.5 −12.8 to +12.7 V
Linear Output Current f = 100 kHz, SFDR = −70 dBc, RL = 150 Ω 40 mA
Short-Circuit Current Sinking/sourcing 150 mA
Off Isolation f = 1 MHz, PD = −VS 80 dB
POWER SUPPLY
Operating Range ±4.5 ±16.5 V
Quiescent Current per Amplifier
= +VS 7.9 8.7 mA
PD
= −VS 0.1 0.3 mA
PD
Positive Power Supply Rejection Ratio +VS = 15 V to 17 V, −VS = −15 V −98 −107 dB
Negative Power Supply Rejection Ratio +VS = 15 V, −VS = −15 V to −17 V −100 −114 dB
Rev. D | Page 3 of 20
ADA4898-1/ADA4898-2 Data Sheet
f = 500 kHz, V
= 2 V p-p
−95 dBc
INPUT CHARACTERISTICS
Input Voltages
Chip powered down
≤−4 V
Negative Power Supply Rejection Ratio
+VS = 5 V, −VS = −5 V to −7 V
−97
−104
dB
±5 V SUPPLY
TA = 25°C, G = +1, RF = 0 Ω, RG open, RL = 1 kΩ to GND (for G > 1, RF = 100 Ω), unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth V
V
Bandwidth for 0.1 dB Flatness G = +2, V
Slew Rate V
Settling Time to 0.1% V
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion SFDR f = 100 kHz, V
f = 1 MHz, V
Input Voltage Noise f = 1 kHz 0.9 nV/√Hz
Input Current Noise f = 1 kHz 2.4 pA/√Hz
DC PERFORMANCE
Input Offset Voltage RF = 1 kΩ, see Figure 43 30 160 µV
Input Offset Voltage Drift RF = 1 kΩ, see Figure 43 1 µV/°C
Input Bias Current RF = 1 kΩ, see Figure 43 −0.1 −0.5 µA
Input Bias Offset Current RF = 1 kΩ, see Figure 43 0.05 0.3 µA
Input Bias Current Drift RF = 1 kΩ, see Figure 43 2 nA/°C
Open-Loop Gain V
= 100 mV p-p 57 MHz
OUT
= 2 V p-p 12 MHz
OUT
= 2 V p-p 3 MHz
OUT
= 2 V step 50 V/µs
OUT
= 2 V step 90 ns
OUT
= 2 V p-p −110 dBc
OUT
OUT
= 2 V p-p −78 dBc
OUT
= ±1 V 87 94 dB
OUT
Input Resistance Differential mode 5 kΩ
Common mode 30 MΩ
Input Capacitance Differential mode 3.2 pF
Common mode 2.5 pF
Input Common-Mode Voltage Range See Figure 43 −3 to +2.5 V
Common-Mode Rejection Ratio ΔVCM = 1 V p-p −102 −120 dB
(POWER-DOWN) PIN (ADA4898-1)
PD
PD
Chip enabled ≥−3 V
Turn On Time V
PD
Turn Off Time V
PD
Input Leakage Current
= 100 mV p-p 100 ns
OUT
= 100 mV p-p 20 μs
OUT
= +VS 0.1 µA
PD
= −VS −2 µA
PD
OUTPUT CHARACTERISTICS
Output Voltage Swing RL // (RF + RG) = 500 Ω, see Figure 43 ±3.1 ±3.2 V
RL // (RF + RG) = 1 kΩ, see Figure 43 ±3.3 ±3.4 V
Linear Output Current f = 100 kHz, SFDR = −70 dBc, RL = 150 Ω 8 mA
Short-Circuit Current Sinking/sourcing 150 mA
Off Isolation f = 1 MHz, PD = −VS 80 dB
POWER SUPPLY
Operating Range ±4.5 ±16.5 V
Quiescent Current Per Amplifier
= +VS 7.5 8.4 mA
PD
= −VS 0.1 0.2 mA
PD
Positive Power Supply Rejection Ratio +VS = 5 V to 7 V, −VS = −5 V −95 −100 dB
Rev. D | Page 4 of 20
Data Sheet ADA4898-1/ADA4898-2
Power Dissipation
See Figure 4
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
5.0
4.5
07037-003
AMBIENT T E M P E RATURE (°C)
MAXIMUM POWER DISSIPATION (W)
0 20 40 60 80 10010 30 50 70 90–40 –20–30 –10
ADA4898-2
ADA4898-1
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 36 V
Differential Mode Input Voltage ±1.5 V
Common-Mode Input Voltage ±11.4 V
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +105°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions; that is, θJA is
specified for a device soldered in the circuit board with its
exposed paddle soldered to a pad on the PCB surface that is
thermally connected to a copper plane, with zero airflow.
The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the output load drive. The quiescent power is
the voltage between the supply pins (V
current (I
). The power dissipated due to the load drive depends
S
upon the particular application. For each output, the power due
to load drive is calculated by multiplying the load current by the
associated voltage drop across the device. RMS voltages and
currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θ
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θ
. The exposed paddle on the underside of the
JA
package must be soldered to a pad on the PCB surface that is
thermally connected to a copper plane to achieve the specified θ
Figure 4 shows the maximum power dissipation vs. the ambient
temperature for the single and dual 8-lead SOIC_N_EP on a
JEDEC standard 4-layer board, with its underside paddle
soldered to a pad that is thermally connected to a PCB plane. θ
values are approximations.
) is the sum of the
D
) times the quiescent
S
JA
. In
.
JA
JA
Table 4.
Package Type θJA θJC Unit
Single 8-Lead SOIC_N_EP on a 4-Layer Board
Dual 8-Lead SOIC_N_EP on a 4-Layer Board
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4898 package is
limited by the associated rise in junction temperature (T
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the ADA4898. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
47 29
42 29
) on
J
°C/W
°C/W
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
Rev. D | Page 5 of 20
ADA4898-1/ADA4898-2 Data Sheet
07037-046
NC
1
–IN
2
+IN
3
–V
S
4
PD
8
+V
S
7
V
OUT
6
NC
5
ADA4898-1
TOP VIEW
(Not to S cale)
NOTES
1. EXPOSED P AD CAN BE CONNECTED
TO THE NEGATIVE SUPPLY (−V
S
) OR
LEFT FLOATING.
07037-051
V
OUT1
1
–IN1
2
+IN1
3
–V
S
4
+V
S
8
V
OUT2
7
–IN2
6
+IN2
5
ADA4898-2
TOP VIEW
(Not to S cale)
NOTES
1. EXPOSED P AD CAN BE CONNECTED
TO THE NEGATIVE SUPPLY (−V
S
) OR
LEFT FLOATING.
3
+IN1
Noninverting Input 1.
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 5. Single 8-Lead SOIC_N_EP Pin Con figuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 NC No Connect.
2 −IN Inverting Input.
3 +IN Noninverting Input.
4 −VS Negative Supply.
5 NC No Connect.
6 V
Output.
OUT
7 +VS Positive Supply.
8
Power Down Not.
PD
EP Exposed Pad. Can be connected to the negative supply (−VS) or can be left floating.
Figure 6. Dual 8-Lead SOIC_N_EP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 V
2 −IN1 Inverting Input 1.
4 −VS Negative Supply.
5 +IN2 Noninverting Input 2.
6 −IN2 Inverting Input 2.
7 V
8 +VS Positive Supply.
EP Exposed Pad. Can be connected to the negative supply (−VS) or can be left floating.
Output 1.
OUT1
Output 2.
OUT2
Rev. D | Page 6 of 20
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