ANALOG DEVICES ADA4898-2 Service Manual

High Voltage, Low Noise, Low Distortion,

Unity-Gain Stable, High Speed Op Amp

ADA4898-1/ADA4898-2

Rev. D

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NC

1

–IN

2

+IN

3

–V

S

4

PD

8

+V

S

7

V

OUT

6

NC

5

NC = NO CONNECT

TOP VIEW

(Not to Scale)

ADA4898-1

07037-001

07037-050

V

OUT1

1

–IN1

2

+IN1

3

–V

S

4

+V

S

8

V

OUT2

7

–IN2

6

+IN2

5

ADA4898-2

TOP VIEW

(Not to Scale)

07037-002

FREQUENCY ( Hz )

VOLTAGE NOISE (nV/√Hz)

CURRENT NOISE (pA/√Hz)

1

0.1

1

10

0.1

1

10

10 100 1k 10k 100k

CURRENT

VOLTAGE

Data Sheet

FEATURES

Ultralow noise

0.9 nV/√Hz

2.4 pA/√Hz

1.2 nV/√Hz at 10 Hz
Ultralow distortion: −93 dBc at 500 kHz
Wide supply voltage range: ±5 V to ±16 V
High speed

−3 dB bandwidth: 65 MHz (G = +1)

Slew rate: 55 V/µs
Unity gain stable
Low input offset voltage: 160 µV maximum
Low input offset voltage drift: 1 μV/°C
Low input bias current: −0.1 µA
Low input bias current drift: 2 nA/°C
Supply current: 8 mA
Power-down feature for single 8-lead package

APPLICATIONS

Instrumentation
Active filters
DAC buffers
SAR ADC drivers
Optoelectronics

GENERAL DESCRIPTION

The ADA4898 is an ultralow noise and distortion, unity gain
stable, voltage feedback op amp that is ideal for use in 16-bit and
18-bit systems with power supplies from ±5 V to ±16 V. The
ADA4898 features a linear, low noise input stage and internal
compensation that achieves high slew rates and low noise.

With the wide supply voltage range, low offset voltage, and wide
bandwidth, the ADA4898 is extremely versatile, and it features a
cancellation circuit that reduces input bias current.

The ADA4898 is available in an 8-lead SOIC package that
features an exposed metal paddle to improve power dissipation and
heat transfer to the negative supply plane. This EPA D offers a
significant thermal relief over traditional plastic packages. The
ADA4898 is rated to work over the extended industrial
temperature range of −40°C to +105°C.

Figure 3. Input Voltage Noise and Current Noise vs. Frequency

CONNECTION DIAGRAM

Figure 1. Single 8-Lead ADA4898-1 SOIC_N_EP (RD-8-1)

Figure 2. Dual 8-Lead ADA4898-2 SOIC_N_EP (RD-8-2)

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

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ADA4898-1/ADA4898-2 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Connection Diagram ....................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

±15 V Supply ................................................................................. 3

±5 V Supply ................................................................................... 4

Absolute Maximum Ratings ............................................................ 5

Thermal Resistance ...................................................................... 5

Maximum Power Dissipation ..................................................... 5

ESD Caution .................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Test Circuits ..................................................................................... 13

Theory of Operation ...................................................................... 14

PD

(Power-Down) Pin for the ADA4898-1 ............................ 14

0.1 Hz to 10 Hz Noise ................................................................ 14

Applications Information .............................................................. 15

Higher Feedback Resistor Gain Operation ............................. 15

Recommended Values for Various Gains ................................ 15

Noise ............................................................................................ 16

Circuit Considerations .............................................................. 16

PCB Layout ................................................................................. 16

Power Supply Bypassing ............................................................ 16

Grounding ................................................................................... 16

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 17

REVISION HISTORY

5/12—Rev. C to Rev. D

Changes to Figure 2 Caption ........................................................... 1

Updated Outline Dimensions ....................................................... 17

Changes to Ordering Guide .......................................................... 17

2/10—Rev. B to Rev. C

Added ADA4898-2 ........................................................ Throughout

Changes to Features .......................................................................... 1

Changes to Table 1 ............................................................................ 3

Changes to Table 2 ............................................................................ 4

Changes to Figure 38, Figure 40, Figure 41 ................................. 14

Changes to Figure 46 ...................................................................... 15

Changes to Figure 47 ...................................................................... 16

Changes to PCB Layout Section ................................................... 17

Changes to Ordering Guide .......................................................... 20

6/09—Rev. A to Rev. B

Changes to General Description Section ...................................... 1

Changes to Specifications Section .................................................. 3

Changes to Figure 29 and Figure 31 ............................................. 11

Added Figure 32 ............................................................................. 12

Added Figure 41 ............................................................................. 13

Changes to

Added Table 6 ................................................................................. 14

Changes to Figure 45 ...................................................................... 15

8/08—Rev. 0 to Rev. A

Changes to General Description Section ....................................... 1

Changes to Table 5 ............................................................................. 6

Changes to Figure 17 ......................................................................... 9

Changes to Figure 28 ...................................................................... 10

Changes to Figure 29 and Figure 32 ............................................ 11

Added 0.1 Hz to 10 Hz Noise Section.......................................... 14

Added Figure 42 and Figure 43; Renumbered Sequentially ..... 14

Changes to Grounding Section..................................................... 16

Updated Outline Dimensions ....................................................... 17

5/08—Revision 0: Initial Release

PD

(Power-Down) Pin Section ................................ 14

Rev. D | Page 2 of 20

Data Sheet ADA4898-1/ADA4898-2

Input Current Noise

f = 1 kHz

2.4 pA/√Hz

Input Offset Voltage

RF = 1 kΩ, see Figure 43

20

125

µV

Input Capacitance

Differential mode

3.2 pF

Input Leakage Current

= +VS

0.1 µA

SPECIFICATIONS

±15 V SUPPLY

TA = 25°C, G = +1, RF = 0 Ω, RG open, RL = 1 kΩ to GND (for G > 1, RF = 100 Ω), unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth V

V

Bandwidth for 0.1 dB Flatness G = +2, V
Slew Rate V
Settling Time to 0.1% V

NOISE/DISTORTION PERFORMANCE

Harmonic Distortion SFDR f = 100 kHz, V

f = 500 kHz, V

f = 1 MHz, V
Input Voltage Noise f = 1 kHz 0.9 nV/√Hz

DC PERFORMANCE

= 100 mV p-p 65 MHz

OUT

= 2 V p-p 14 MHz

OUT

= 2 V p-p 3.3 MHz

OUT

= 5 V step 55 V/µs

OUT

= 5 V step 85 ns

OUT

= 2 V p-p −116 dBc

OUT

= 2 V p-p −93 dBc

OUT

= 2 V p-p −79 dBc

OUT

Input Offset Voltage Drift RF = 1 kΩ, see Figure 43 1 µV/°C
Input Bias Current

RF = 1 kΩ, see Figure 43 −0.1 −0.4 µA
Input Bias Offset Current RF = 1 kΩ, see Figure 43 0.03 0.3 µA
Input Bias Current Drift RF = 1 kΩ, see Figure 43 2 nA/°C
Open-Loop Gain V

= ±5 V 99 103 dB

OUT

INPUT CHARACTERISTICS

Input Resistance Differential mode 5 kΩ
Common mode 30 MΩ

Common mode 2.5 pF
Input Common-Mode Voltage Range See Figure 43 ±11 V
Common-Mode Rejection Ratio VCM = ±2 V −103 −126 dB

(POWER-DOWN) PIN (ADA4898-1)

PD

Input Voltages Chip powered down ≤−14 V

PD
Chip enabled ≥−13 V

Turn On Time V

PD

Turn Off Time V

PD

= 100 mV p-p 100 ns

OUT

= 100 mV p-p 20 μs

OUT

PD

= −VS −0.2 µA

PD

OUTPUT CHARACTERISTICS

Output Voltage Swing RL // (RF + RG) = 500 Ω, see Figure 43 −11.0 to +11.8 −11.7 to +12.1 V
RL // (RF + RG) = 1 kΩ, see Figure 43 −12.5 to +12.5 −12.8 to +12.7 V
Linear Output Current f = 100 kHz, SFDR = −70 dBc, RL = 150 Ω 40 mA
Short-Circuit Current Sinking/sourcing 150 mA
Off Isolation f = 1 MHz, PD = −VS 80 dB

POWER SUPPLY

Operating Range ±4.5 ±16.5 V
Quiescent Current per Amplifier

= +VS 7.9 8.7 mA

PD

= −VS 0.1 0.3 mA

PD
Positive Power Supply Rejection Ratio +VS = 15 V to 17 V, −VS = −15 V −98 −107 dB
Negative Power Supply Rejection Ratio +VS = 15 V, −VS = −15 V to −17 V −100 −114 dB

Rev. D | Page 3 of 20

ADA4898-1/ADA4898-2 Data Sheet

f = 500 kHz, V

= 2 V p-p

−95 dBc

INPUT CHARACTERISTICS

Input Voltages

Chip powered down

≤−4 V

Negative Power Supply Rejection Ratio

+VS = 5 V, −VS = −5 V to −7 V

−97

−104

dB

±5 V SUPPLY

TA = 25°C, G = +1, RF = 0 Ω, RG open, RL = 1 kΩ to GND (for G > 1, RF = 100 Ω), unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth V

V

Bandwidth for 0.1 dB Flatness G = +2, V
Slew Rate V
Settling Time to 0.1% V

NOISE/DISTORTION PERFORMANCE

Harmonic Distortion SFDR f = 100 kHz, V

f = 1 MHz, V

Input Voltage Noise f = 1 kHz 0.9 nV/√Hz
Input Current Noise f = 1 kHz 2.4 pA/√Hz

DC PERFORMANCE

Input Offset Voltage RF = 1 kΩ, see Figure 43 30 160 µV
Input Offset Voltage Drift RF = 1 kΩ, see Figure 43 1 µV/°C
Input Bias Current RF = 1 kΩ, see Figure 43 −0.1 −0.5 µA
Input Bias Offset Current RF = 1 kΩ, see Figure 43 0.05 0.3 µA
Input Bias Current Drift RF = 1 kΩ, see Figure 43 2 nA/°C
Open-Loop Gain V

= 100 mV p-p 57 MHz

OUT

= 2 V p-p 12 MHz

OUT

= 2 V p-p 3 MHz

OUT

= 2 V step 50 V/µs

OUT

= 2 V step 90 ns

OUT

= 2 V p-p −110 dBc

OUT

OUT

= 2 V p-p −78 dBc

OUT

= ±1 V 87 94 dB

OUT

Input Resistance Differential mode 5 kΩ
Common mode 30 MΩ
Input Capacitance Differential mode 3.2 pF
Common mode 2.5 pF
Input Common-Mode Voltage Range See Figure 43 −3 to +2.5 V
Common-Mode Rejection Ratio ΔVCM = 1 V p-p −102 −120 dB

(POWER-DOWN) PIN (ADA4898-1)

PD

PD
Chip enabled ≥−3 V

Turn On Time V

PD

Turn Off Time V

PD
Input Leakage Current

= 100 mV p-p 100 ns

OUT

= 100 mV p-p 20 μs

OUT

= +VS 0.1 µA

PD

= −VS −2 µA

PD

OUTPUT CHARACTERISTICS

Output Voltage Swing RL // (RF + RG) = 500 Ω, see Figure 43 ±3.1 ±3.2 V
RL // (RF + RG) = 1 kΩ, see Figure 43 ±3.3 ±3.4 V
Linear Output Current f = 100 kHz, SFDR = −70 dBc, RL = 150 Ω 8 mA
Short-Circuit Current Sinking/sourcing 150 mA
Off Isolation f = 1 MHz, PD = −VS 80 dB

POWER SUPPLY

Operating Range ±4.5 ±16.5 V
Quiescent Current Per Amplifier

= +VS 7.5 8.4 mA

PD

= −VS 0.1 0.2 mA

PD

Positive Power Supply Rejection Ratio +VS = 5 V to 7 V, −VS = −5 V −95 −100 dB

Rev. D | Page 4 of 20

Data Sheet ADA4898-1/ADA4898-2

Power Dissipation

See Figure 4

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

5.0

4.5

07037-003

AMBIENT T E M P E RATURE (°C)

MAXIMUM POWER DISSIPATION (W)

0 20 40 60 80 10010 30 50 70 90–40 –20–30 –10

ADA4898-2

ADA4898-1

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage 36 V

Differential Mode Input Voltage ±1.5 V
Common-Mode Input Voltage ±11.4 V
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +105°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions; that is, θJA is
specified for a device soldered in the circuit board with its
exposed paddle soldered to a pad on the PCB surface that is
thermally connected to a copper plane, with zero airflow.

The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the output load drive. The quiescent power is
the voltage between the supply pins (V
current (I

). The power dissipated due to the load drive depends

S

upon the particular application. For each output, the power due
to load drive is calculated by multiplying the load current by the
associated voltage drop across the device. RMS voltages and
currents must be used in these calculations.

Airflow increases heat dissipation, effectively reducing θ
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θ

. The exposed paddle on the underside of the

JA

package must be soldered to a pad on the PCB surface that is
thermally connected to a copper plane to achieve the specified θ

Figure 4 shows the maximum power dissipation vs. the ambient
temperature for the single and dual 8-lead SOIC_N_EP on a
JEDEC standard 4-layer board, with its underside paddle
soldered to a pad that is thermally connected to a PCB plane. θ
values are approximations.

) is the sum of the

D

) times the quiescent

S

JA

. In

.

JA

JA

Table 4.

Package Type θJA θJC Unit

Single 8-Lead SOIC_N_EP on a 4-Layer Board
Dual 8-Lead SOIC_N_EP on a 4-Layer Board

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the ADA4898 package is
limited by the associated rise in junction temperature (T
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the ADA4898. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.

47 29
42 29

) on

J

°C/W
°C/W

Figure 4. Maximum Power Dissipation vs. Ambient Temperature

ESD CAUTION

Rev. D | Page 5 of 20

ADA4898-1/ADA4898-2 Data Sheet

07037-046

NC

1

–IN

2

+IN

3

–V

S

4

PD

8

+V

S

7

V

OUT

6

NC

5

ADA4898-1

TOP VIEW

(Not to S cale)

NOTES

1. EXPOSED P AD CAN BE CONNECTED

TO THE NEGATIVE SUPPLY (−V

S

) OR

LEFT FLOATING.

07037-051

V

OUT1

1

–IN1

2

+IN1

3

–V

S

4

+V

S

8

V

OUT2

7

–IN2

6

+IN2

5

ADA4898-2

TOP VIEW

(Not to S cale)

NOTES

1. EXPOSED P AD CAN BE CONNECTED

TO THE NEGATIVE SUPPLY (−V

S

) OR

LEFT FLOATING.

3

+IN1

Noninverting Input 1.

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 5. Single 8-Lead SOIC_N_EP Pin Con figuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 NC No Connect.
2 −IN Inverting Input.
3 +IN Noninverting Input.
4 −VS Negative Supply.
5 NC No Connect.
6 V

Output.

OUT

7 +VS Positive Supply.
8

Power Down Not.

PD

EP Exposed Pad. Can be connected to the negative supply (−VS) or can be left floating.

Figure 6. Dual 8-Lead SOIC_N_EP Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 V
2 −IN1 Inverting Input 1.

4 −VS Negative Supply.
5 +IN2 Noninverting Input 2.
6 −IN2 Inverting Input 2.
7 V
8 +VS Positive Supply.
EP Exposed Pad. Can be connected to the negative supply (−VS) or can be left floating.

Output 1.

OUT1

Output 2.

OUT2

Rev. D | Page 6 of 20

Data Sheet ADA4898-1/ADA4898-2

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

3

1 10 100

07037-004

FREQUENCY (MHz)

NORMALIZED CLOSED-LOOP GAIN (dB)

R

L

= 1kΩ

V

OUT

= 100mV p-p

VS = ±15V

G = +1

R

F

= 0Ω

G = +1

R

F

= 100Ω

G = +2

R

F

= 100Ω

G = +5

RF = 100Ω

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

3

1 10 100

07037-005

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

RL = 1kΩ

RL = 100Ω

R

L

= 200Ω

G = +1
V

OUT

= 100mV p-p

V

S

= ±15V

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

1 10 100

07037-006

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

T

A

= +25°C

G = +1
RL = 1kΩ
V

OUT

= 100mV p-p

VS = ±15V

TA = +105°C T

A

= +85°C

TA = –40°C

T

A

= 0°C

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

3

1 10 100

07037-007

FREQUENCY (MHz)

NORMALIZED CLOSED-LOOP GAIN (dB)

RL = 1kΩ
V

OUT

= 2V p-p

VS = ±15V

G = +1

R

F

= 0Ω

G = +1

RF = 100Ω

G = +5

RF = 100Ω

G = +2

R

F

= 100Ω

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

1 10 100

07037-008

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

R

L

= 1kΩ

R

L

= 100Ω

G = +1
V

OUT

= 2V p-p

V

S

= ±15V

R

L

= 200Ω

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

1 10 100

07037-009

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

G = +1
RL = 1kΩ
V

OUT

= 2V p-p

VS = ±15V

TA = –40°C

TA = +105°C

TA = +25°C

T

A

= 0°C

TA = +85°C

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 7. Small Signal Frequency Response for Various Gains

Figure 8. Small Signal Frequency Response for Various Loads

Figure 10. Large Signal Frequency Response for Various Gains

Figure 11. Large Signal Frequency Response for Various Loads

Figure 9. Small Signal Frequency Response for Various Temperatures

Figure 12. Large Signal Frequency Response for Various Temperatures

Rev. D | Page 7 of 20

ADA4898-1/ADA4898-2 Data Sheet

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

1 10 100

07037-010

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

G = +1
R

L

= 1kΩ

V

OUT

= 100mV p-p

V

S

= ±15V

VS = ±5V

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

3

1 10 100

07037-011

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

G = +1
RL = 1kΩ
V

OUT

= 100mV p-p

VS = ±15V

CL = 33pF

C

L

= 15pF

CL = 5pF

CL = 0pF

0.1

1

10

1 10 100 1k 10k 100k

07037-012

FREQUENCY ( Hz )

VOLTAGE NOISE (nV/√Hz)

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

1 10 100

07037-013

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

V

S

= ±15V

G = +1
R

L

= 1kΩ

V

OUT

= 2V p-p

V

S

= ±5V

–0.5

–0.4

–0.3

–0.2

–0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

100k 1M 10M

07037-014

FREQUENCY ( Hz )

NORMALIZED GAIN (d B)

G = +2
R

L

= 1kΩ

VS = ±15V

V

OUT

= 2V p-p

V

OUT

= 0.1V p-p

07037-035

FREQUENCY ( Hz )

INPUT CURRENT NOISE (pA/

Hz)

1

1

10

100

10 100 1k

10k 100k

Figure 13. Small Signal Frequency Response for Various Supply Voltages

Figure 14. Small Signal Frequency Response for Various Capacitive Loads

Figure 16. Large Signal Frequency Response for Various Supply Voltages

Figure 17. 0.1 dB Flatness for Various Output Voltages

Figure 15. Voltage Noise vs. Frequency

Figure 18. Input Current Noise vs. Frequency

Rev. D | Page 8 of 20

Data Sheet ADA4898-1/ADA4898-2

–20

–10

0

10

20

30

40

50

60

70

80

110

90

100

07037-016

FREQUENCY ( Hz )

OPEN-LOOP GAIN (dB)

100k 1M 1G10M 100M

PHASE

GAIN

–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
–190
–200

OPEN-LOOP PHASE (Degrees)

ΔV

OUT

= ±5V

V

S

= ±15V

07037-017

FREQUENCY ( Hz )

DISTORTION (dBc)

–140

–120

–100

–80

–60

–40

–20

0

100k 1M 10M

G = +1, HD2

G = +1, HD3

G = +2, HD3, R

F

= 250Ω

G = +2, HD2, R

F

= 250Ω

RL = 1kΩ
VS = ±15V
V

OUT

= 2V p-p

07037-018

FREQUENCY ( Hz )

DISTORTION (dBc)

–140

–120

–100

–80

–60

–40

–20

0

100k 1M 10M

R

L

= 1kΩ, HD3

R

L

= 100Ω, HD3

G = +1
V

S

= ±15V

V

OUT

= 2V p-p

R

L

= 1kΩ, HD2

RL = 100Ω, HD2

1

07073-019

OUTPUT VOLTAGE (V p-p)

DISTORTION (dBc)

–135

–125

–120

–130

–115

–110

–105

–100

–95

2 3 4 5 6

HD2

HD3

f = 100kHz
G = +1
RL = 1kΩ
V

S

= ±15V

07037-020

FREQUENCY ( Hz )

DISTORTION (dBc)

–140

–120

–100

–80

–60

–40

–20

0

100k 1M

10M

R

L

= 1kΩ, HD3

R

L

= 100Ω, HD3

R

L

= 100Ω, HD2

G = +1
V

S

= ±5V

V

OUT

= 2V p-p

R

L

= 1kΩ, HD2

–0.04

–0.02

0

0.02

0.04

0.06

0.08

0.10

0.12

0.14

CL = 0pF

C

L

= 5pF

C

L

= 15pF

CL = 33pF

07037-021

TIME (20ns/DIV)

OUTPUT VOLTAGE (V)

V

OUT

= 100mV p-p
G = +1
R

L

= 1kΩ

V

S

= ±15V

Figure 19. Open-Loop Gain and Phase vs. Frequency

Figure 20. Harmonic Distortion vs. Frequency and Gain

Figure 22. Harmonic Distortion vs. Output Amplitude

Figure 23. Harmonic Distortion vs. Frequency and Loads

Figure 21. Harmonic Distortion vs. Frequency and Loads

Figure 24. Small Signal Transient Response for Various Capacitive Loads

Rev. D | Page 9 of 20

ADA4898-1/ADA4898-2 Data Sheet

0.14
V

= 100mV p-p

OUT

R

=1kΩ

0.12

0.10

0.08

0.06

0.04

0.02

OUTPUT VOLT AGE (V)

–0.02

–0.04

L

V

= ±15V

S

0

G = +1

G = +2

TIME (20n s/DIV)

Figure 25. Small Signal Transient Response for Various Gains

2.5
V

= 2V p-p

OUT

G = +1
R

= 100Ω

L

2.0

1.5

1.0

V

= ±5V

S

2.5
V

= 2V p-p

OUT

G = +1
R

= 1kΩ

L

2.0

1.5

1.0

0.5

OUTPUT VO LTAGE (V )

0

07037-022

–0.5

= ±5V

V

S

TIME (100n s/DIV)

VS = ±15V

07037-025

Figure 28. Large Signal Transient Response for

= 1 kΩ

L

2.5

2.0

1.5

1.0

Various Supply Voltages, R

V

= 2V p-p

OUT

= 1kΩ

R

L

= ±15V

V

S

G = +2

0.5

OUTPUT VOLT AGE (V)

0

–0.5

TIME (1 00ns/DIV)

Figure 26. Large Signal Transient Response for

Various Supply Voltages, R

0.5

0.4

INPUT

0.3

0.2

0.1

0

–0.1

SETTLING TIME (%)

–0.2

–0.3

–0.4

–0.5

OUTPUT

∆t = 85ns

TIME (10n s/DIV)

Figure 27. Settling Time

VS = ±15V

= 100 Ω

L

G = +1
R

= 1kΩ

L

V

OUT

V

= ±15V

S

= 5V p-p

0.5

OUTPUT VOLTAGE (V)

0

07037-023

–0.5

TIME (1 00ns/DIV)

G = +1

07037-024

Figure 29. Large Signal Transient Response for Various Gains

10k

PD LOW

1k

100

10

OUTPUT IMPEDANCE (Ω)

1

0.1
100k 1M 100M10M

07037-026

FREQUENCY (Hz)

PD HIGH

G = +1

= 0Ω

R

F

= ±15V

V

S

07037-028

Figure 30. Output Impedance vs. Frequency

Rev. D | Page 10 of 20

Data Sheet ADA4898-1/ADA4898-2

–

V

–

0

–20

–40

–60

–80

CMRR (dB)

–100

–120

–140

100 10M1k 100k 1M10k

= 100mV p-p

∆V

CM

FREQUENCY (Hz)

∆VCM = 1V p-p

G = +1
R

= 0Ω

F

R

= 100Ω

L

V

= ±15V

S

Figure 31. Common-Mode Rejection Ratio (CMRR) vs. Frequency

15

POSITIVE SWING,
V

= +15V

12

= ±15

S

NEGATIVE SWING,
V

S

9

6

3

OUTPUT VOLTAGE SWING (V), V

0

50 100 1000 4000

07037-029

S

= –15V

POSITIVE SWING, V

LOAD RESIST ANCE (Ω)

Figure 34 Output Swing vs. Load, G = +2, Load = R

NEGATIVE SWING,

V

= –5V

S

= +5V

S

// (RF + RG)

L

5

4

= ±5V

S

3

2

1

OUTPUT VOLTAGE SWING (V), V

0

07037-100

45

V

= 0.1V p-p

OUT

–55

= 2V p-p

V

OUT

–65

PD ISOLATION (dB)

G = +1
R

L

V

–75

100k 1M 10M 100M

FREQUENCY (Hz)

S

Figure 32. PD Input to Output Isolation vs. Frequency

0

–20

–40

–60

PSRR (dB)

–80

–100

–120

+PSRR

–PSRR

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

G = +1

= 0Ω

R

F

= 100Ω

R

L

= ±15V

V

S

V

OUT

= 2V p-p

Figure 33. Power Supply Rejection Ratio (PSRR) vs. Frequency

= 1kΩ
= ±15V

40

G = +1

= 1kΩ

R

L

= 2V p-p

V

–50

OUT

–60

–70

–80

CROSSTALK (dB)

–90

–100

–110

07037-031

+IN1 TO V

1 10 100

+IN1 TO V

, VS = ±15V

OUT2

+IN2 TO V

FREQUENCY (MHz)

OUT2

+IN2 TO V

OUT1

, VS = ±5V

, VS = ±5V

OUT1

, VS = ±15V

07037-101

Figure 35. Crosstalk vs. Frequency

07037-030

Rev. D | Page 11 of 20

ADA4898-1/ADA4898-2 Data Sheet

1000

800

600

400

200

0

07037-032

INPUT BIAS CURRE NT (µA)

COUNT

–0.15–0.20–0.25 –0.10 0–0.05

N = 6180
MEAN: –0.13
SD: 0.02
V

S

= ±15V

1000

800

600

400

200

0

07037-033

INPUT OFFSET VOLTAGE (µV)

COUNT

0–30–60 30 1209060

N = 6180
MEAN: 27
SD: 20
V

S

= ±15V

Figure 36. Input Bias Current Distribution

Figure 37. Input Offset Voltage Distribution, VS = ±15 V

Rev. D | Page 12 of 20

Data Sheet ADA4898-1/ADA4898-2

IN

V

OUT

10µF

+V

S

–V

S

49.9Ω

R

L

0.1µF

0.1µF

+

10µF

07037-052

+

V

OUT

0.1µF

49.9Ω

+V

S

–V

S

R

L

10µF

+

AC

07037-053

IN

V

OUT

10µF

+V

S

–V

S

1kΩ

1kΩ

1kΩ

1kΩ

53.6Ω

R

L

+

10µF

+

07037-054

0.1µF

0.1µF

IN

V

OUT

10µF

+V

S

–V

S

R

G

R

F

49.9Ω

R

L

C

L

+

10µF

07037-055

+

0.1µF

0.1µF

0.1µF

V

OUT

+V

S

–V

S

R

L

10µF

+

AC

49.9Ω

07037-056

07037-139

+V

S

–V

S

+I

B

–I

B

200Ω

1kΩ

V

CONTROL

RIN = 20Ω

RF = 1kΩ

IN-AMP

V

OUT

TEST CIRCUITS

Figure 38. Typical Noninverting Load Configuration

Figure 39. Positive Power Supply Rejection

Figure 40. Common-Mode Rejection

Figure 41. Typical Capacitive Load Configuration

Figure 42. Negative Power Supply Rejection

Figure 43.DC Test Circuit

Rev. D | Page 13 of 20

ADA4898-1/ADA4898-2 Data Sheet

THEORY OF OPERATION

The ADA4898 is a voltage feedback op amp that combines unity
gain stability with 0.9 nV/√Hz input noise. It employs a highly
linear input stage that can maintain greater than −90 dBc (at
2 V p-p) distortion out to 600 kHz while in a unity-gain
configuration. This rare combination of unity gain stability, low
input-referred noise, and extremely low distortion is the result
of Analog Devices, Inc., proprietary op amp architecture and
high voltage bipolar processing technology.

The simplified ADA4898 topology, shown in Figure 44, is a
single gain stage with a unity gain output buffer. It has over 100 dB
of open-loop gain and maintains precision specifications, such
as CMRR, PSRR, and offset, to levels that are normally associated
with topologies having two or more gain stages.

m

R1

BUFFERg

C

C

Figure 44. Topology

V

OUT

R

L

07037-041

PD (POWER-DOWN) PIN FOR THE ADA4898-1

The PD pin saves power by decreasing the quiescent power
dissipated in the device. It is very useful when power is an issue
and the device does not need to be turned on at all times. The
response of the device is rapid when going from power-down
mode to full power operation mode. Note that
the output in a high-Z state, which means that the ADA4898
is not recommended for use as a multiplexer. Leaving the
pin floating keeps the amplifier in full power operation mode.

PD

does not put

PD

Table 7. Power-Down Voltage Control

Pin

PD

±15 V ±10 V ±5 V

Power-Down Mode ≤−14 V ≤−9 V ≤−4 V

0.1 Hz TO 10 Hz NOISE

Figure 45 shows the 0.1 Hz to 10 Hz voltage and current noise
of the ADA4898. The peak-to-peak noise voltage is below 0.5 μV.
Figure 46 shows the circuit used to measure the low frequency
noise. It uses a band-pass filter of approximately 0.1 Hz and 10 Hz
and a high gain stage feeding into an instrumentation amplifier.

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

OUTPUT VOLT AGE (µV)

–0.3

–0.4

–0.5

02 46 8101214161820

Figure 45. 0.1 Hz to 10 Hz Noise

TIME (s)

07037-047

FARADAY CAGE

R = 5.36kΩ, GAIN APPROX. 10Ω

10nF

–V

= –9V

S

1

R

G

AD620

2

–IN

3

+IN

4

–V

S

R

+V

OUTPUT

REF

8

G

7

S

6

5

+VS = +9V

10nF

COAX

FLOATING SHIELD

TEK

TDS 754A SCOPE

IN

07037-048

50Ω

= +5V

+V

R

+IN

DUT

ADA4898-1

–IN

–V

= –5V

R

+VS = +9V
(BATTERY)

7805

7905

–V

S

(BATTERY)

= –9V

50Ω

+V

–V

MOMENTARY

1kΩ

1µF

806kΩ

806kΩ

= +5V

R

= –5V

R

13Ω

= +9V

+V

S

+IN

AD743

–IN

–VS = –9V

10nF

13kΩ

10nF

OUT

15.8kΩ

1µF

Figure 46. Low Frequency Noise Circuit

Rev. D | Page 14 of 20

Data Sheet ADA4898-1/ADA4898-2

07037-043

V

IN

V

OUT

10µF

+V

S

–V

S

R

T

R

L

+

10µF

+

C

F

R

F

R

F

0.1µF

0.1µF

–15

–12

–9

–6

–3

0

3

6

9

12

07037-044

FREQUENCY ( Hz )

CLOSED-LOOP GAIN (dB)

100k 10M1M 100M

R

F

= 1kΩ, C

F

= 2.7pF

R

F

= 1kΩ

R

F

= 100Ω

G = +2
R

L

= 1kΩ

V

S

= ±15V

APPLICATIONS INFORMATION

HIGHER FEEDBACK RESISTOR GAIN OPERATION

The ADA4898 schematic for the noninverting gain
configuration shown in Figure 47 is nearly a textbook example.
The only exception is the feedback capacitor in parallel with
the feedback resistor, R
only when using a large R
difference between using a 100 Ω resistor and a 1 kΩ feedback
resistor. Due to the high input capacitance in the ADA4898 when
using a higher feedback resistor, more peaking appears in the
closed-loop gain. Using the lower feedback resistor resolves this
issue; however, when running at higher supplies (±15 V) with
an R

of 100 Ω, the system draws a lot of extra current into the

F

feedback network. To avoid this problem, a higher feedback
resistor can be used with a feedback capacitor in parallel. Figure 48
shows the effect of placing a feedback capacitor in parallel with
a larger R
C

F

. In this gain-of-2 configuration, RF = RG = 1 kΩ and

F

= 2.7 pF. When using CF, the peaking drops from 6 dB to less

than 2 dB.

, but this capacitor is recommended

F

value (>300 Ω). Figure 48 shows the

F

Figure 48. Small Signal Frequency Response for

Various Feedback Impedances

RECOMMENDED VALUES FOR VARIOUS GAINS

Table 8 provides a useful reference for determining various gains
and associated performance. R
than 1. A low feedback R
minimizes the contribution to the overall noise performance
of the amplifier.

is set to 100 Ω for gains greater

F

resistor value reduces peaking and

F

Figure 47. Noninverting Gain Schematic

Table 8. Gains and Recommended Resistor Values Associated with Them (Conditions: V

Gain RF (Ω) RG (Ω)

+1 0 N/A 65 55 0.9 1.29
[phone] 1.8 3.16
+5 100 24.9 9 45 4.5 7.07

−3 dB SS BW (MHz),
V

= 100 mV p-p

OUT

Slew Rate (V/µs),
V

= 2 V Step

OUT

Rev. D | Page 15 of 20

= ±5 V, TA = 25°C, RL = 1 kΩ, RT = 49.9 Ω)

S

ADA4898 Voltage
Noise (nV/√Hz), RTO

Total System Noise
(nV/√Hz), RTO

ADA4898-1/ADA4898-2 Data Sheet

GAIN FROM

B TO OUTPUT

= –

R2

R1

GAIN FROM

A TO OUTPUT

=

NOISE GAIN =

NG = 1 +

R2

R1

I

N–

V

N

V

N, R1

V

N, R3

R1

R2

I

N+

R3

4kTR2

4kTR1

4kTR3

V

N, R2

B

A

V

N

2

+ 4kTR3 + 4kTR1

R2

2

R1 + R2

I

N+

2

R32 + I

N–

2

R1 × R2

2

+ 4kTR2

R1

2

R1 + R2 R1 + R2

RTI NOISE =

RTO NOISE = NG × RTI NOISE

V

OUT

+

07037-045

)(4kBTR

NOISE

To analyze the noise performance of an amplifier circuit, identify
the noise sources, and then determine if each source has a
significant contribution to the overall noise performance of the
amplifier. To simplify the noise calculations, noise spectral densities
were used rather than actual voltages to leave bandwidth out of the
expressions. Noise spectral density, which is generally expressed
in nV/√Hz, is equivalent to the noise in a 1 Hz bandwidth.

The noise model shown in Figure 49 has six individual noise
sources: the Johnson noise of the three resistors, the op amp
voltage noise, and the current noise in each input of the amplifier.
Each noise source has its own contribution to the noise at the
output. Noise is generally specified as referring to input (RTI),
but it is often simpler to calculate the noise referred to the
output (RTO) and then divide by the noise gain to obtain the RTI
noise.

Figure 49. Op Amp Noise Analysis Model

All resistors have a Johnson noise that is calculated by

where:
k is Boltzmann’s constant (1.38 × 10

−23

J/K).

B is the bandwidth in Hertz.
T is the absolute temperature in Kelvin.
R is the resistance in ohms.

A simple relationship that is easy to remember is that a 50 Ω
resistor generates a Johnson noise of 1 nV/√Hz at 25°C.

In applications where noise sensitivity is critical, care must be
taken not to introduce other significant noise sources to the
amplifier. Each resistor is a noise source. Attention to the
following areas is critical to maintain low noise performance:
design, layout, and component selection. A summary of noise

performance for the amplifier and associated resistors is shown
in Table 8.

CIRCUIT CONSIDERATIONS

Careful and deliberate attention to detail when laying out the
ADA4898 board yields optimal performance. Power supply
bypassing, parasitic capacitance, and component selection all
contribute to the overall performance of the amplifier.

PCB LAYOUT

Because the ADA4898 has a small signal bandwidth of 65 MHz, it
is essential that high frequency board layout techniques be
employed. All ground and power planes under the pins of the
ADA4898 should be cleared of copper to prevent the formation of
parasitic capacitance between the input pins to ground and the
output pins to ground. A single mounting pad on a SOIC
footprint can add as much as 0.2 pF of capacitance to ground if
the ground plane is not cleared from under the mounting pads.

POWER SUPPLY BYPASSING

Power supply bypassing for the ADA4898 has been optimized
for frequency response and distortion performance. Figure 47
shows the recommended values and location of the bypass
capacitors. Power supply bypassing is critical for stability,
frequency response, distortion, and PSR performance. The 0.1 µF
capacitors shown in Figure 47 should be as close to the supply
pins of the ADA4898 as possible. The 10 µF electrolytic
capacitors should be adjacent to, but not necessarily close to,
the 0.1 µF capacitors. The capacitor between the two supplies
helps improve PSR and distortion performance. In some cases,
additional paralleled capacitors can help improve frequency
and transient response.

GROUNDING

Ground and power planes should be used where possible. Ground
and power planes reduce the resistance and inductance of the
power planes and ground returns. The returns for the input
and output terminations, bypass capacitors, and R
be kept as close to the ADA4898 as possible. The output load
ground and the bypass capacitor grounds should be returned to
the same point on the ground plane to minimize parasitic trace
inductance, ringing, and overshoot and to improve distortion
performance.

The ADA4898 package features an exposed paddle. For optimum
electrical and thermal performance, solder this paddle to a nega­tive supply plane.

should all

G

Rev. D | Page 16 of 20

Data Sheet ADA4898-1/ADA4898-2

OUTLINE DIMENSIONS

FOR PROPE R CO NNE CTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DES CRIPTIONS
SECTION O F THIS DATA SHEET.

2.29 (0.090)

4.00 (0.157)

3.90 (0.154)

3.80 (0.150)

5.00 (0.197)

4.90 (0.193)

4.80 (0.189)

85

TOP VIEW

41

6.20 (0.244)

6.00 (0.236)

5.80 (0.228)

2.29 (0.090)

1.75 (0.069)

1.35 (0.053)

0.10 (0.004)
MAX

COPLANARITY

0.10

Figure 50. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]

4.00 (0.157)

3.90 (0.154)

3.80 (0.150)

1.75 (0.069)

1.35 (0.053)

0.10 (0.004)
MAX

COPLANARITY

0.10

1.27 (0.05)
BSC

1.65 (0.065)

1.25 (0.049)

SEATING

0.51 (0.020)

0.31 (0.012)

CONTROLLING DIME NSIONS ARE IN MILLIME TER; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER E QUIVALENTS FOR
REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

PLANE

COMPLIANT TO JE DE C S TANDARDS MS-012-A A

BOTTOM VIEW

0.25 (0.0098)

0.17 (0.0067)

(PINS UP)

8°
0°

0.50 (0.020)

0.25 (0.010)

45°

1.27 (0.050)

0.40 (0.016)

(RD-8-1)

Dimensions shown in millimeters and (inches)

5.00 (0.197)

4.90 (0.193)

4.80 (0.189)

85

TOP VIEW

1.27 (0.05)
BSC

0.51 (0.020)

0.31 (0.012)

6.20 (0.244)

6.00 (0.236)

41

5.80 (0.228)

1.65 (0.065)

1.25 (0.049)

SEATING
PLANE

3.098 (0.122)

BOTTOM VIEW

0.25 (0.0098)

0.17 (0.0067)

(PINS UP)

8°
0°

FOR PROPER CONNE CT I O N O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DES CRIPTIONS
SECTION O F THIS DATA SHEET.

2.41 (0.095)

0.50 (0.020)

0.25 (0.010)

45°

1.27 (0.050)

0.40 (0.016)

07-28-2008-A

CONTROLL ING DIMENSIONS ARE IN MILLIME TER; INCH DIMENS IONS
(IN PARENTHESES) ARE ROUNDED-OF F MILL IMETER EQ UIVALENTS FO R
REFERENCE ONLYAND ARE NOT APPROPRI ATE FOR USE IN DESI GN.

COMPLIANT TO JEDEC STANDARDS MS-012-AA

07-28-2008-A

Figure 51. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]

(RD-8-2)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option Ordering Quantity

ADA4898-1YRDZ −40°C to +105°C 8-Lead SOIC_N_EP RD-8-1 98
ADA4898-1YRDZ-R7 −40°C to +105°C 8-Lead SOIC_N_EP RD-8-1 1,000
ADA4898-1YRDZ-RL −40°C to +105°C 8-Lead SOIC_N_EP RD-8-1 2,500
ADA4898-2YRDZ −40°C to +105°C 8-Lead SOIC_N_EP RD-8-2 98
ADA4898-2YRDZ-R7 −40°C to +105°C 8-Lead SOIC_N_EP RD-8-2 1,000
ADA4898-2YRDZ-RL −40°C to +105°C 8-Lead SOIC_N_EP RD-8-2 2,500
ADA4898-1YRD-EBZ Evaluation Board
ADA4898-2YRD-EBZ Evaluation Board

1

Z = RoHS Compliant Part.

Rev. D | Page 17 of 20

ADA4898-1/ADA4898-2 Data Sheet

NOTES

Rev. D | Page 18 of 20

Data Sheet ADA4898-1/ADA4898-2

NOTES

Rev. D | Page 19 of 20

ADA4898-1/ADA4898-2 Data Sheet

©2008-2012 Analog Devices, Inc. All rights reserved. Trademarks and

NOTES

registered trademarks are the property of their respective owners.
D07037-0-5/12(D)

Rev. D | Page 20 of 20