Datasheet ADA4898-1YRDZ, ADA4898 Datasheet (Analog Devices)

High Voltage, Low Noise, Low Distortion,

Unity Gain Stable, High Speed Op Amp

ADA4898-1

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

FEATURES

Ultralow noise

0.9 nV/√Hz

2.4 pA/√Hz

1.2 nV/√Hz @10 Hz
Ultralow distortion: −93 dBc at 500 kHz
Wide supply voltage range: ±5 V to ±16 V
High speed

−3 dB bandwidth: 65 MHz (G = +1)

Slew rate: 55 V/µs
Unity gain stable
Low input offset voltage: 150 µV maximum
Low input offset voltage drift: 1 V/°C
Low input bias current: −0.1 µA
Low input bias current drift: 2 nA/°C
Supply current: 8 mA
Power-down feature

APPLICATIONS

Instrumentation
Active filters
DAC buffers
SAR ADC drivers
Optoelectronics

CONNECTION DIAGRAM

NC

1

–IN

2

+IN

3

–V

S

4

PD

8

+V

S

7

OUT

6

NC

5

NC = NO CONNECT

ADA4898-1

07037-001

Figure 1. 8-Lead SOIC_N_EP (RD-8)

GENERAL DESCRIPTION

The ADA4898-1 is an ultralow noise and distortion, unity gain
stable, voltage feedback op amp that is ideal for use in 16-bit
and 18-bit systems with power supplies from ±5 V to ±16 V.
The ADA4898-1 features a linear, low noise input stage and internal
compensation that achieves high slew rates and low noise.

With the wide supply voltage range, low offset voltage, and wide
bandwidth, the ADA4898-1 is designed to work in the most
demanding applications. The ADA4898-1 also features an input
bias current cancellation mode that reduces input bias current
by a factor of 60.

The ADA4898-1 is available in an 8-lead SOIC package that
features an exposed metal paddle on its underside that improves
heat transfer to the ground plane. This is a significant improvement
over traditional plastic packages. The ADA4898-1 is rated to
work over the extended automotive temperature range of

−40°C to +105°C.

07037-002

FREQUENCY (Hz)

VOLTAGE NOISE (nV/√Hz)

CURRENT NOISE (p A/√Hz)

1

0.1

1

10

0.1

1

10

10 100 1k 10k 100k

CURRENT

VOLTAGE

Figure 2. Input Voltage Noise and Current Noise vs. Frequency

ADA4898-1

Rev. 0 | Page 2 of 16

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Connection Diagram .......................................................................1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications with ±15 V Supply................................................... 3

Specifications with ±5 V Supply..................................................... 4

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

Maximum Power Dissipation .....................................................5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics............................................. 7

Test C irc uits ..................................................................................... 12

Theory of Operation ...................................................................... 13

PD

(Power Down) Pin............................................................... 13

Current Noise Measurement .................................................... 13

Applications Information.............................................................. 14

Higher Feedback Gain Operation............................................ 14

Recommended Values for Various Gains................................ 14

Noise ............................................................................................ 15

Circuit Considerations .............................................................. 15

PCB Layout ................................................................................. 15

Power Supply Bypassing............................................................ 15

Grounding................................................................................... 15

Outline Dimensions .......................................................................16

Ordering Guide .......................................................................... 16

REVISION HISTORY

5/08—Revision 0: Initial Release

ADA4898-1

Rev. 0 | Page 3 of 16

SPECIFICATIONS WITH ±15 V SUPPLY

TA = 25°C, G = +1, RF = 0 Ω, RG open, RL = 1 kΩ to GND (for G > 1, RF = 100 Ω), unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth V

OUT

= 100 mV p-p 65 MHz

V

OUT

= 2 V p-p 14 MHz

Bandwidth for 0.1 dB Flatness G = +2, V

OUT

= 2 V p-p 3.3 MHz

Slew Rate V

OUT

= 5 V step 55 V/μs

Settling Time to 0.1% V

OUT

= 5 V step 85 ns

NOISE/DISTORTION PERFORMANCE

Harmonic Distortion SFDR f = 100 kHz, V

OUT

= 2 V p-p −116 dBc

f = 500 kHz, V

OUT

= 2 V p-p −93 dBc

f = 1 MHz, V

OUT

= 2 V p-p −79 dBc
Input Voltage Noise f = 100 kHz 0.9 nV/√Hz
Input Current Noise f = 100 kHz 2.4 pA/√Hz

DC PERFORMANCE

Input Offset Voltage 20 110 μV
Input Offset Voltage Drift 1 μV/°C
Input Bias Current

−0.1 −0.4 μA
Input Bias Offset Current 0.03 0.3 μA
Input Bias Current Drift 2 nA/°C
Open-Loop Gain V

OUT

= ±5 V 99 103 dB

INPUT CHARACTERISTICS

Input Resistance Differential mode 5 kΩ
Common mode 30 MΩ
Input Capacitance Differential mode 0.8 pF
Common mode 2.2 pF
Input Common-Mode Voltage Range ±11 V
Common-Mode Rejection Ratio VCM = ±2 V −103 −126 dB

PD (Power Down) PIN

PD Input Voltages

Chip powered down ≤−14 V
Chip enabled ≥−13 V
Input Leakage Current

PD = +VS

−0.1 μA

PD = −VS

−0.2 μA

OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 1 kΩ −11.4 to +12.1 −11.7 to +12.2 V
R

L

= None ±12.76 ±12.82 V
Short-Circuit Current Sinking/sourcing 150 mA
Off Isolation

f = 1 MHz,

PD = −V

S

80 dB

POWER SUPPLY

Operating Range ±4.5 ±16.5 V
Quiescent Current

PD = +V

S

8.1 mA

PD = −V

S

0.1 mA
Positive Power Supply Rejection Ratio +VS = 15 V to 17 V, −VS = −15 V −98 −107 dB
Negative Power Supply Rejection Ratio +VS = 15 V, −VS = −15 V to −17 V −100 −114 dB

ADA4898-1

Rev. 0 | Page 4 of 16

SPECIFICATIONS WITH ±5 V SUPPLY

TA = 25°C, G = +1, RF = 0 Ω, RG open, RL = 1 kΩ to GND (for G > 1, RF = 100 Ω), unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth V

OUT

= 100 mV p-p 57 MHz

V

OUT

= 2 V p-p 12 MHz

Bandwidth for 0.1 dB Flatness G = +2, V

OUT

= 2 V p-p 3 MHz

Slew Rate V

OUT

= 2 V step 50 V/μs

Settling Time to 0.1% V

OUT

= 2 V step 90 ns

NOISE/DISTORTION PERFORMANCE

Harmonic Distortion SFDR f = 500 kHz, V

OUT

= 2 V p-p −95 dBc

f = 1 MHz, V

OUT

= 2 V p-p −78 dBc
Input Voltage Noise f = 100 kHz 0.9 nV/√Hz
Input Current Noise f = 100 kHz 2.4 pA/√Hz

DC PERFORMANCE

Input Offset Voltage 30 150 μV
Input Offset Voltage Drift 1 μV/°C
Input Bias Current −0.1 −0.4 μA
Input Bias Offset Current 0.01 0.3 μA
Input Bias Current Drift 2 nA/°C
Open-Loop Gain V

OUT

= ±1 V 90 94 dB

INPUT CHARACTERISTICS

Input Resistance Differential mode 5 kΩ
Common mode 30 MΩ
Input Capacitance Differential mode 0.8 pF
Common mode 2.2 pF
Input Common-Mode Voltage Range −3 to +2.5 V
Common-Mode Rejection Ratio VCM = ±1 V −102 −120 dB

PD (Power Down) PIN

PD Input Voltages

Chip powered down ≤−4 V
Chip enabled ≥−3 V
Input Leakage Current

PD = +VS

0.1 μA

PD = −VS

−2 μA

OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 1 kΩ ±3.12 ±3.17 V
R

L

= None ±3.3 ±3.34 V
Short-Circuit Current Sinking/sourcing 150 mA
Off Isolation

f = 1 MHz,

PD = −V

S

80 dB

POWER SUPPLY

Operating Range ±4.5 ±16.5 V
Quiescent Current

PD = +V

S

7.7 mA

PD = −V

S

0.1 mA
Positive Power Supply Rejection Ratio +VS = 5 V to 7 V, −VS = −5 V −95 −100 dB
Negative Power Supply Rejection Ratio +VS = 5 V, −VS = −5 V to −7 V −97 −104 dB

ADA4898-1

Rev. 0 | Page 5 of 16

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage 36 V
Power Dissipation See Figure 3
Differential Mode Input Voltage ±1.5 V
Common-Mode Input Voltage ±11.4 V
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +105°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in the circuit board with its
exposed paddle soldered to a pad on the PCB surface that is
thermally connected to a copper plane, with zero airflow.

Table 4.

Package Type θJAθJCUnit

8-Lead SOIC with EP on Four-Layer Board 47 29

°C/W

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the ADA4898-1
package is limited by the associated rise in junction temperature
(T

J

) on the die. At approximately 150°C, which is the glass
transition temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the ADA4898-1. Exceeding a
junction temperature of 150°C for an extended period can
result in changes in the silicon devices, potentially causing
failure.

The power dissipated in the package (P

D

) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the output load drive. The quiescent power is
the voltage between the supply pins (V

S

) times the quiescent

current (I

S

). The power dissipated due to the load drive depends
upon the particular application. For each output, the power due
to load drive is calculated by multiplying the load current by the
associated voltage drop across the device. RMS voltages and
currents must be used in these calculations.

Airflow increases heat dissipation, effectively reducing θ

JA

. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θ

JA

. The exposed paddle on the underside of the
package must be soldered to a pad on the PCB surface that is
thermally connected to a copper plane to achieve the specified θ

JA

.

Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC_EP
(47°C/W) on a JEDEC standard four-layer board, with its
underside paddle soldered to a pad that is thermally connected
to a PCB plane. θ

JA

values are approximations.

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

07037-003

AMBIENT TEMPERATURE (°C)

MAXIMUM POWER DISSIPATIO N (W)

0 2040608010010 30 50 70 90–40 –20–30 –10

Figure 3. Maximum Power Dissipation vs. Ambient Temperature

ESD CAUTION

ADA4898-1

Rev. 0 | Page 6 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NC

1

–IN

2

+IN

3

–V

S

4

PD

8

+V

S

7

OUT

6

NC

5

NC = NO CONNECT

ADA4898-1

TOP VIEW

(Not to Scale)

07037-046

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 NC No Connect
2 −IN Inverting Input
3 +IN Noninverting Input
4 −V

S

Negative Supply
5 NC No Connect
6 OUT Output
7 +V

S

Positive Supply
8

PD

Power Down

ADA4898-1

Rev. 0 | Page 7 of 16

TYPICAL PERFORMANCE CHARACTERISTICS

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

3

1 10 100

07037-004

FREQUENCY (MHz)

NORMALIZE D CLOSED-LO OP GAIN (dB)

RL = 1kΩ
V

OUT

= 100mV p-p

V

S

= ±15V

G = +1

R

F

= 0Ω

G = +1

R

F

= 100Ω

G = +2

R

F

= 100Ω

G = +5

R

F

= 100Ω

Figure 5. Small Signal Frequency Response for Various Gains

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

3

1 10 100

07037-005

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

RL = 1kΩ

RL = 100Ω

RL = 200Ω

G = +1
V

OUT

= 100mV p-p

V

S

= ±15V

Figure 6. Small Signal Frequency Response for Various Loads

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

1 10 100

07037-006

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

T = +25°C

G = +1
R

L

= 1kΩ

V

OUT

= 100mV p-p

V

S

= ±15V

T = +105°C T = +85°C

T = –40°C

T = 0°C

Figure 7. Small Signal Frequency Response for Various Temperatures

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

3

1 10 100

07037-007

FREQUENCY (MHz)

NORMALIZED CL OSED-LO OP GAIN (d B)

RL = 1kΩ
V

OUT

= 2V p-p

V

S

= ±15V

G = +1

R

F

= 0Ω

G = +1

R

F

= 100Ω

G = +5

R

F

= 100Ω

G = +2

R

F

= 100Ω

Figure 8. Large Signal Frequency Response for Various Gains

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

1 10 100

07037-008

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

RL = 1kΩ

RL = 100Ω

G = +1
V

OUT

= 2V p-p

V

S

= ±15V

RL = 200Ω

Figure 9. Large Signal Frequency Response for Various Loads

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

1 10 100

07037-009

FREQUENCY (MHz)

CLOSED-LOOP GAIN (dB)

G = +1
R

L

= 1kΩ

V

OUT

= 2V p-p

V

S

= ±15V

T = +85°C

T = –40°C

T = +105°C

T = +25°C

T = 0°C

Figure 10. Large Signal Frequency Response for Various Temperatures

ADA4898-1

Rev. 0 | Page 8 of 16

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

110

07037-010

FREQUENCY (M Hz)

CLOSED-LOOP GAIN (dB)

100

G = +1
R

L

= 1kΩ

V

OUT

= 100mV p-p

V

S

= ±15V

VS = ±5V

Figure 11. Small Signal Frequency Response for Various Supply Voltages

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

3

110

07037-011

FREQUENCY (M Hz)

CLOSED-LOOP GAIN (dB)

100

G = +1
R

L

= 1kΩ

V

OUT

= 100mV p-p

V

S

= ±15V

CL = 33pF

C

L

= 15pF

CL = 5pF

CL = 0pF

Figure 12. Small Signal Frequency Response for Various Capacitive Loads

0.1

1

10

1 10 100 1k 10k 100k

07037-012

FREQUENCY (Hz)

VOLTAGE NOIS E (nV/√Hz)

Figure 13. Voltage Noise vs. Frequency

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

110

07037-013

FREQUENCY (M Hz)

CLOSED-LOOP GAIN (dB)

100

VS = ±15V

G = +1
R

L

= 1kΩ

V

OUT

= 2V p-p

VS = ±5V

Figure 14. Large Signal Frequency Response for Various Supply Voltages

–0.5

–0.4

–0.3

–0.2

–0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

100k 1M 10M

7037-014

FREQUENCY (Hz)

NORMALIZE D GAIN (dB)

G = +2
R

L

= 1kΩ

V

S

= ±15V

V

OUT

= 2V p-p

V

OUT

= 0.1V p-p

Figure 15. 0.1 dB Flatness for Various Output Voltages

07037-035

FREQUENCY (Hz)

CURRENT NOISE ( pA/√Hz)

1

1

10

100

10 100 1k 10k 100k

Figure 16. Input Current Noise vs. Frequency

ADA4898-1

Rev. 0 | Page 9 of 16

–20

–10

0

10

20

30

40

50

60

70

80

110

90

100

07037-016

FREQUENCY (Hz)

OPEN-LOOP GAIN (dB)

100k 1M 1G10M 100M

PHASE

GAIN

–

70

–80

–90

–100

–110

–120

–130

–140

–150

–160

–170

–180

–190

–200

OPEN-LO OP PHASE (Degrees)

Figure 17. Open-Loop Gain and Phase vs. Frequency

07037-017

FREQUENCY (Hz)

DISTORT ION (dBc)

–140

–120

–100

–80

–60

–40

–20

0

100k 1M 10M

G = +1, HD2

G = +1, HD3

G = +2, HD3, R

F

= 250Ω

G = +2, HD2, R

F

= 250Ω

RL = 1kΩ
V

S

= ±15V

V

OUT

= 2V p-p

Figure 18. Harmonic Distortion vs. Frequency and Gain

07037-018

FREQUENCY (Hz)

DISTORTI ON (dBc)

–140

–120

–100

–80

–60

–40

–20

0

100k 1M 10M

RL = 1kΩ, HD3

R

L

= 100Ω, HD3

G = +1
V

S

= ±15V

V

OUT

= 2V p-p

RL = 1kΩ, HD2

RL = 100Ω, HD2

Figure 19. Harmonic Distortion vs. Frequency and Loads

1

07073-019

OUTPUT VOLTAGE (V p-p)

DISTORTION (dBc)

–135

–125

–120

–130

–115

–110

–105

–100

–

95

23456

HD2

HD3

f = 100kHz
G = +1
R

L

= 1kΩ

V

S

= ±15V

Figure 20. Harmonic Distortion vs. Output Amplitude

07037-020

FREQUENCY (Hz)

DISTORTION (dBc)

–140

–120

–100

–80

–60

–40

–20

0

100k 1M 10M

RL = 1kΩ, HD3

R

L

= 100Ω, HD3

R

L

= 100Ω, HD2

G = +1
V

S

= ±5V

V

OUT

= 2V p-p

RL = 1kΩ, HD2

Figure 21. Harmonic Distortion vs. Frequency and Loads

–0.04

–0.02

0

0.02

0.04

0.06

0.08

0.10

0.12

0.14

CL = 0pF

C

L

= 5pF

CL = 15pF

CL = 33pF

07037-021

TIME (20n s/DIV)

OUTPUT VO LTAGE ( V)

V

OUT

= 100mV p-p
G = +1
R

L

= 1kΩ

V

S

= ±15V

Figure 22. Small Signal Transient Response for Various Capacitive Loads

ADA4898-1

Rev. 0 | Page 10 of 16

G = +1

G = +2

–0.04

–0.02

0

0.02

0.04

0.06

0.08

0.10

0.12

0.14

07037-022

TIME (20n s/DIV)

OUTPUT VOLTAGE (V)

V

OUT

= 100mV p-p

R

L

=1kΩ

V

S

= ±15V

Figure 23. Small Signal Transient Response for Various Gains

–0.5

0

0.5

1.0

1.5

2.0

2.5

VS = ±15V

V

S

= ±5V

07037-023

TIME (1 00ns/DIV)

OUTPUT VOLTAGE (V)

V

OUT

= 2V p-p
G = +1
R

L

= 100Ω

Figure 24. Large Signal Transient Response for

Various Supply Voltages, R

L

= 100 Ω

INPUT

0.5

0.4

0.3

0.2

0.1

0

0.1

0.2

0.3

0.4

0.5

07037-026

TIMES ( 10ns/DIV)

SETTLING TIME (%)

G = +1
R

L

= 1kΩ

V

OUT

= 5V p-p

V

S

= ±15V

Δt = 85ns

OUTPUT

Figure 25. Settling Time

–0.5

0

0.5

1.0

1.5

2.0

2.5

07037-025

TIME (100n s/DIV)

OUTPUT VO LTAGE (V)

V

OUT

= 2V p-p
G = +1
R

L

= 1kΩ

VS = ±15V

V

S

= ±5V

Figure 26. Large Signal Transient Response for

Various Supply Voltages, R

L

= 1 kΩ

–0.5

0

0.5

1.0

1.5

2.0

2.5

G = +1

07037-024

TIME (1 00ns/DIV)

OUTPUT VO LTAGE (V )

V

OUT

= 2V p-p

R

L

= 1kΩ

V

S

= ±15V

G = +2

Figure 27. Large Signal Transient Response for Various Gains

–20

–10

0

10

20

30

40

50

60

70

80

90

07037-028

FREQUENCY (Hz)

OUTPUT IMPE DANCE (d B)

100k 1M 1G10M 100M

V

OUT

= 0.1V p-p

DISABLED

G = +1
R

F

= 0Ω

R

L

= 0Ω

V

S

= ±15V

V

OUT

= 2V p-p

ENABLED

V

OUT

= 2V p-p

DISABLED

V

OUT

= 0.1V p-p

ENABLED

Figure 28. Output Impedance vs. Frequency

ADA4898-1

Rev. 0 | Page 11 of 16

–140

–120

–100

–80

–60

–40

–20

0

07037-029

FREQUENCY (Hz)

CMRR (dB)

100 1M 100M10M1k 100k10k

G = +1
R

L

= 100Ω

V

S

= ±15V

V

OUT

= 2V p-p

–120

–100

–80

–60

–40

–20

0

07037-030

FREQUENCY (Hz)

PSRR (dB)

10k 100k 1M 10M

G = +1
R

L

= 100Ω

V

S

= ±15V

V

OUT

= 2V p-p

+PSRR

–PSRR

Figure 29. Common-Mode Rejection Ratio (CMRR) vs. Frequency

Figure 32. Power Supply Rejection Ratio (PSRR) vs. Frequency

–75

–65

–55

–

45

100k 1M 10M 100M

V

OUT

= 0.1V p-p

07037-031

FREQUENCY (Hz)

PD ISOLATION (dB)

G = +1
R

L

= 1kΩ

V

S

= ±15V

V

OUT

= 2V p-p

1000

800

600

400

200

0

07037-032

INPUT BIAS CURRENT (µA)

COUNT

–0.15–0.20–0.25 –0. 10 0–0.05

N = 6180
MEAN: –0.13
SD: 0.02
V

S

= ±15V

Figure 33.

PD

Isolation vs. Frequency

Figure 30. Input Bias Current Distribution

1000

800

600

400

200

0

07037-033

OFFSET VOLTAGE (µV)

COUNT

0–30–60 30 1209060

N = 6180
MEAN: 27
SD: 20
V

S

= ±15V

1000

800

600

400

200

0

OFFSET VOLTAGE (µV)

COUNT

N = 6180
MEAN: –2.8
SD: 20
V

S

= ±5V

07037-034

0–30–60 30 9060–90

Figure 31. Input Offset Voltage Distribution, V

S

= ±15 V

Figure 34. Input Offset Voltage Distribution, V

S

= ±5 V

ADA4898-1

Rev. 0 | Page 12 of 16

TEST CIRCUITS

V

IN

V

OUT

0.1µF

0.1µF

0.1µF

10µF

+

V

S

–V

S

49.9Ω

07037-036

R

L

+

10µF

+

Figure 35. Typical Noninverting Load Configuration

V

OUT

0.1µF

49.9Ω

+

V

S

–V

S

07037-037

R

L

10µF

+

AC

Figure 36. Positive Power Supply Rejection

V

IN

V

OUT

0.1µF

0.1µF

0.1µF

10µF

+

V

S

–V

S

1kΩ

1kΩ

1kΩ

1kΩ

07037-038

53.6Ω

R

L

+

10µF

+

Figure 37. Common-Mode Rejection

V

IN

V

OUT

0.1µF

0.1µF

0.1µF

10µF

+

V

S

–V

S

R

G

R

F

49.9Ω

07037-039

R

L

C

L

+

10µF

+

Figure 38. Typical Capacitive Load Configuration

0.1µF

V

OUT

+

V

S

–V

S

07037-040

R

L

10µF

+

AC

49.9Ω

Figure 39. Negative Power Supply Rejection

ADA4898-1

Rev. 0 | Page 13 of 16

THEORY OF OPERATION

The ADA4898-1 is a voltage feedback op amp that combines
unity-gain stability with 0.9 nV/√Hz input noise. It employs a
highly linear input stage that can maintain greater than −90 dBc
(@ 2 V p-p) distortion out to 500 kHz while in a unity-gain
configuration. This rare combination of low gain stability, low
input referred noise, and extremely low distortion is the result
of Analog Devices, Inc., proprietary op amp architecture and
high speed complementary bipolar processing technology.

The simplified ADA4898-1 topology, shown in

Figure 40, is a
single gain stage with a unity-gain output buffer. It has over 100 dB
of open-loop gain and maintains precision specifications such
as CMRR, PSRR and offset to levels that are normally associated
with topologies having two or more gain stages.

BUFFERg

m

C

C

R1

R

L

V

OUT

07037-041

Figure 40. Topology

PD (POWER DOWN) PIN

The PD pin saves power by decreasing the quiescent power
dissipated in the device. It is very useful when power is an issue
and the device does not need to be turned on at all times. The
response of the device is rapid when going from a power down
mode to full power operation mode. Note that

PD

does not put the
output in a high-Z state, which means that the ADA4898-1 is
not recommended for use as a multiplexer.

CURRENT NOISE MEASUREMENT

To measure the very low (2.4 pA/√Hz) input current noise of
the ADA4898-1, 10 kΩ resistors were used on both inputs of the
amplifier.

Figure 41 shows the noise measurement circuit used.
The 10 kΩ resistors are used on both inputs to balance the input
impedance and cancel the common-mode noise. In addition, a
high gain configuration is used to increase the total output noise
and bring it above the noise floor of the instrument.

07037-042

100

Ω

10Ω

10kΩ

10kΩ

V

OUT

Figure 41. Current Noise Measurement Circuit

The current noise density (In) is calculated using the following
formula:

[

]

11k20

2)HznV/18.4(11

2/1

2

2

×

××−

=

no

n

e

I

ADA4898-1

Rev. 0 | Page 14 of 16

APPLICATIONS INFORMATION

HIGHER FEEDBACK GAIN OPERATION

The ADA4898-1 schematic for the noninverting gain
configuration is nearly a textbook example (see

Figure 42).
The only exception is the feedback capacitor in parallel with
the feedback resistor, R

F

, but this capacitor is recommended

only when using a large R

F

value (>300 Ω). Figure 43 shows the
difference between using a 100 Ω resistor and a 1 kΩ resistor.
Due to the high input capacitance in the ADA4898-1 when
using a higher feedback resistor, more peaking appears in the
closed-loop gain. Using the lower feedback resistor resolves this
issue; however, when running at higher supplies (±15 V) with
100 Ω R

F

, the system draws a lot of extra current into the
feedback network. To avoid this problem, a higher feedback
resistor can be used with a feedback capacitor in parallel.

Figure 43
shows the effect of placing a feedback capacitor in parallel with
a larger R

F

. In this gain of 2 configuration, RF = RG = 1 kΩ and

C

F

= 2.7 pF. When using CF, the peaking drops from 6 dB to less

then 2 dB.

07037-043

V

IN

V

OUT

0.1µF

0.1µF

0.1µF

10µF

+V

S

–V

S

R

T

R

L

+

10µF

+

C

F

R

F

R

F

Figure 42. Noninverting Gain Schematic

–15

–12

–9

–6

–3

0

3

6

9

12

07037-044

FREQUENCY (Hz)

CLOSED-LOOP GAIN (dB)

100k 10M1M 100M

RF = 1kΩ, CF = 2.7pF

R

F

= 1kΩ

RF = 100Ω

G = +2
R

L

= 1kΩ

V

S

= ±15V

Figure 43. Small Signal Frequency R esponse for

Various Feedback Impedances

RECOMMENDED VALUES FOR VARIOUS GAINS

Table 6 provides a useful reference for determining various gains
and associated performance. Resistor R

F

is set to 100 Ω for gains

greater than 1. A low feedback R

F

resistor value reduces peaking
and minimizes the contribution to the overall noise performance
of the amplifier.

Table 6. Various Gains and Recommended Resistor Values Associated (Conditions: VS = ±5 V, TA = 25°C, RL = 1 kΩ, RT = 49.9 Ω)

Gain RF (Ω) RG (Ω)

−3 dB SS BW (MHz),
V

OUT

= 100 mV p-p

Slew Rate (V/µs),
V

OUT

= 2 V Step

ADA4898-1 Voltage
Noise (nV/√Hz), RTO

Total System Noise
(nV/√Hz), RTO

+1 0 NA 65 55 0.9 1.29
[phone] 1.8 3.16
+5 100 24.9 9 45 4.5 7.07

ADA4898-1

Rev. 0 | Page 15 of 16

NOISE

To analyze the noise performance of an amplifier circuit,
identify the noise sources, and then determine if each source
has a significant contribution to the overall noise performance
of the amplifier. To simplify the noise calculations, noise spectral
densities were used rather than actual voltages to leave bandwidth
out of the expressions (noise spectral density, which is generally
expressed in nV/

√Hz, is equivalent to the noise in a 1 Hz

bandwidth).

The noise model shown in

Figure 44 has six individual noise
sources: the Johnson noise of the three resistors, the op amp
voltage noise, and the current noise in each input of the amplifier.
Each noise source has its own contribution to the noise at the
output. Noise is generally specified referred to input (RTI), but
it is often simpler to calculate the noise referred to the output
(RTO) and then divide by the noise gain to obtain the RTI noise.

GAIN FROM

B TO OUTP UT

= –

R2

R1

GAIN FROM

A TO OUTP UT

=

NOISE GAIN =

NG = 1 +

R2

R1

I

N–

V

N

V

N, R1

V

N, R3

R1

R2

I

N+

R3

4kTR2

4kTR1

4kTR3

V

N, R2

B

A

V

N

2

+ 4kTR3 + 4kTR1

R2

2

R1 + R2

I

N+

2

R32 + I

N–

2

R1 × R2

2

+ 4kTR2

R1

2

R1 + R2 R1 + R2

RTI NOIS E =

RTO NOIS E = NG × RTI NOISE

V

OUT

+

7037-045

Figure 44. Op Amp Noise Analysis Model

All resistors have a Johnson noise that is calculated by

)(4kBTR .

where:

k is Boltzmann’s Constant (1.38 × 10

−23

J/K).

B is the bandwidth in Hertz.
T is the absolute temperature in Kelvin.
R is the resistance in ohms.

A simple relationship that is easy to remember is that a 50 Ω
resistor generates a Johnson noise of 1 nV/√Hz at 25°C.

In applications where noise sensitivity is critical, care must be
taken not to introduce other significant noise sources to the
amplifier. Each resistor is a noise source. Attention to the
following areas is critical to maintain low noise performance:
design, layout, and component selection. A summary of noise
performance for the amplifier and associated resistors can be
seen in

Table 6.

CIRCUIT CONSIDERATIONS

Careful and deliberate attention to detail when laying out the
ADA4898-1 board yields optimal performance. Power supply
bypassing, parasitic capacitance, and component selection all
contribute to the overall performance of the amplifier.

PCB LAYOUT

Because the ADA4898-1 can operate up to 65 MHz, it is
essential that RF board layout techniques be employed. All
ground and power planes under the pins of the ADA4898-1
should be cleared of copper to prevent the formation of parasitic
capacitance between the input pins to ground and the output pins
to ground. A single mounting pad on a SOIC footprint can add
as much as 0.2 pF of capacitance to ground if the ground plane
is not cleared from under the mounting pads.

POWER SUPPLY BYPASSING

Power supply bypassing for the ADA4898-1 has been optimized
for frequency response and distortion performance.

Figure 42
shows the recommended values and location of the bypass
capacitors. Power supply bypassing is critical for stability,
frequency response, distortion, and PSR performance. The

0.1 µF capacitors shown in

Figure 42 should be as close to the
supply pins of the ADA4898-1 as possible. The 10 µF electrolytic
capacitors should be adjacent to but not necessary close to the

0.1 µF capacitors. The capacitor between the two supplies helps
improve PSR and distortion performance. In some cases, additional
paralleled capacitors can help improve frequency and transient
response.

GROUNDING

Ground and power planes should be used where possible. Ground
and power planes reduce the resistance and inductance of the
power planes and ground returns. The returns for the input
and output terminations, bypass capacitors, and R

G

should all
be kept as close to the ADA4898-1 as possible. The output load
ground and the bypass capacitor grounds should be returned to
the same point on the ground plane to minimize parasitic trace
inductance, ringing, and overshoot and to improve distortion
performance.

The ADA4898-1 package features an exposed paddle. For
optimum electrical and thermal performance, solder this paddle to
ground. For more information on high speed circuit design, see

A Practical Guide to High-Speed Printed-Circuit-Board Layout at

www.analog.com.

ADA4898-1

Rev. 0 | Page 16 of 16

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MS-012-A A

CONTROLL ING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE IN DESI GN.

060506-A

0.25 (0.0098)

0.17 (0.0067)

1.27 (0.050)

0.40 (0.016)

0.50 (0.020)

0.25 (0.010)

45°

8°
0°

1.75 (0.069)

1.35 (0.053)

1.65 (0.065)

1.25 (0.049)

SEATING
PLANE

85

41

5.00 (0.197)

4.90 (0.193)

4.80 (0.189)

4.00 (0.157)

3.90 (0.154)

3.80 (0.150)

1.27 (0.05)
BSC

6.20 (0.244)

6.00 (0.236)

5.80 (0.228)

0.51 (0.020)

0.31 (0.012)

COPLANARITY

0.10

TOP VIEW

2.29 (0.090)

BOTTOM VIEW

(PINS UP)

2.29 (0.090)

0.10 (0.004)
MAX

Figure 45. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]

(RD-8-1)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Temperature Range Package Description Package Option Ordering Quantity

ADA4898-1YRDZ

1

−40°C to +105°C 8-Lead SOIC_N_EP RD-8-1 1

ADA4898-1YRDZ-R7

1

−40°C to +105°C 8-Lead SOIC_N_EP RD-8-1 1,000

ADA4898-1YRDZ-RL

1

−40°C to +105°C 8-Lead SOIC_N_EP RD-8-1 2,500

1

Z = RoHS Compliant Part.

©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07037-0-5/08(0)