Ultralow Distortion, Low Power,
A
–V
A
–V
A
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FEATURES
High speed
850 MHz, −3 dB bandwidth (G = +1, R
750 MHz, −3 dB bandwidth (G = +1, R
2800 V/μs slew rate
Low distortion: −88 dBc @ 10 MHz (G = +1, R
Low power: 5 mA/amplifier @ 10 V
Low noise: 4.4 nV/√Hz
Wide supply voltage range: 5 V to 10 V
Power-down feature
Available in 3 mm × 3 mm 8-lead LFCSP (single), 8-lead SOIC
(single), and 4 mm × 4 mm 16-lead LFCSP (dual)
APPLICATIONS
Instrumentation
IF and baseband amplifiers
Active filters
ADC drivers
DAC buffers
= 1 kΩ, LFCSP)
L
= 1 kΩ, SOIC)
L
= 1 kΩ)
L
Low Noise, High Speed Op Amp
ADA4857-1/ADA4857-2
CONNECTION DIAGRAMS
DA4857-1
TOP VIEW
(Not to Scale)
1PD
2FB
3–IN
4+IN
NC = NO CONNECT
Figure 1. 8-Lead LFCSP (CP)
DA4857-1
TOP VIEW
(Not to Scale)
1
FB
–IN
2
+IN
3
4
S
NC = NO CONNECT
Figure 2. 8-Lead SOIC (R)
DA4857-2
TOP VIEW
(Not to Scale)
FB1
PD1
16
15
8+V
S
7OUT
6NC
5–V
S
07040-001
8
PD
+V
7
S
OUT
6
NC
5
07040-002
S1
OUT1
+V
14
13
GENERAL DESCRIPTION
The ADA4857 is a unity-gain stable, high speed, voltage feedback
amplifier with low distortion, low noise, and high slew rate. With a
spurious-free dynamic range (SFDR) of −88 dBc @ 10 MHz, the
ADA4857 is an ideal solution for a variety of applications, including
ultrasounds, ATE, active filters, and ADC drivers. The Analog
Devices, Inc., proprietary next-generation XFCB process and
innovative architecture enables such high performance amplifiers.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
1–IN1
2+IN1
3NC
4
S2
5
6
S2
+V
OUT2
NC = NO CONNECT
Figure 3. 16-Lead LFCSP (CP)
12 –V
S1
11 NC
10 +IN2
9–IN2
8
7
FB2
PD2
07040-003
The ADA4857 has 850 MHz bandwidth, 2800 V/μs slew rate, and
settles to 0.1% in 15 ns. With a wide supply voltage range (5 V to
10 V), the ADA4857 is an ideal candidate for systems that require
high dynamic range, precision, and speed.
The ADA4857-1 amplifier is available in a 3 mm × 3 mm, 8-lead
LFCSP and a standard 8-lead SOIC. The ADA4857-2 is available in
a 4 mm × 4 mm, 16-lead LFCSP. The LFCSP features an exposed
paddle that provides a low thermal resistance path to the printed
circuit board (PCB). This path enables more efficient heat transfer
and increases reliability. The ADA4857 works over the extended
industrial temperature range (−40°C to +125°C).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
ADA4857-1/ADA4857-2
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagrams ...................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±5 V Supply ................................................................................... 3
+5 V Supply ................................................................................... 4
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
Maximum Power Dissipation ..................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Test Circuits ..................................................................................... 15
Applications Information .............................................................. 16
Power-Down Operation ............................................................ 16
Capacitive Load Considerations .............................................. 16
Recommended Values for Various Gains ................................ 16
Active Low-Pass Filter (LPF) .................................................... 17
Noise ............................................................................................ 18
Circuit Considerations .............................................................. 18
PCB Layout ................................................................................. 18
Power Supply Bypassing ............................................................ 18
Grounding ................................................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
11/08—Rev. 0 to Rev. A
Changes to Table 5 ............................................................................ 7
Changes to Table 7 ............................................................................ 8
Changes to Figure 32 ...................................................................... 13
Added Figure 44; Renumbered Sequentially .............................. 15
Changes to Layout .......................................................................... 15
Changes to Table 8 .......................................................................... 16
Added Active Low-Pass Filter (LFP) Section .............................. 17
Added Figure 48 and Figure 49; Renumbered Sequentially ..... 17
Changes to Grounding Section ..................................................... 18
Exposed Paddle Notation Added to Outline Dimensions ........ 19
Changes to Ordering Guide .......................................................... 20
5/08—Revision 0: Initial Version
Rev. A | Page 2 of 20
ADA4857-1/ADA4857-2
www.BDTIC.com/ADI
SPECIFICATIONS
±5 V SUPPLY
TA = 25°C, G = +2, RG = RF = 499 Ω, RL = 1 kΩ to ground, PD = no connect, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth (LFCSP/SOIC) G = +1, V
G = +1, V
G = +2, V
Full Power Bandwidth G = +1, V
Bandwidth for 0.1 dB Flatness (LFCSP/SOIC) G = +2, V
Slew Rate (10% to 90%) G = +1, V
Settling Time to 0.1% G = +2, V
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion f = 1 MHz, G = +1, V
f = 1 MHz, G = +1, V
f = 10 MHz, G = +1, V
f = 10 MHz, G = +1, V
f = 50 MHz, G = +1, V
f = 50 MHz, G = +1, V
Input Voltage Noise f = 100 kHz 4.4 nV/√Hz
Input Current Noise f = 100 kHz 1.5 pA/√Hz
DC PERFORMANCE
Input Offset Voltage ±2 ±4.5 mV
Input Offset Voltage Drift 2.3 μV/°C
Input Bias Current
−2 −3.3 μA
Input Bias Current Drift 24.5 nA/°C
Input Bias Offset Current 50 nA
Open-Loop Gain V
OUT
PD (POWER-DOWN) PIN
PD Input Voltage Chip powered down ≥(VCC − 2) V
Chip enabled ≤(VCC − 4.2) V
Turn-Off Time 50% off PD to <10% of final V
Turn-On Time 50% off PD to <10% of final V
PD Pin Leakage Current Chip enabled 58 μA
Chip powered down 80 μA
INPUT CHARACTERISTICS
Input Resistance Common mode 8 MΩ
Differential mode 4 MΩ
Input Capacitance Common mode 2 pF
Input Common-Mode Voltage Range ±4 V
Common-Mode Rejection Ratio VCM = ±1 V −78 −86 dB
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time VIN = ±2.5 V, G = +2 10 ns
Output Voltage Swing RL = 1 kΩ ±4 V
R
= 100 Ω ±3.7 V
L
Output Current 50 mA
Short-Circuit Current Sinking and sourcing 125 mA
Capacitive Load Drive 30% overshoot, G = +2 10 pF
= 0.2 V p-p 650 850/750 MHz
OUT
= 2 V p-p 600/550 MHz
OUT
= 0.2 V p-p 400/350 MHz
OUT
= 2 V p-p, THD < −40 dBc 110 MHz
OUT
= 2 V p-p, RL = 150 Ω 75/90 MHz
OUT
= 4 V step 2800 V/μs
OUT
= 2 V step 15 ns
OUT
= 2 V p-p (HD2) −108 dBc
OUT
= 2 V p-p (HD3) −108 dBc
OUT
= 2 V p-p (HD2) −88 dBc
OUT
= 2 V p-p (HD3) −93 dBc
OUT
= 2 V p-p (HD2) −65 dBc
OUT
= 2 V p-p (HD3) −62 dBc
OUT
= −2.5 V to +2.5 V 57 dB
, VIN = 1 V, G = +2 55 μs
OUT
, VIN = 1 V, G = +2 33 ns
OUT
Rev. A | Page 3 of 20
ADA4857-1/ADA4857-2
www.BDTIC.com/ADI
Parameter Conditions Min Typ Max Unit
POWER SUPPLY
Operating Range 4.5 10.5 V
Quiescent Current 5 5.5 mA
Quiescent Current (Power Down) PD ≥ VCC − 2 V 350 450 μA
Positive Power Supply Rejection +VS = 4.5 V to 5.5 V, −VS = −5 V −59 −62 dB
Negative Power Supply Rejection +VS = 5 V, −VS = −4.5 V to −5.5 V −65 −68 dB
+5 V SUPPLY
TA = 25°C, G = +2, RF = RG = 499 Ω, RL = 1 kΩ to midsupply, PD = no connect, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth (LFCSP/SOIC) G = +1, V
G = +1, V
G = +2, V
Full Power Bandwidth G = +1, V
Bandwidth for 0.1 dB Flatness (LFCSP/SOIC) G = +2, V
Slew Rate (10% to 90%) G = +1, V
Settling Time to 0.1% G = +2, V
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion f = 1 MHz, G = +1, V
f = 1 MHz, G = +1, V
f = 10 MHz, G = +1, V
f = 10 MHz, G = +1, V
f = 50 MHz, G = +1, V
f = 50 MHz, G = +1, V
Input Voltage Noise f = 100 kHz 4.4 nV/√Hz
Input Current Noise f = 100 kHz 1.5 pA/√Hz
DC PERFORMANCE
Input Offset Voltage ±1 ±4.2 mV
Input Offset Voltage Drift 4.6 μV/°C
Input Bias Current
−1.7 −3.3 μA
Input Bias Current Drift 24.5 nA/°C
Input Bias Offset Current 50 nA
Open-Loop Gain V
OUT
PD (POWER-DOWN) PIN
PD Input Voltage Chip powered down ≥(VCC − 2) V
Chip enabled ≤(VCC − 4.2) V
Turn-Off Time 50% off PD to <10% of final V
Turn-On Time 50% off PD to <10% of final V
PD Pin Leakage Current Chip enable 8 μA
Chip powered down 30 μA
INPUT CHARACTERISTICS
Input Resistance Common mode 8 MΩ
Differential mode 4 MΩ
Input Capacitance Common mode 2 pF
Input Common-Mode Voltage Range 1 to 4 V
Common-Mode Rejection Ratio VCM = 2 V to 3 V −76 −84 dB
= 0.2 V p-p 595 800/750 MHz
OUT
= 2 V p-p 500/400 MHz
OUT
= 0.2 V p-p 360/300 MHz
OUT
= 2 V p-p, THD < −40 dBc 95 MHz
OUT
= 2 V p-p, RL = 150 Ω 50/40 MHz
OUT
= 2 V step 1500 V/μs
OUT
= 2 V step 15 ns
OUT
= 2 V p-p (HD2) −92 dBc
OUT
= 2 V p-p (HD3) −90 dBc
OUT
= 2 V p-p (HD2) −81 dBc
OUT
= 2 V p-p (HD3) −71 dBc
OUT
= 2 V p-p (HD2) −69 dBc
OUT
= 2 V p-p (HD3) −55 dBc
OUT
= 1.25 V to 3.75 V 57 dB
, VIN = 1 V, G = +2 38 μs
OUT
, VIN = 1 V, G = +2 30 ns
OUT
Rev. A | Page 4 of 20
ADA4857-1/ADA4857-2
www.BDTIC.com/ADI
Parameter Conditions Min Typ Max Unit
OUTPUT CHARACTERISTICS
Overdrive Recovery Time G = +2 15 ns
Output Voltage Swing RL = 1 kΩ 1 to 4 V
R
Output Current 50 mA
Short-Circuit Current Sinking and sourcing 75 mA
Capacitive Load Drive 30% overshoot, G = +2 10 pF
POWER SUPPLY
Operating Range 4.5 10.5 V
Quiescent Current 4.5 5 mA
Quiescent Current (Power Down) PD ≥ VCC − 2 V 250 350 μA
Positive Power Supply Rejection +VS = 4.5 V to 5.5 V, −VS = 0 V −58 −62 dB
Negative Power Supply Rejection +VS = 5 V, −VS = −0.5 V to +0.5 V −65 −68 dB
= 100 Ω 1.1 to 3.9 V
L
Rev. A | Page 5 of 20
ADA4857-1/ADA4857-2
(
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 11 V
Power Dissipation See Figure 4
Common-Mode Input Voltage −VS + 0.7 V to +VS − 0.7 V
Differential Input Voltage ±VS
Exposed Paddle Voltage −VS
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +125°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is specified
for device soldered in circuit board for surface-mount packages.
Table 4.
Package Type θJA θ
Unit
JC
8-Lead SOIC 115 15 °C/W
8-Lead LFCSP 94.5 34.8 °C/W
16-Lead LFCSP 68.2 19 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the ADA4857 is
limited by the associated rise in junction temperature (T
the die. At approximately 150°C, which is the glass transition
temperature, the properties of the plastic change. Even temporarily
exceeding this temperature limit may change the stresses that
the package exerts on the die, permanently shifting the parametric
performance of the ADA4857. Exceeding a junction temperature of
175°C for an extended period can result in changes in silicon
devices, potentially causing degradation or loss of functionality.
) on
J
The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
die due to the ADA4857 drive at the output. The quiescent
power is the voltage between the supply pins (V
quiescent current (I
P
= Quiescent Power + (Total Drive Power − Load Power)
D
()
D
).
S
⎛
V
V
⎜
IVP
SS
⎜
⎝
OUTS
×+×=
2
R
L
RMS output voltages should be considered. If R
to −V
, as in single-supply operation, the total drive power is
S
V
× I
. If the rms signal levels are indeterminate, consider the
S
OUT
worst case, when V
()
D
= VS/4 for RL to midsupply.
OUT
2
)
V
4/
S
IVP
+×=
SS
R
L
In single-supply operation with R
case is V
= VS/2.
OUT
Airflow increases heat dissipation, effectively reducing θ
In addition, more metal directly in contact with the package
leads and exposed paddle from metal traces, through holes,
ground, and power planes reduces θ
Figure 4 shows the maximum power dissipation in the package
vs. the ambient temperature for the SOIC and LFCSP packages
on a JEDEC standard 4-layer board. θ
3.0
2.5
2.0
1.5
1.0
ADA4857-1 (LFCSP )
0.5
MAXIMUM POWER DISSIPATION (W)
0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ADA4857-1 (SOIC)
) is the sum of the
D
) times the
S
⎞
⎟
⎟
⎠
L
2
V
OUT
–
R
L
is referenced
L
referenced to −VS, the worst
.
JA
.
JA
values are approximations.
JA
ADA4857-2 (LFCSP )
07040-004
Rev. A | Page 6 of 20
ESD CAUTION
ADA4857-1/ADA4857-2
–V
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1PD
ADA4857-1
2FB
TOP VIEW
3–IN
(Not to Scal e)
4+IN
NC = NO CONNECT
8+V
S
7OUT
6NC
5–V
S
07040-005
Figure 5. 8-Lead LFCSP Pin Configuration
Table 5. 8-Lead LFCSP Pin Function Descriptions
Pin No. Mnemonic Description
1 PD Power Down.
2 FB Feedback.
3 −IN Inverting Input.
4 +IN Noninverting Input.
5 −VS Negative Supply.
6 NC No Connect.
7 OUT Output.
8 +VS Positive Supply.
EP GND or VS
Exposed Pad. The exposed pad
may be connected to GND or V
1
FB
ADA4857-1
–IN
2
TOP VIEW
+IN
3
(Not to Scale)
4
S
NC = NO CONNECT
8
PD
+V
7
S
OUT
6
NC
5
07040-006
Figure 6. 8-Lead SOIC Pin Configuration
Table 6. 8-Lead SOIC Pin Function Descriptions
Pin No. Mnemonic Description
1 FB Feedback
2 −IN Inverting Input
3 +IN Noninverting Input
4 −VS Negative Supply
5 NC No Connect
6 OUT Output
7 +VS Positive Supply
8 PD Power Down
.
S
Rev. A | Page 7 of 20
ADA4857-1/ADA4857-2
–V
www.BDTIC.com/ADI
S1
OUT1
FB1
PD1
+V
14
13
16
15
1–IN1
ADA4857-2
2+IN1
3NC
(Not to Scale)
4
S2
NC = NO CONNECT
TOP VIEW
5
6
S2
+V
OUT2
12 –V
S1
11 NC
10 +IN2
9–IN2
8
7
FB2
PD2
07040-007
Figure 7. 16-Lead LFCSP Pin Configuration
Table 7. 16-Lead LFCSP Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN1 Inverting Input 1.
2 +IN1 Noninverting Input 1.
3, 11 NC No Connect.
4 −VS2 Negative Supply 2.
5 OUT2 Output 2.
6 +VS2 Positive Supply 2.
7 PD2 Power Down 2.
8 FB2 Feedback 2.
9 −IN2 Inverting Input 2.
10 +IN2 Noninverting Input 2.
12 −VS1 Negative Supply 1.
13 OUT1 Output 1.
14 +VS1 Positive Supply 1.
15 PD1 Power Down 1.
16 FB1 Feedback 1.
EP GND or Vs Exposed Pad. The exposed pad may be connected to GND or VS.
Rev. A | Page 8 of 20
ADA4857-1/ADA4857-2
www.BDTIC.com/ADI
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C (G = +1, RF = 0 Ω, and, RG open; G = +2, and RF = RG = 499 Ω), unless otherwise noted.
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
VS = ±5V
NORMALIZE D CLOSED-LOOP GAIN (dB)
R
= 1kΩ
L
–9
V
= 0.2V p-p
OUT
–10
1 10 100 1000
G = +10
G = +5
FREQUENCY (MHz )
G = +1
G = +2
07040-008
Figure 8. Small Signal Frequency Responses for Various Gains (LFCSP)
3
2
1
0
–1
–2
–3
–4
–5
–6
CLOSED-LOOP GAIN (dB)
–7
–8
G = +1
R
= 1kΩ
L
–9
V
= 0.2V p-p
OUT
–10
1 10 100 1000
FREQUENCY (MHz )
±5V
+5V
07040-009
Figure 9. Small Signal Frequency Response for Various Supply Voltages (LFCSP)
3
2
1
0
–1
–2
–3
–4
–5
–6
CLOSED-LOOP GAIN (dB)
–7
G = +1
–8
V
= ±5V
S
R
= 1kΩ
–9
L
V
= 0.2V p-p
OUT
–10
1 10 100 1000
FREQUENCY (MHz )
–40°C
+25°C
+125°C
07040-010
Figure 10. Small Signal Frequency Response for Various Temperatures (LFCSP)
Figure 12. Small Signal Frequency Response for Various Capacitive Loads (LFCSP)
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
VS = ±5V
NORMALIZE D CLOSED-LOOP GAIN (dB)
R
= 1kΩ
L
–9
V
= 2V p-p
OUT
–10
1 10 100 1000
G = +10
G = +5
FREQUENCY (MHz )
G = +1
G = +2
Figure 11. Large Signal Frequency Responses for Various Gains (LFCSP)
9
8
7
6
5
4
3
2
1
0
–1
–2
CLOSED-LOOP GAIN (dB)
–3
–4
G = +2
V
= ±5V
–5
S
R
= 1kΩ
L
–6
V
= 0.2V p-p
OUT
–7
1 10 100 1000
NO CAP LOAD
FREQUENCY (MHz)
10pF
5pF
3
2
1
0
–1
–2
–3
–4
–5
–6
CLOSED-LOOP GAIN (dB)
–7
–8
G = +1
V
= ±5V
S
–9
R
= 100Ω
L
–10
1 10 100 1000
FREQUE NCY (MHz )
4V p-p
Figure 13. Large Signal Frequency Response vs. V
1V p-p
OUT
(LFCSP)
07040-011
07040-012
07040-013
Rev. A | Page 9 of 20
ADA4857-1/ADA4857-2
–
–
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9
8
7
6
5
4
3
2
1
0
–1
–2
CLOSED-LOOP GAIN (dB)
–3
–4
G = +2
–5
V
= ±5V
S
–6
V
= 0.2V p-p
OUT
–7
1 10 100 1000
RL = 100Ω
FREQUENCY (MHz)
RL = 1kΩ
07040-014
Figure 14. Small Signal Frequency Response for Various Resistive Loads (LFCSP)
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
VS = 5V
NORMALIZE D CLOSED-LO OP GAIN (d B)
R
= 1kΩ
L
–9
V
= 0.2V p-p
OUT
–10
1 10 100 1000
G = +10
G = +5
FREQUENCY (MHz)
G = +1
G = +2
07040-015
Figure 15. Small Signal Frequency Response for Various Gains (LFCSP)
40
VS = ±5V
V
= 2V p-p
OUT
–50
R
= 1kΩ
L
–60
G = +1, HD2
G = +1, HD3
DISTORTION (dBc)
–70
–80
–90
–100
G = +2, HD2
3
2
1
0
–1
–2
–3
–4
–5
–6
CLOSED-LOOP GAIN (dB)
–7
–8
G = +1
V
= ±5V
S
–9
V
= 2V p-p
OUT
–10
1 10 100 1000
FREQUENCY (MHz)
RL = 100Ω
RL = 1kΩ
07040-017
Figure 17. Large Signal Frequency Response for Various Resistive Loads (LFCSP)
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
VS = ±5V
NORMALIZE D CLOSED-LOOP GAI N (dB)
R
= 1kΩ
L
–9
V
= 0.2V p-p
OUT
–10
1 10 100 1000
G = +10
G = +5
FREQUENCY (MHz)
G = +1
G = +2
07040-018
Figure 18. Small Signal Frequency Response for Various Gains (SOIC)
40
G = +1
V
= ±5V
S
V
OUT
= 2V p-p
RL = 100Ω, HD3
RL = 100Ω, HD2
RL = 1kΩ, HD2
DISTORTION (dBc)
–50
–60
–70
–80
–90
–100
–110
–120
0.2 1 10 100
G = +2, HD3
FREQUENCY (MHz)
07040-016
Figure 16. Harmonic Distortion vs. Frequency and Gain (LFCSP)
Rev. A | Page 10 of 20
–110
–120
0.2 1 10 100
RL = 1kΩ, HD3
FREQUENCY (MHz)
Figure 19. Harmonic Distortion vs. Frequency and Load (LFCSP)
07040-019
ADA4857-1/ADA4857-2
–
www.BDTIC.com/ADI
40
G = +2
V
= ±5V
S
R
= 1kΩ
–50
L
–60
–70
–80
–90
DISTORTION (dBc)
–100
–110
–120
12345678
HD2, f = 10MHz
HD2, f = 1MHz
OUTPUT VOLTAGE (V p-p)
HD3, f = 10MHz
HD3, f = 1MHz
Figure 20. Harmonic Distortion vs. Output Voltage
6.3
VS = ±5V
G = +2
R
= 150Ω
L
6.2
07040-020
0.5
0.4
0.3
0.2
0.1
0
–0.1
SETTLING TIME (%)
–0.2
–0.3
INPUT
–0.4
–0.5
OUTPUT
TIME (5ns/DIV)
V
OUT
G = +2
V
= ±5
S
= 2V p-p
07040-023
Figure 23. Short-Term Settling Time (LFCSP)
6.3
VS = ±5V
G = +2
R
= 150Ω
L
6.2
6.1
V
= 2V p-p
OUT
6.0
5.9
CLOSED-LOOP GAIN (dB)
5.8
5.7
1 10 100
V
= 0.2V p-p
OUT
FREQUENCY (MHz )
07040-021
Figure 21. 0.1 dB Flatness vs. Frequency for Various Output Voltages (SOIC)
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
OUTPUT VOLTAGE (V)
–1.5
–2.0
–2.5
4V p-p
2V p-p
TIME (10ns/DIV)
VS = ±5V
= 1kΩ
R
L
G = +2
07040-022
Figure 22. Large Signal Transient Response for Various Output Voltages (SOIC)
6.1
6.0
V
= 2V p-p
OUT
5.9
CLOSED-LOOP GAIN (dB)
5.8
5.7
1 10 100
V
= 0.2V p-p
OUT
FREQUENCY (MHz )
07040-024
Figure 24. 0.1 dB Flatness vs. Frequency for Various Output Voltages (LFCSP)
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
OUTPUT VOLTAGE (V)
–1.5
–2.0
–2.5
4V p-p
2V p-p
TIME (10n s/DIV)
VS = ±5V
R
= 1kΩ
L
G = +1
07040-025
Figure 25. Large Signal Transient Response for Various Output Voltages (LFCSP)
Rev. A | Page 11 of 20
ADA4857-1/ADA4857-2
www.BDTIC.com/ADI
OUTPUT VOLTAGE (V)
0.25
0.20
0.15
0.10
0.05
–0.05
–0.10
–0.15
–0.20
–0.25
CL = 1.5pF
0
TIME (10n s/DIV)
VS = ±5V
R
G = +1
CL = 10pF
= 1kΩ
L
Figure 26. Small Signal Transient Response for Various Capacitive Loads (LFCSP)
OUTPUT VOLTAGE (V)
0.25
0.20
0.15
0.10
0.05
–0.05
–0.10
–0.15
–0.20
–0.25
VS = ±5V
VS = ±2.5V
0
TIME (10n s/DIV)
RL = 1kΩ
G = +1
Figure 27. Small Signal Transient Response for Various Supply Voltages (LFCSP)
1000
VS = ±5V
100
2.0
1.6
1.2
0.8
0.4
0
–0.4
–0.8
OUTPUT VOLTAGE (V)
–1.2
–1.6
07040-026
–2.0
RL = 1kΩ
TIME (10ns/DIV)
VS = ±5V
G = +2
RL = 100Ω
07040-029
Figure 29. Large Signal Transient Response for Various Load Resistances (SOIC)
2.0
1.6
1.2
0.8
0.4
0
–0.4
–0.8
OUTPUT VO LTAGE (V )
–1.2
–1.6
07040-027
–2.0
RL = 1kΩ
TIME (10ns/DIV)
VS = ±5V
G = +1
RL = 100Ω
07040-030
Figure 30. Large Signal Transient Response for Various Load Resistances (LFCSP)
100
Ω)
k
10
VS = ±5V
G = +2
10
1
CLOSED-LO OP OUTP UT IMPEDANCE (Ω)
0.1
0.1 1 10 100
G = +5
G = +2
FREQUENCY (MHz )
1000
07040-028
Figure 28. Closed-Loop Output Impedance vs. Frequency for Various Gains
Rev. A | Page 12 of 20
1
0.1
CLOSED-LO OP INPUT IMPEDANCE (
0.01
1 10 100 1000
FREQUENCY (MHz )
Figure 31. Closed-Loop Input Impedance vs. Frequency
07040-031
ADA4857-1/ADA4857-2
–
www.BDTIC.com/ADI
L
= 1k
0
Ω
–20
–40
–60
–80
–100
–120
–140
OPEN-LOOP PHASE (Degrees)
–160
–180
07040-032
80
70
60
50
40
30
20
OPEN-LOOP GAIN (dB)
10
0
–10
0.1
PHASE
GAIN
1 10 100 1000
FREQUENCY (MHz)
VS = ±5V
R
Figure 32. Open-Loop Gain and Phase vs. Frequency
8
VS = ±5V
G = +1
6
0
G = +2
V
= ±5V
S
–10
R
= 1kΩ
L
PD = 3V
–20
–30
–40
–50
–60
PD ISOLATION (dB)
–70
–80
–90
–100
0.1 1 10 100 1000
FREQUENCY (MHz)
LFCSP
Figure 35. PD Isolation vs. Frequency
8
VS = ±5V
G = +2
6
SOIC
07040-035
4
2
0
–2
OUTPUT VOL TAGE (V)
–4
–6
INPUT
–8
OUTPUT
R
OUTPUT
R
= 1kΩ
L
= 100Ω
L
TIME (40n s/DIV)
Figure 33. Input Overdrive Recovery for Various Resistive Loads
10
VS = ±5V
= 1kΩ
R
L
0
–10
–20
–30
–40
PSRR (dB)
–50
+PSRR
–60
–70
–PSRR
–80
0.1 1 10 100 1000
FREQUENCY (MHz )
Figure 34. Power Supply Rejection Ratio (PSRR) vs. Frequency
4
2
0
–2
OUTPUT VOLTAGE (V)
–4
2 × INPUT
–6
07040-033
–8
OUTPUT
R
= 1kΩ
L
OUTPUT
R
= 100Ω
L
TIME (2 00ns/DIV)
07040-036
Figure 36. Output Overdrive Recovery for Various Resistive Loads
30
VS = ±5V
= 1kΩ
R
L
–40
–50
–60
CMRR (dB)
–70
–80
–90
0.1 1 10 100 1000
07040-034
FREQUENCY (MHz )
07040-037
Figure 37. Common-Mode Rejection Ratio (CMRR) vs. Frequency
Rev. A | Page 13 of 20
ADA4857-1/ADA4857-2
www.BDTIC.com/ADI
100
VS = ±5V
10
CURRENT NOISE (pA/√Hz)
VOLTAGE NOISE (nV/√Hz)
1000
100
VS = ±5V
10
1
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 38. Input Current Noise vs. Frequency
50
N = 238
MEAN: 5.00
SD: 0.02
40
30
COUNT
20
10
0
4.954.904.85 5. 00
SUPPLY CURRENT (mA)
Figure 39. Supply Current
07040-050
5.155.105.05
07040-042
1
1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 40. Input Voltage Noise vs. Frequency
3.5
3.0
PD INPUT
OUTPUT
TIME (20µs/DIV)
VOLTAGE (V)
2.5
2.0
1.5
1.0
0.5
0
–0.5
Figure 41. Disable/Enable Switching Speed
07040-041
07040-043
Rev. A | Page 14 of 20
ADA4857-1/ADA4857-2
V
V
V
V
V
V
V
V
www.BDTIC.com/ADI
TEST CIRCUITS
+
S
1kΩ
1kΩ
1kΩ
10µF
1kΩ
10µF
+
+
0.1µF 0. 1µF
V
OUT
R
L
0.1µF
–V
S
07040-046
+
S
10µF
+
0.1µF
0.1µF
V
IN
49.9Ω
10µF
+
–V
0.1µF
S
Figure 42. Noninverting Load Configuration
V
OUT
R
L
07040-047
IN
53.6Ω
Figure 45. Common-Mode Rejection
+
S
10µF
+
AC
49.9Ω
V
OUT
R
L
0.1µF
–V
S
07040-045
Figure 43. Positive Power Supply Rejection
+
S
10µF
+
R
R
F
G
V
IN
49.9Ω
10µF
+
0.1µF
0.1µF
V
C
0.1µF
–V
S
OUT
R
L
L
Figure 44. Typical Capacitive Load Configuration (LFCSP)
+
S
10µF
+
0.1µF
V
OUT
R
L
07040-048
AC
49.9Ω
–V
S
Figure 46. Negative Power Supply Rejection
+
S
10µF
+
R
IN
07040-051
R
G
49.9Ω
10µF
F
+
–V
S
0.1µF 0.1µF
0.1µF
R
40Ω
SNUB
V
OUT
R
C
L
L
07040-049
Figure 47. Typical Capacitive Load Configuration (SOIC)
Rev. A | Page 15 of 20
ADA4857-1/ADA4857-2
www.BDTIC.com/ADI
APPLICATIONS INFORMATION
POWER-DOWN OPERATION
The PD pin is used to power down the chip, which reduces the
quiescent current and the overall power consumption. It is low
enabled, which means that the chip is on with full power when
the PD pin input voltage is low (see Tab l e 8 ). Note that PD does not
put the output in a high-Z state, which means that the ADA4857
should not be used as a multiplexer.
Table 8. PD Operation Table Guide
Supply Voltage
Condition ±5 V ±2.5 V +5 V
Enabled ≤+0.8 V ≤−1.7 V ≤+0.8 V
Powered down ≥+3 V ≥+0.5 V ≥+3 V
Table 9. Various Gain and Recommended Resistor Values Associated with Conditions; VS = ±5 V, TA = 25°C, RL = 1 kΩ, RT = 49.9 Ω
−3 dB SS BW (MHz),
V
Gain RF (Ω) RG (Ω)
+1 0 N/A 850 2350 4.4 4.49
+2 499 499 360 1680 8.8 9.89
+5 499 124 90 516 22.11 23.49
+10 499 56.2 43 213 43.47 45.31
= 200 mV p-p
OUT
Slew Rate (V/μs),
V
= 2 V Step
OUT
CAPACITIVE LOAD CONSIDERATIONS
When driving a capacitive load using the SOIC package, R
used to reduce the peaking (see Figure 47). An optimum resistor
value of 40 Ω is found to maintain the peaking within 1 dB for
any capacitive load up to 40 pF.
SNUB
is
RECOMMENDED VALUES FOR VARIOUS GAINS
Tabl e 9 provides a useful reference for determining various gains
and associated performance. R
their contribution to the overall noise performance of the amplifier.
ADA4857 Voltage
Noise (nV/√Hz), RTO
and RG are kept low to minimize
F
Total System
Noise (nV/√Hz), RTO
Rev. A | Page 16 of 20
ADA4857-1/ADA4857-2
www.BDTIC.com/ADI
ACTIVE LOW-PASS FILTER (LPF)
Active filters are used in many applications such as antialiasing
filters and high frequency communication IF strips. With a
410 MHz gain bandwidth product and high slew rate, the
ADA4857-2 is an ideal candidate for active filters. Figure 48
shows the frequency response of 90 MHz and 45 MHz LPFs.
In addition to the bandwidth requirements, the slew rate must
be capable of supporting the full power bandwidth of the filter.
In this case, a 90 MHz bandwidth with a 2 V p-p output swing
requires at least 2800 V/μs.
The circuit shown in Figure 49 is a 4-pole, Sallen-Key LPF. The
filter comprises two identical cascaded Sallen-Key LPF sections,
each with a fixed gain of G = 2. The net gain of the filter is equal
to G = 4 or 12 dB. The actual gain shown in Figure 48 is 12 dB.
This does not take into account the output voltage being divided in
half by the series matching termination resistor, R
load resistor.
Setting the resistors equal to each other greatly simplifies the
design equations for the Sallen-Key filter. To achieve 90 MHz,
the value of R should be set to 182 Ω. However, if the value of R
is doubled, the corner frequency is cut in half to 45 MHz. This
would be an easy way to tune the filter by simply multiplying
the value of R (182 Ω) by the ratio of 90 MHz and the new
corner frequency in megahertz.
+IN1
49.9Ω
R
R
T
R
C2
5.6pF
348Ω
, and the
T
C1
3.9pF
10µF
+5V
0.1µF
U1
10µF
0.1µF
–5V
R2
R1
348Ω
OUT1
Figure 49. 4-Pole, Sallen-Key Low-Pass Filter (ADA4857-2)
Figure 48 shows the output of each stage is of the filter and the
two different filters corresponding to R = 182 Ω and R = 365 Ω.
Resistor values are kept low for minimal noise contribution,
offset voltage, and optimal frequency response. Due to the low
capacitance values used in the filter circuit, the PCB layout and
minimization of parasitics is critical. A few picofarads can detune
the corner frequency, f
of the filter. The capacitor values shown
c
in Figure 49 actually incorporate some stray PCB capacitance.
Capacitor selection is critical for optimal filter performance.
Capacitors with low temperature coefficients, such as NPO
ceramic capacitors and silver mica, are good choices for filter
elements.
15
12
9
6
3
0
–3
–6
–9
–12
–15
–18
–21
MAGNITUDE (d B)
–24
–27
–30
–33
–36
RL = 100Ω
–39
= ±5V
V
S
–42
0.1 1 10 100 500
OUT1, f = 90MHz
OUT1, f = 45MHz
OUT2, f = 90MHz
OUT2, f = 45MHz
FREQUENCY (MHz)
Figure 48. Low-Pass Filter Response
C3
3.9pF
10µF
+5V
0.1µF
348Ω
U2
10µF
0.1µF
–5V
R4
R3
348Ω
R
49.9Ω
T
OUT2
07040-075
R
R
5.6pF
C4
07040-074
Rev. A | Page 17 of 20
ADA4857-1/ADA4857-2
V
www.BDTIC.com/ADI
NOISE
To analyze the noise performance of an amplifier circuit, identify
the noise sources and determine if the source has a significant
contribution to the overall noise performance of the amplifier.
To simplify the noise calculations, noise spectral densities were
used rather than actual voltages to leave bandwidth out of the
expressions (noise spectral density, which is generally expressed
in nV/√Hz, is equivalent to the noise in a 1 Hz bandwidth).
The noise model shown in Figure 50 has six individual noise
sources: the Johnson noise of the three resistors, the op amp
voltage noise, and the current noise in each input of the amplifier.
Each noise source has its own contribution to the noise at the
output. Noise is generally referred to input (RTI), but it is often
easier to calculate the noise referred to the output (RTO) and
then divide by the noise gain to obtain the RTI noise.
N, R2
R2
4kTR2
V
N, R1
B
4kTR1
V
N, R3
A
4kTR3
RTI NOISE =
RTO NOISE = NG × RTI NOISE
I
N–
R1
V
N
R3
I
N+
2
V
+ 4kTR3 + 4kTR1
N
2
+
I
R32 + I
N+
Figure 50. Op Amp Noise Analysis Model
R1 × R2
2
N–
R1 + R2 R1 + R2
All resistors have Johnson noise that is calculated by
)(4kBTR
where:
–23
k is Boltzmann’s Constant (1.38 × 10
J/K).
B is the bandwidth in Hertz.
T is the absolute temperature in Kelvin.
R is the resistance in ohms.
A simple relationship that is easy to remember is that a 50 Ω
resistor generates a Johnson noise of 1 nV/√Hz at 25°C.
In applications where noise sensitivity is critical, care must
be taken not to introduce other significant noise sources to
the amplifier. Each resistor is a noise source. Attention to the
following areas is critical to maintain low noise performance:
design, layout, and component selection. A summary of noise
performance for the amplifier and associated resistors can be
seen in Tab le 9 .
GAIN FROM
B TO OUT PUT
R2
R1 + R2
2
+ 4kTR2
GAIN FROM
A TO OUTPUT
NOISE GAIN =
NG = 1 +
V
OUT
= –
R1
2
R1
=
R2
R1
R2
2
7040-073
CIRCUIT CONSIDERATIONS
Careful and deliberate attention to detail when laying out the
ADA4857 board yields optimal performance. Power supply
bypassing, parasitic capacitance, and component selection all
contribute to the overall performance of the amplifier.
PCB LAYOUT
Because the ADA4857 can operate up to 850 MHz, it is essential
that RF board layout techniques be employed. All ground and
power planes under the pins of the ADA4857 should be cleared
of copper to prevent the formation of parasitic capacitance between
the input pins to ground and the output pins to ground. A single
mounting pad on the SOIC footprint can add as much as 0.2 pF
of capacitance to ground if the ground plane is not cleared from
under the mounting pads. The low distortion pinout of the
ADA4857 increases the separation distance between the inputs
and the supply pins, which improves the second harmonics. In
addition, the feedback pin reduces the distance between the output
and the inverting input of the amplifier, which helps minimize
the parasitic inductance and capacitance of the feedback path,
reducing ringing and peaking.
POWER SUPPLY BYPASSING
Power supply bypassing for the ADA4857 was optimized for
frequency response and distortion performance. Figure 42 shows
the recommended values and location of the bypass capacitors.
The 0.1 μF bypassing capacitors should be placed as close as
possible to the supply pins. Power supply bypassing is critical for
stability, frequency response, distortion, and PSR performance.
The capacitor between the two supplies helps improve PSR and
distortion performance. The 10 μF electrolytic capacitors should
be close to the 0.1 μF capacitors; however, it is not as critical. In
some cases, additional paralleled capacitors can help improve
frequency and transient response.
GROUNDING
Ground and power planes should be used where possible. Ground
and power planes reduce the resistance and inductance of the
power planes and ground returns. The returns for the input, output
terminations, bypass capacitors, and R
close to the ADA4857 as possible. The output load ground and the
bypass capacitor grounds should be returned to the same point
on the ground plane to minimize parasitic trace inductance,
ringing, and overshoot and to improve distortion performance.
The ADA4857 LFSCP packages feature an exposed paddle. For
optimum electrical and thermal performance, solder this paddle to
the ground plane or the power plane. For more information on
high speed circuit design, see A Practical Guide to High-Speed
Printed-Circuit-Board Layout at www.analog.com.
should all be kept as
G
Rev. A | Page 18 of 20
ADA4857-1/ADA4857-2
www.BDTIC.com/ADI
OUTLINE DIMENSIONS
3.25
3.00 SQ
INDICATOR
0.90 MAX
0.85 NOM
SEATING
PLANE
PIN 1
12° MAX
2.75
TOP
VIEW
0.70 MAX
0.65 TYP
0.30
0.23
0.18
2.95
2.75 SQ
2.55
0.05 MAX
0.01 NOM
0.20 REF
0.60 MAX
Figure 51. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-2)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
0.60 MAX
5
EXPOSED
PA D
(BOTTOM VIEW)
0.50
0.40
0.30
4
FOR PROPER CONNECTION O F
THE EXPOSE D PAD, REFER T O
THE PIN CONF IGURATIO N AND
FUNCTION DESCRIPTIO NS
SECTION OF THIS DATA SHEET.
0.50
BSC
8
1.60
1.45
1.30
1
1.89
1.74
1.59
PIN 1
INDICATOR
72408-B
4.00 (0.1574)
3.80 (0.1497)
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
CONTROLL ING DIMENSI ONS ARE IN MILLIMETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.
85
1
1.27 (0.0500)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-A A
BSC
6.20 (0.2441)
5.80 (0.2284)
4
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
8°
0°
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
0.40 (0.0157)
45°
012407-A
Figure 52. 8-Lead Standard Small Outline Package [SOIC_N]
(R-8)
Dimensions shown in millimeters and (inches)
Rev. A | Page 19 of 20
ADA4857-1/ADA4857-2
www.BDTIC.com/ADI
PIN 1
INDICATOR
12° MAX
1.00
0.85
0.80
BSC SQ
SEATING
PLANE
4.00
0.60 MAX
TOP
VIEW
0.80 MAX
0.65 TYP
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
0.35
0.30
0.25
3.75
BSC SQ
0.20 REF
0.65 BSC
0.05 MAX
0.02 NOM
COPLANARITY
0.75
0.60
0.50
0.08
(BOTTO M VIEW )
13
12
9
8
1.95 BSC
0.60 MAX
16
5
FOR PROPER CO NNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DES CRIPTIONS
SECTION O F THIS DAT A SHEET.
PIN 1
INDICATOR
1
4
5
2
.
2
0
1
.
2
S
9
.
1
5
0.25 MIN
Q
072808-A
Figure 53. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Ordering Quantity Branding
ADA4857-1YCPZ-R21 –40°C to +125°C 8-Lead LFCSP_VD CP-8-2 250 H15
ADA4857-1YCPZ-RL1 –40°C to +125°C 8-Lead LFCSP_VD CP-8-2 5,000 H15
ADA4857-1YCPZ-R71 –40°C to +125°C 8-Lead LFCSP_VD CP-8-2 1,500 H15
ADA4857-1YRZ1 –40°C to +125°C 8-Lead SOIC_N R-8 1
ADA4857-1YRZ-R71 –40°C to +125°C 8-Lead SOIC_N R-8 2,500
ADA4857-1YRZ-RL1 –40°C to +125°C 8-Lead SOIC_N R-8 1,000
ADA4857-2YCPZ-R21 –40°C to +125°C 16-Lead LFCSP_VQ CP-16-4 250
ADA4857-2YCPZ-RL1 –40°C to +125°C 16-Lead LFCSP_VQ CP-16-4 5,000
ADA4857-2YCPZ-R71 –40°C to +125°C 16-Lead LFCSP_VQ CP-16-4 1,500
1
Z = RoHS Compliant Part.
Rev. A | Page 20 of 20
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