ANALOG DEVICES ADA4855-3 Service Manual

Single Supply, High Speed,

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FEATURES

Voltage feedback architecture Rail-to-rail output swing: 0.1 V to 4.9 V High speed amplifiers

410 MHz, −3 dB bandwidth, G = 1 210 MHz, −3 dB bandwidth, G = 2 Slew rate: 870 V/μs 53 MHz, 0.1 dB large signal flatness

5.3 ns settling time to 0.1% with 2 V step

High input common-mode voltage range

−V

− 0.2 V to +VS − 1 V

S

Supply range: 3 V to 5.5 V Differential gain error: 0.01% Differential phase error: 0.01° Low power

7.8 mA/amplifier typical supply current Power-down feature

Available in 16-lead LFCSP

APPLICATIONS

Professional video Consumer video Imaging Instrumentation Base stations Active filters

GENERAL DESCRIPTION

The ADA4855-3 (triple) is a single-supply, rail-to-rail output operational amplifier. It provides excellent high speed performance with 410 MHz, −3 dB bandwidth and a slew rate of 870 V/μs. It has a wide input common-mode voltage range that extends from

0.2 V below ground to 1 V below the positive rail.In addition, the output voltage swings within 100 mV of either supply rail, making this rail-to-rail operational amplifier easy to use on singlesupply voltages as low as 3.3 V.

The ADA4855-3 offers a typical low power of 7.8 mA per amplifier and is capable of delivering up to 57 mA of load current. It also features a power-down function for power sensitive applications that reduces the supply current down to 1 mA.

The ADA4855-3 is available in a 16-lead LFCSP and is designed to work over the extended industrial temperature range of

−40°C to +105°C.

Rail-to-Rail Output, Triple Op Amp

ADA4855-3

CONNECTION DIAGRAM

+IN1

16 15 14 13

1

NC

2+IN2

NC

PD

1

0

–1

–2

–3

–4

–5

NORMALIZED CLOSED-L OOP GAIN (dB)

–6

110

ADA4855-3

3

4

5678

+IN3

NOTES

1. NC = NO CONNECT .

2. EXPOSE D PAD CONNECTED TO –V

Figure 1.

G = 5

FREQUENCY (MHz)

Figure 2. Frequency Response

S

–IN1

OUT1

–V

12

+V

S

OUT2

11

–IN2

10

+V

9

S

–V

–IN3

OUT3

.

S

07685-001

G = 1

G = 2

100 1000

07685-004

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADA4855-3

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REVISION HISTORY

11/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

ADA4855-3

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SPECIFICATIONS

5 V OPERATION

TA = 25°C, VS = 5 V, G = 1, RL = 150 Ω, unless otherwise noted.

Table 1.

Parameter Test Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth VO = 0.1 V p-p 410 MHz V V V Bandwidth for 0.1 dB Flatness VO = 2 V p-p 53 MHz V Slew Rate VO = 2 V step 870 V/μs Settling Time to 0.1% VO = 2 V step (rise/fall) 5.3/9.5 ns V

NOISE/DISTORTION PERFORMANCE

Harmonic Distortion (HD2/HD3) fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ −84/−105 dBc f Crosstalk, Output to Output f = 5 MHz, G = 2 −90 dBc Input Voltage Noise f = 100 kHz 6.8 nV/√Hz Input Current Noise f = 100 kHz 2 pA/√Hz Differential Gain Error G = 2 0.01 % Differential Phase Error G = 2 0.01 Degrees

DC PERFORMANCE

Input Offset Voltage 1.3 3 mV Input Offset Voltage Drift 5.5 μV/°C Input Bias Current −3.8 μA Input Offset Current ±0.05 μA Open-Loop Gain VO = 0.5 V to 4.5 V 92 dB

INPUT CHARACTERISTICS

Input Resistance 6.4 MΩ Input Capacitance 0.5 pF Input Common-Mode Voltage Range −VS − 0.2 +VS − 1 V Common-Mode Rejection Ratio VCM = –0.2 V to +4 V 94 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing 0.1 to 4.9 V Linear Output Current per Amplifier HD2 ≤ −60 dBc, RL = 10 Ω 57 mA

POWER-DOWN

Turn-On Time 78 ns Turn-Off Time 1.2 μs Bias Current On 0.3 μA Off −125 μA Turn-On Voltage +VS − 1.25 V

POWER SUPPLY

Operating Range 3 5.5 V Quiescent Current per Amplifier 7.8 mA Supply Current When Powered Down 1.1 mA Power Supply Rejection Ratio ∆VS = 4.5 V to 5.5 V 96 dB

= 2 V p-p 200 MHz

O

= 0.1 V p-p, G = 2 210 MHz

O

= 2 V p-p, G = 2 120 MHz

O

= 2 V p-p, G = 2 50 MHz

O

= 2 V step (rise/fall), G = 2 7.4/7 ns

O

= 20 MHz, VO = 2 V p-p, RL = 1 kΩ −60/−66 dBc

C

Rev. 0 | Page 3 of 20

ADA4855-3

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3.3 V OPERATION

TA = 25°C, VS = 3.3 V, G = 1, RL = 150 Ω, unless otherwise noted.

Table 2.

Parameter Test Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth VO = 0.1 V p-p 430 MHz

V

Bandwidth for 0.1 dB Flatness VO = 1.4 V p-p, G = 2 55 MHz

Slew Rate VO = 2 V step, G = 2 870 V/μs

Settling Time to 0.1% VO = 2 V step (rise/fall), G = 2 7.4/7.1 ns NOISE/DISTORTION PERFORMANCE

Harmonic Distortion (HD2/HD3) fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ −76/−76 dBc

f

Crosstalk, Output to Output f = 5 MHz, G = 2 −88 dBc

Input Voltage Noise f = 100 kHz 6.8 nV/√Hz

Input Current Noise f = 100 kHz 2 pA/√Hz

Differential Gain Error G = 2 0.01 %

Differential Phase Error G = 2 0.01 Degrees DC PERFORMANCE

Input Offset Voltage 1.3 mV

Input Offset Voltage Drift 5.5 μV/°C

Input Bias Current −3.8 μA

Input Offset Current 0.05 μA

Open-Loop Gain VO = 0.5 V to 4.5 V 92 dB INPUT CHARACTERISTICS

Input Resistance 6.4 MΩ

Input Capacitance 0.5 pF

Input Common-Mode Voltage Range −VS − 0.2 +VS − 1 V

Common-Mode Rejection Ratio VCM = –0.2 V to +3.2 V 94 dB OUTPUT CHARACTERISTICS

Output Voltage Swing 0.1 to 3.22 V

Linear Output Current per Amplifier HD2 ≤ −60 dBc, RL = 10 Ω 40 mA POWER-DOWN

Turn-On Time 78 ns

Turn-Off Time 1.2 μs

Turn-On Voltage +VS − 1.25 V POWER SUPPLY

Operating Range 3 5.5 V

Quiescent Current per Amplifier 7.5 mA

Supply Current When Powered Down 0.95 mA

Power Supply Rejection Ratio ∆VS = 2.97 V to 3.63 V 94 dB

= 1.4 V p-p 210 MHz

O

= 0.1 V p-p, G = 2 210 MHz

O

= 2 V p-p, G = 2 125 MHz

O

= 20 MHz, VO = 2 V p-p, RL = 1 kΩ −68/−75 dBc

C

Rev. 0 | Page 4 of 20

ADA4855-3

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ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage 6 V Internal Power Dissipation1 See Figure 3 Common-Mode Input Voltage (−VS − 0.2 V) to (+VS − 1 V) Differential Input Voltage ±VS Output Short-Circuit Duration Observe power curves Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +105°C Lead Temperature (Soldering, 10 sec) 300°C

1

Specification is for device in free air.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, θJA is specified for a device soldered in a circuit board for surface-mount packages.

Table 4.

Package Type θJA θ

16-Lead LFCSP 67 17.5 °C/W

Unit

JC

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the ADA4855-3 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure.

To ensure proper operation, it is necessary to observe the maximum power derating curves.

3.0

2.5

2.0

1.5

1.0

0.5

MAXIMUM POWER DISSIPATION (W)

0

–40

–30

Figure 3. Maximum Power Dissipation vs. Ambient Temperature

0

–20

102030405060708090

–10

AMBIENT TEMPERATURE (°C)

07685-103

100

ESD CAUTION

Rev. 0 | Page 5 of 20

ADA4855-3

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

S

–IN1

+IN1

OUT1

–V

14

13

15

16

1NC

ADA4855-3

2+IN2

TOP VIEW

3NC

(Not to Scale)

4PD

5

6

–IN3

+IN3

NOTES

1. NC = NO CONNECT .

2. EXPOSE D PAD CONNECTED TO –V

12 +V

S

11 OU T2

10 –IN2

9+V

S

8

7

S

–V

OUT3

.

S

07685-003

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 NC No Connect. 2 +IN2 Noninverting Input 2. 3 NC No Connect. 4

PD

Power Down.

5 +IN3 Noninverting Input 3. 6 −IN3 Inverting Input 3. 7 OUT3 Output 3. 8 −VS Negative Supply. 9 +VS Positive Supply. 10 −IN2 Inverting Input 2. 11 OUT2 Output 2. 12 +VS Positive Supply. 13 −VS Negative Supply. 14 OUT1 Output 1. 15 −IN1 Inverting Input 1. 16 +IN1 Noninverting Input 1. 17 (EPAD) Exposed Pad (EPAD) The exposed pad must be connected to −VS.

Rev. 0 | Page 6 of 20

ADA4855-3

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TYPICAL PERFORMANCE CHARACTERISTICS

T = 25°C, VS = 5V, G = 1, RF = 1 kΩ for G > 1, RL = 150 Ω, small signal V otherwise noted.

1

= 100 mV p-p, and large signal V

OUT

1

= 2 V p-p, unless

OUT

0

–1

–2

–3

–4

–5

NORMALIZED CLOSED-L OOP GAIN (dB)

–6

110

G = 5

FREQUENCY (M Hz)

G = 2

100 1000

Figure 5. Small Signal Frequency Response vs. Gain

1

0

–1

–2

–3

–4

G = 5

G = 2

G = 1

0

–1

–2

–3

–4

–5

NORMALIZED CLOSED-L OOP GAIN (dB)

–6

07685-004

110

G = 2

G = 5

FREQUENCY (MHz )

G = 1

100 1000

07685-007

Figure 8. Large Signal Frequency Response vs. Gain

1

0

–1

–2

–3

–4

V

OUT

G = 5

= 2V p-p

G = 2 V

OUT

= 2V p-p

G = 1 V

OUT

= 1.4V p-p

–5

NORMALIZED CLOSED-L OOP GAIN (dB)

VS = 3.3V

–6

110

FREQUENCY (M Hz)

100 1000

Figure 6. Small Signal Frequency Response vs. Gain

1

0

–1

–2

–3

–4

CLOSED-LOOP GAIN (dB)

–5

–6

110

FREQUENCY (M Hz)

RL = 150

100 1000

Figure 7. Small Signal Frequency Response vs. Load

RL = 1k

–5

NORMALIZED CLOSED-L OOP GAIN (dB)

= 3.3V

V

S

–6

07685-005

110

FREQUENCY (MHz )

100 1000

07685-008

Figure 9. Large Signal Frequency Response vs. Gain

1

0

–1

–2

–3

–4

CLOSED-LOOP GAIN (dB)

–5

–6

07685-006

110

FREQUENCY (M Hz)

CF = 4.4pF

CF = 2.2pF

100 1000

CF = 6.6pF

07685-009

Figure 10. Small Signal Frequency Response vs. Capacitive Load

Rev. 0 | Page 7 of 20

ADA4855-3

–

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0.2

6.2

0.1

= 3.3V, V

V

S

0

–0.1

–0.2

–0.3

CLOSED-LOOP GAIN (dB)

–0.4

–0.5

1 10 100 1000

VS= 5V, V

= 2V p-p

OUT

FREQUENCY (MHz)

OUT

Figure 11. 0.1 dB Flatness vs. Supply Voltage

1

0

–1

–2

–3

–4

CLOSED-LOOP GAIN (dB)

–5

= +105°C

T

A

T

= –40°C

A

= +85°C

A

T

= +25°C

A

= 1.4V p-p

6.1

6.0

5.9

5.8

5.7

CLOSED-LOOP GAIN (dB)

5.6

07685-037

5.5

VS= 5V

VS= 3.3V

G= 2

1 10 100 1000

FREQUENCY (MHz)

07685-040

Figure 14. 0.1 dB Flatness vs. Supply Voltage

100

75

50

25

GAIN (dB)

0

–25

PHASE

GAIN

0

–50

–100

–150

–200

–250

PHASE (Degrees)

–6

1 10 100 1000

FREQUENCY (MHz)

Figure 12. Small Signal Frequency Response vs. Temperature

50

V

= 1V p-p

OUT

V

= 3.3V

S

–55

R

= 1k

L

–60

–65

–70

–75

DISTORTION (dBc)

–80

–85

–90

0.1 1 10 40

HD2

HD3

FREQUENCY (MHz)

Figure 13. Harmonic Distortion vs. Frequency

07685-038

–50

10 100 1k 10k 100k 1M 10M 100M 1G 10G

FREQUENCY (Hz)

–300

07685-035

Figure 15. Open-Loop Gain and Phase vs. Frequency

50

V

= 1V p-p

OUT

R

= 1k

L

–60

–70

–80

–90

–100

DISTORTI ON (dBc)

–110

–120

07685-014

–130

0.1 1 10 40

HD2

HD3

07685-011

FREQUENCY (MHz)

Figure 16. Harmonic Distortion vs. Frequency

Rev. 0 | Page 8 of 20

ADA4855-3

R p A



–

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0

–20

–40

–60

–80

FORWARD ISOLATIO N (dB)

–100

–120

0.1 1 10 100 1000

OUT3

OUT1

OUT2

FREQUENCY (MHz )

Figure 17. Forward Isolation vs. Frequency

0

–10

–20

–30

–40

–PSRR +PSRR

0.01 0. 1 1 1 0 100

FREQUENCY (MHz)

PSRR (dB)

–50

–60

–70

–80

–90

–100

Figure 18. Power Supply Rejection Ratio (PSRR) vs. Frequency

100

40

–50

–60

–70

–80

–90

CROSSTALK (d B)

–100

–110

07685-012

–120

110

IN2, IN3, OUT1

IN1, IN2, OUT3

IN1, IN3, OUT2

07685-015

100 1000

FREQUENCY (MHz)

Figure 20. Crosstalk vs. Frequency

30

–40

–50

–60

–70

CMRR (dB)

–80

–90

07685-013

–100

0.01 0.1 1 10 100

FREQUENCY (MHz)

07685-016

Figure 21. Common-Mode Rejection Ratio (CMRR) vs. Frequency

100

Hz) /

10

ENT NOISE (

CUR

1

10 10 0 1k 10k 100k 1M 10M

FREQUENCY (Hz)

07685-020

Figure 19. Input Current Noise vs. Frequency

Rev. 0 | Page 9 of 20

= 5V

V

S

VS= 3.3V

10

VOLTAGE NOISE (n V/Hz)

1

10 100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 22. Input Voltage Noise vs. Frequency

07685-017

ADA4855-3

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0.08

0.06

0.04

0.02

V

= 3.3V

S

VS = 5V

1.5

1.0

0.5

CL = 2.2pF C

= 4.4pF

L

C

= 6.6pF

L

0

–0.02

OUTPUT VOL TAGE (V)

–0.04

–0.06

–0.08

TIME (10n s/DIV)

Figure 23. Small Signal Transient Response vs. Supply Voltage

0.08

0.06

OUTPUT VO LTAGE (V )

0.04

0.02

0

–0.02

–0.04

–0.06

–0.08

CL = 2.2pF

= 4.4pF

C

L

= 6.6pF

C

L

TIME (1 0ns/DIV)

Figure 24. Small Signal Transient Response vs. Capacitive Load

1.5

1.0

0.5

R

= 150

L

RL = 1k

0

–0.5

OUTPUT VOLT AGE (V)

–1.0

07685-018

–1.5

TIME (10ns/DIV)

07685-022

Figure 26. Large Signal Transient Response vs. Capacitive Load

0.08

0.06

CL = 2.2pF C

0.04

0.02

0

–0.02

OUTPUT VO LTAGE (V )

–0.04

–0.06

07685-019

–0.08

VS = 3.3V

TIME (1 0ns/DIV)

L

C

L

= 4.4pF = 6.6pF

07685-023

Figure 27. Small Signal Transient Response vs. Capacitive Load

23.7

23.2

0

–0.5

OUTPUT VOLT AGE (V)

–1.0

–1.5

TIME ( 10ns/DIV)

07685-021

Figure 25. Large Signal Transient Response vs. Load Resistance

Rev. 0 | Page 10 of 20

22.7

22.2

QUIESCENT CURRENT (mA)

21.7

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1

SUPPLY VOLTAGE (V)

Figure 28. Quiescent Current vs. Supply Voltage

4.3 4.7 4.9 5. 3 5.54.5 5.1

07685-029

ADA4855-3

www.BDTIC.com/ADI

4

2 × V

OUT

IN

TIME (50n s/DIV)

07685-025

3

2

1

0

–1

VOLTAGE (V)

–2

–3

–4

V

G = 2

Figure 29. Output Overdrive Recovery

0.6 V

= 1V p-p

OUT

V

= 3.3V

S

0.4

0.2

0

CL = 2.2pF C

= 4.4pF

L

C

= 6.6pF

L

2.0

1.5

1.0

0.5

VOLTAGE (V)

2.5

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

–2.5

0

2 × V

IN

V

OUT

0

G = 2 V

= 3.3V

IN

TIME (50n s/DIV)

07685-028

Figure 32. Output Overdrive Recovery

3

V

PD

V

OUT

2

1

0

–0.2

OUTPUT VO LTAGE (V)

–0.4

–0.6

TIME (10n s/DIV)

Figure 30. Large Signal Transient Response vs. Capacitive Load

0.5

0.4

0.3

0.2

0.1

0

–0.1

SETTLING TIME (%)

–0.2

–0.3

–0.4

–0.5

INPUT

ERROR

TIME (2ns/DIV)

Figure 31. Settling Time

–0.5

OUTPUT VO LTAGE (V )

–1.0

–1.5

07685-026

–2.0

TIME (1µs/DIV)

–1

POWER-DOW N VOLTAG E (V)

–2

07685-129

–3

Figure 33. Turn-On/Turn-Off Time

0.5

0.4

0.3

0.2

0.1

0

–0.1

SETTLING TIME (%)

–0.2

–0.3

VS = 3.3V

–0.4

07685-024

–0.5

INPUT

TIME (2ns/DIV)

ERROR

07685-027

Figure 34. Settling Time

Rev. 0 | Page 11 of 20

ADA4855-3

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0

–10

–20

–30

–40

OFFSET VO LTAGE (mV)

–50

–60

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

COMMON-MODE VOLTAGE (V)

VS = 3.3V

Figure 35. Input Offset Voltage vs. Common-Mode Voltage

23.6

23.4

23.2

23.0

22.8

22.6

22.4

QUIESCENT CURRENT (mA)

22.2

22.0

21.8 –40 –25 –10 5 20

VS = 5V

VS = 3.3V

35 65 80 110 12550 95

TEMPERATURE (°C)

Figure 36. Quiescent Current vs. Temperature

2.4

2.2

100

10

1

= 5V

V

S

07685-031

OUTPUT IM PEDANCE ()

0.1

0.01

0.1 1 10 100 1000 FREQUENCY (MHz)

07685-036

Figure 38. Output Impedance vs. Frequency

5.00

4.95

4.90

4.85

4.80

4.75

4.70

SATURATION VOLTAGE (mV)

4.65

4.60

0.01 0.1 1 10 100

07685-032

LOAD CURRENT (mA)

07685-039

Figure 39. Output Saturation Voltage vs. Load Current

2.0

1.8

1.6

1.4

OFFSET VO LTAGE (mV)

1.2

1.0 –40 –20 0 20 40 60 80 100

TEMPERATURE ( °C)

07685-034

Figure 37. Offset Drift vs. Temperature

Rev. 0 | Page 12 of 20

ADA4855-3

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TEST CIRCUITS

+

S

+

S

10µF

+

0.1µF

IN

49.9

10µF

+

–V

0.1µF

S

R

Figure 40. Noninverting Load Configuration

V

OUT

L

07685-041

V

IN

53.6

10µF

+

1k

10µF

+

–V

S

0.1µF 0.1µF

0.1µF

Figure 43. Common-Mode Rejection

V

OUT

R

L

07685-044

+

S

10µF

+

AC

49.9

V

OUT

R

L

0.1µF

–V

S

07685-042

Figure 41. Positive Power Supply Rejection

+

S

10µF

+

R

G

F

IN

49.9

10µF

+

0.1µF

C

L

0.1µF

–V

S

Figure 42. Typical Capacitive Load Configuration

Figure 44. Negative Power Supply Rejection

R

G

V

OUT

R

L

07685-043

IN

Figure 45. Typical Noninverting Gain Configuration

49.9

10µF

R

10µF

AC

+

S

+

0.1µF

V

OUT

R

49.9

–V

S

L

07685-045

+

S

+

F

–V

0.1µF

V

OUT

R

L

0.1µF

S

07685-046

Rev. 0 | Page 13 of 20

ADA4855-3

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THEORY OF OPERATION

The ADA4855 is a voltage feedback op amp that employs a new input stage that achieves a high slew rate while maintaining a wide common-mode input range. The input common-mode range of the ADA4855 extends from 200 mV below the negative rail to 1 V below the positive rail. This feature makes the ADA4855 ideal for single-supply applications. In addition, this new input stage does not sacrifice noise performance for slew rate. At

6.8 nV/√Hz, the ADA4855 is one of the lowest noise rail-torail output video amplifiers in the market.

Besides a novel input stage, the ADA4855 employs the Analog Devices, Inc., patented rail-to-rail output stage. This output stage makes efficient use of the power supplies, allowing the op amp to drive up to three video loads to within 350 mV of the positive power rail. In addition, this output stage provides the amplifier with very fast overdrive characteristics, which is an important property in video applications.

The ADA4855 comes in a 16-lead LFCSP that has an exposed thermal pad for lower operating temperature. This pad is internally connected to the negative rail. To avoid printed circuit board (PCB) layout problems, the ADA4855 features a new pinout flow that is optimized for video applications. As shown in Figure 4, the noninverting input and output pins of each amplifier are adjacent to each other for ease of layout.

The ADA4855 is fabricated in Analog Devices dielectrically isolated eXtra Fast Complementary Bipolar 3 (XFCB3) process, which results in the outstanding speed and dynamic range displayed by the amplifier.

+

+IN

–IN

S

G

m1

–V

S

Figure 46. High Level Design Schematic

C

1

G

m2

R

C

OUT

07685-147

Rev. 0 | Page 14 of 20

ADA4855-3

V

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APPLICATIONS INFORMATION

GAIN CONFIGURATIONS

The ADA4855-3 is a single-supply, high speed, voltage feedback amplifier. Tabl e 6 provides a convenient reference for quickly determining the feedback and gain set resistor values and bandwidth for common gain configurations.

Table 6. Recommended Values and Frequency Performance

−3 dB SS

Gain RF RG

BW (MHz)

1 0 Ω N/A 200 53 2 1 kΩ 1 kΩ 120 50 5 1 kΩ 200 Ω 45 6

1

Conditions: VS = 5 V, TA = 25°C, RL = 150 Ω.

Figure 47 and Figure 48 show the typical noninverting and inverting configurations and recommended bypass capacitor values.

+

S

10µF

0.1µF

V

IN

+

ADA4855-3

–

R

F

R

G

0.1µF

10µF

–V

S

Figure 47. Noninverting Gain Configuration

R

F

+V

S

R

G

V

IN

–

ADA4855-3

+

–V

S

0.1µF

Large Signal 0.1 dB Flatness (MHz)

0.1µF

10µF

0.1µF

10µF

V

OUT

07685-047

V

OUT

1

20 MHz ACTIVE LOW-PASS FILTER

The ADA4855-3 triple amplifier lends itself to higher order active filters. Figure 49 shows a 20 MHz, 6-pole, Sallen-Key low-pass filter.

R7

1k

R1

232R21.69k

V

IN

C1 15pF

R3

309R41.87k

Figure 49. 20 MHz, 6-Pole Low-Pass Filter

The filter has a gain of approximately 6 dB and flat frequency response out to 14 MHz. This type of filter is commonly used at the output of a video DAC as a reconstruction filter. The frequency response of the filter is shown in Figure 50.

10

0

–10

–20

–30

–40

MAGNITUDE (d B)

–50

R8

261

–

U1

OP AMP

+

C2

6.6pF

R9

1k

C4

C3

4.3pF

15pF

R5

261R61.43k

C5 33pF

OUT2

–

OP AMP

+

R11

1k

OUT1

R10

261

U2

C6 3pF

OUT2

R12

261

–

U3

OP AMP

+

OUT3

V

OUT

07685-049

07685-048

Figure 48. Inverting Gain Configuration

Rev. 0 | Page 15 of 20

–60

–70

1

10 100

FREQUENCY (MHz )

Figure 50. 20 MHz, Low-Pass Filter Frequency Response

200

07685-050

ADA4855-3

www.BDTIC.com/ADI

RGB VIDEO DRIVER

Figure 51 shows a typical RGB driver application using dual supplies. The gain of the amplifier is set at +2, where R

= RG =

F

1 kΩ. The amplifier inputs are terminated with shunt 75 Ω resistors, and the outputs have series 75 Ω resistors for proper video matching. In Figure 51, the

pin is not shown connected

PD

to any signal source for simplicity. If the power-down function is not used, it is recommended that the

pin be tied to the

PD

positive supply or be left floating (not connected).

75 1k

(R)

V

IN

16 15 14 13

1

(G)

V

IN

V

(B)

IN

75

PD

2

3

4

ADA4855-3

5 6 7 8

75 1k

Figure 51. RGB Video Driver

1k

75

–V

75

V

(R)

OUT

S

10µF

+

0.1µF

(B)

+V

1k

+V

0.1µF

S

0.1µF

75

1k

+

V

OUT

10µF

(G)

07685-051

0.1µF

12

11

10

9

0.1µF

S

V

OUT

DRIVING MULTIPLE VIDEO LOADS

Each amplifier in the ADA4855-3 can drive up to three video loads simultaneously, as shown in Figure 52. When driving three video loads, the ADA4855-3 maintains its excellent performance for 0.1 dB flatness and 3 dB bandwidth. Figure 53 shows the large signal frequency response of the ADA4855-3 with three different load configurations: 150 Ω, 75 Ω and 50 Ω.

R

F

1k

75

10µF

+V

S

R

1k

G

–

0.1µF

ADA4855-3

0.1µF

10µF

75

+

–V

S

75

CABLE

V

IN

Figure 52. Video Driver Schematic for Triple Video Loads

75

CABLE

75

CABLE

75

CABLE

75

V

1

OUT

V

2

OUT

V

3

OUT

6.5

6.0

5.5

5.0

4.5

AGNITUDE (dB)

4.0

M

V

=2V p-p

OUT

3.5 G = 2

3.0

2.5

110

FREQUENCY (MHz)

RL=150 R

=75

L

R

=50

L

07685-153

200

100

Figure 53. Large Signal Frequency Response vs. Loads

(POWER-DOWN) PIN

PD

The ADA4855-3 is equipped with a PD (power-down) pin for all three amplifiers. This allows the user to reduce the

quiescent supply current when an amplifier is inactive. The power-down threshold levels are derived from the voltage applied to the +V

pin. When used in single-supply applications,

S

this is especially useful with conventional logic levels. The amplifier is enabled when the voltage applied to the

greater than +V

− 1.25 V. In a single-supply application, the

S

PD

pin is

voltage threshold is typically +3.75 V, and in a ±2.5 V dualsupply application, the voltage threshold is typically +1.25 V. The amplifier is also enabled when the

pin is left floating (not

PD connected). However, the amplifier is powered down when the voltage on the

pin is lower than 2.5 V from +VS. If the PD

PD

pin is not used, it is best to connect it to the positive supply.

Table 7. Power-Down Voltage Control

Pin 5 V ±2.5 V 3 V

PD

Not Active >3.75 V >1.25 V >1.75 V Active <2 V <0 V <1 V

07685-052

Rev. 0 | Page 16 of 20

ADA4855-3

V

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SINGLE-SUPPLY OPERATION POWER SUPPLY BYPASSING

The ADA4855-3 is designed for a single power supply. Figure 54 shows the schematic for a single 5 V supply video driver. The input signal is ac-coupled into the amplifier via C1. Resistor R2 and Resistor R4 establish the input midsupply reference for the amplifier. C5 prevents constant current from being drawn through the gain set resistor. C6 is the output coupling capacitor. For more information on ac-coupled single-supply operation of op amps, see Avoiding Op-Amp Instability Problems in Single- Supply Applications, Analog Dialogue, Volume 35, Number 2, March-May, 2001, at www.analog.com.

R6

1k

5

C3

10µF

C4

0.01µF

C6

–V

S

220µF

R7

75

ADA4855-3

U1

R8 75

V

OUT

07685-155

C2

1µF

R4

R2

50k

5V

R3

1k

V

IN

75

C1

R1

22µF

R5

1k

C5

22µF

Figure 54. AC-Coupled, Single-Supply Video Driver Schematic

Another way to configure the ADA4855-3 in single-supply operation is dc-coupled. The common-mode input voltage can go ~200 mV below ground, which makes it a true single-supply amplifier. However, in video applications, the black level is set at 0 V, which means that the output of the amplifier must go to ground level as well. The ADA4855-3 has a rail-to-rail output that can swing to within 100 mV from either rail. Figure 55 shows the schematic for adding 50 mV dc offset to the input signal so that the output is not clipped while still properly terminating the input with 75 Ω.

5

C1

V

3.74k

IN

76.8

10µF

5V

R1

R2

R3

1k

C2

0.1µF

U1

R4

–V

S

R5

75

ADA4855-3

R6 75

V

OUT

Careful attention must be paid to bypassing the power supply pins of the ADA4855-3. High quality capacitors with low equivalent series resistance (ESR), such as multilayer ceramic capacitors (MLCCs), should be used to minimize supply voltage ripple and power dissipation. A large, usually tantalum, 2.2 μF to 47 μF capacitor located in close proximity to the ADA4855-3 is required to provide good decoupling for lower frequency signals. The actual value is determined by the circuit transient and frequency requirements. In addition, 0.1 μF MLCC decoupling capacitors should be located as close to each of the power supply pins and across both supplies as is physically possible, no more than 1/8-inch away. The ground returns should terminate immediately into the ground plane. Locating the bypass capacitor return close to the load return minimizes ground loops and improves performance.

LAYOUT

As is the case with all high speed applications, careful attention to printed circuit board (PCB) layout details prevents associated board parasitics from becoming problematic. The ADA4855-3 can operate at up to 410 MHz; therefore, proper RF design techniques must be employed. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance return path. Removing the ground plane on all layers from the area near and under the input and output pins reduces stray capacitance. Signal lines connecting the feedback and gain resistors should be kept as short as possible to minimize the inductance and stray capacitance associated with these traces. Termination resistors and loads should be located as close as possible to their respective inputs and outputs. Input and output traces should be kept as far apart as possible to minimize coupling (crosstalk) through the board. Adherence to microstrip or stripline design techniques for long signal traces (greater than 1 inch) is recommended. For more information on high speed board layout, see A Practical Guide to High-Speed Printed-Circuit-Board Layout, Analog Dialogue, Volume 39, September 2005, at www.analog.com.

07685-156

Figure 55. DC-Coupled, Single-Supply Video Driver Schematic

Rev. 0 | Page 17 of 20

ADA4855-3

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING PLANE

4.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.35

0.30

0.25

3.75

BSC SQ

0.20 REF

0.60 MAX

0.65 BSC

0.05 MAX

0.02 NOM

COPLANARITY

0.75

0.60

0.50

0.08

0.60 MAX

(BOTTO M VIEW )

16

13

12

9

8

5

1.95 BSC

FOR PROPER CO NNECTION O F THE EXPOSED PAD, REFER TO THE PIN CONF IGURATIO N AND FUNCTION DES CRIPTIONS SECTION O F THIS DAT A SHEET.

PIN 1 INDICATOR

1

4

5

2

.

2

0

1

.

2

9

.

1

5

0.25 MIN

Q

S

COMPLIANT TO JEDEC STANDARDS MO-220-VGGC

072808-A

Figure 56.16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad (CP-16-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Ordering Quantity

ADA4855-3YCPZ-R2 ADA4855-3YCPZ-R7 ADA4855-3YCPZ-RL

1

Z = RoHS Compliant Part.

1

–40°C to +105°C 16-Lead LFCSP_VQ CP-16-4 1,500

1

–40°C to +105°C 16-Lead LFCSP_VQ CP-16-4 5,000

–40°C to +105°C 16-Lead LFCSP_VQ CP-16-4 250

Rev. 0 | Page 18 of 20

ADA4855-3

www.BDTIC.com/ADI

NOTES

Rev. 0 | Page 19 of 20

ADA4855-3

www.BDTIC.com/ADI

NOTES

Rev. 0 | Page 20 of 20

ANALOG DEVICES ADA4855-3 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

CONNECTION DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

5 V OPERATION

3.3 V OPERATION

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

MAXIMUM POWER DISSIPATION

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUITS

THEORY OF OPERATION

APPLICATIONS INFORMATION

GAIN CONFIGURATIONS

20 MHz ACTIVE LOW-PASS FILTER

RGB VIDEO DRIVER

DRIVING MULTIPLE VIDEO LOADS

(POWER-DOWN) PIN

SINGLE-SUPPLY OPERATION POWER SUPPLY BYPASSING

LAYOUT

OUTLINE DIMENSIONS

ORDERING GUIDE