Low Power, Low Noise and Distortion,
A
V
–
www.BDTIC.com/ADI
FEATURES
Low power: 1.1 mA/amp
Low wideband noise
2.1 nV/√Hz
1.4 pA/√Hz
Low 1/f noise
7 nV/√Hz @ 10 Hz
13 pA/√Hz @ 10 Hz
Low distortion: −105 dBc @ 100 kHz, V
High speed
80 MHz, −3 dB bandwidth (G = +1)
12 V/μs slew rate
175 ns settling time to 0.1%
Low offset voltage: 0.3 mV maximum
Rail-to-rail output
Power down
Wide supply range: 2.7 V to 12 V
APPLICATIONS
Low power, low noise signal processing
Battery-powered instrumentation
16-bit PulSAR® ADC drivers
GENERAL DESCRIPTION
= 2 V p-p
O
Rail-to-Rail Output Amplifier
ADA4841-1/ADA4841-2
CONNECTION DIAGRAMS
DA4841-1
TOP VIEW
NC
18
(Not to Scale)
–IN
27
+IN
3
–V
4
S
Figure 1. 8-Lead SOIC (R)
ADA4841-2
1
OUT1
2
–IN1
+IN1
3
–V
4
S
(Not to Scale)
Figure 2. 8-Lead MSOP (RM-8) and 8-Lead SOIC_N (R)
ADA4841-1
1
OUT
2
–V
S
3
+IN
Figure 3. 6-Lead SOT-23 (RJ)
6
5
TOP VIEW
6
5
4
POWER DOWN
+V
S
V
OUT
NC
8
+V
S
7
OUT2
–IN2
6
+IN2
5
+V
S
POWER DOWN
–IN
5614-064
05614-001
05614-099
The ADA4841-1/ADA4841-2 are unity gain stable, low
noise and distortion, rail-to-rail output amplifiers that have a
quiescent current of 1.5 mA maximum. Despite their low power
consumption, these amplifiers offer low wideband voltage noise
performance of 2.1 nV/√Hz and 1.4 pA/√Hz current noise,
along with excellent spurious-free dynamic range (SFDR) of
−105 dBc at 100 kHz. To maintain a low noise environment at
lower frequencies, the amplifiers have low 1/f noise of 7 nV/√Hz
and 13 pA/√Hz at 10 Hz.
The ADA4841-1/ADA4841-2 output can swing to less than
50 mV o
f either rail. The input common-mode voltage range
extends down to the negative supply. The ADA4841-1/
ADA4841-2 can drive up to 10 pF of capacitive load with
minimal peaking.
The ADA4841-1/ADA4841-2 provide the performance required
o efficiently support emerging 16-bit to 18-bit ADCs and are
t
ideal for portable instrumentation, high channel count, industrial
measurement, and medical applications. The ADA4841-1/
ADA4841-2 are ideally suited to drive the AD7685/AD7686,
16-b
it PulSAR ADCs.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The ADA4841-1/ADA4841-2 packages feature Pb-free lead
f
inish. The amplifiers are rated to work over the industrial
temperature range (−40°C to +125°C).
30
VS = ±5V
G = +1
–40
–50
–60
–70
–80
–90
HARMONIC DIS TORTION (dBc)
–100
–110
–120
2V p-p SECOND
0.01 1
FREQUENCY (MHz)
Figure 4. Harmonic Distortion
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
2V p-p THIRD
0.1
05614-048
ADA4841-1/ADA4841-2
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features .............................................................................................. 1
Headroom Considerations........................................................ 14
Applications....................................................................................... 1
Connection Diagrams...................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Typical Performance Characteristics............................................. 7
Theory of Operation ...................................................................... 13
Amplifier Description................................................................ 13
DC Errors.................................................................................... 13
Noise Considerations................................................................. 13
REVISION HISTORY
3/06—Rev. B to Rev. C
Added SOT-23 Package .....................................................Universal
Changes to General Description .................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 5
Changes to Input Protection Section ........................................... 15
Changes to Ordering Guide.......................................................... 20
10/05—Rev. A to Rev. B
dded ADA4841-2.............................................................Universal
A
Changes to General Description and Features ............................. 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 5
Changes to Table 4, Table 5, and Figure 4..................................... 6
Changes to Figure 6.......................................................................... 7
Changes to Figure 12, Figure 13, Figure 15, and Figure 16......... 8
Deleted Figure 25; Renumber Sequentially................................. 10
Changes to Figure 24 and Figure 28............................................. 10
Changes to Figure 31...................................................................... 11
Inserted Figure 37; Renumber Sequentially................................ 12
Changes to Amplifier Description Section and Figure 39........ 13
Capacitance Drive...................................................................... 15
Input Protection ......................................................................... 15
Power-Down Operation ............................................................ 16
Applications..................................................................................... 17
Typical Performance Values...................................................... 17
16-Bit ADC Driver..................................................................... 17
Reconstruction Filter................................................................. 17
Layout Considerations............................................................... 18
Ground Plane.............................................................................. 18
Power Supply Bypassing............................................................ 18
Outline Dimensions .......................................................................19
Ordering Guide .......................................................................... 20
Changed DC Performance Considerations Section
t
o DC Errors Section...................................................................... 13
Changes to Noise Considerations Section .................................. 14
Changes to Headroom Considerations Section and Figure 39 15
Changes to Power-Down Operation Section.............................. 16
Changes to 16-Bit ADC Driver Section,
Figure 48, and Figure 49................................................................ 17
Changes to Power Supply Bypassing Section ............................. 18
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide.......................................................... 20
9/05—Rev. 0 to Rev. A
hanges to Features ..........................................................................1
C
Changes to Figure 2...........................................................................1
Changes to Figure 12.........................................................................8
Changes to Figure 40...................................................................... 14
Changes to Headroom Considerations Section ......................... 15
7/05—Revision 0: Initial Version
Rev. C | Page 2 of 20
ADA4841-1/ADA4841-2
www.BDTIC.com/ADI
SPECIFICATIONS
TA = 25°C, VS = ±5 V, RL = 1 kΩ, Gain = +1, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth VO = 0.02 V p-p 58 80 MHz
V
Slew Rate G = +1, VO = 9 V step, RL = 1 kΩ 12 13 V/μs
Settling Time to 0.1% G = +1, VO = 8 V step 650 ns
Settling Time to 0.01% G = +1, VO = 8 V step 1000 ns
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion HD2/HD3 fC = 100 kHz, VO = 2 V p-p, G = +1 −111/−105 dBc
f
Input Voltage Noise f = 100 kHz 2.1 nV/√Hz
Input Current Noise f = 100 kHz 1.4 pA/√Hz
DC PERFORMANCE
Input Offset Voltage 40 300 μV
Input Offset Voltage Drift 1 μV/°C
Input Bias Current 3 5.3 μA
Input Offset Current 0.1 0.5 μA
Open-Loop Gain VO = ±4 V 103 120 dB
INPUT CHARACTERISTICS
Input Resistance, Common Mode 90 MΩ
Input Resistance, Differential Mode 25 kΩ
Input Capacitance, Common Mode 1 pF
Input Capacitance, Differential Mode 3 pF
Input Common-Mode Voltage Range −5.1 +4 V
Common-Mode Rejection Ratio (CMRR) VCM = Δ 4 V 95 115 dB
MATCHING CHARACTERISTICS (ADA4841-2)
Input Offset Voltage 70 μV
Input Bias Current 60 nA
POWER DOWN PIN (ADA4841-1)
POWER DOWN Voltage
POWER DOWN Voltage
Input Current
Enable
Power Down
Switching Speed
Enable 1 μs
Power Down 40 μs
OUTPUT CHARACTERISTICS
Output Voltage Swing G > +1 ±4.9 ±4.955 V
Output Current Limit Sourcing, VIN = +VS , RL = 50 Ω to GND 30 mA
Sinking, VIN = −VS , RL = 50 Ω to GND 60 mA
Capacitive Load Drive 30% overshoot 15 pF
POWER SUPPLY
Operating Range 2.7 12 V
Quiescent Current/Amplifier
Positive Power Supply Rejection Ratio +VS = +5 V to +6 V, −VS = −5 V 95 110 dB
Negative Power Supply Rejection Ratio +VS = +5 V, −VS = −5 V to +6 V 96 120 dB
= 2 V p-p 3 MHz
O
= 1 MHz, VO = 2 V p-p −80/−67 dBc
C
Enabled >3.6 V
Power down <3.2 V
POWER DOWN
POWER DOWN
POWER DOWN
POWER DOWN
Rev. C | Page 3 of 20
= +5 V
= −5 V
= +5 V
= −5 V
1 2 μA
−13 −30 μA
1.2 1.5 mA
40 90 μA
ADA4841-1/ADA4841-2
www.BDTIC.com/ADI
TA = 25°C, VS = 5 V, RL = 1 kΩ, Gain = +1, VCM = 2.5 V, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth VO = 0.02 V p-p 54 80 MHz
V
Slew Rate G = +1, VO = 4 V step, RL = 1 kΩ 10 12 V/μs
Settling Time to 0.1% G = +1, VO = 2 V step 175 ns
Settling Time to 0.01% G = +1, VO = 2 V step 550 ns
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion HD2/HD3 fC = 100 kHz, VO = 2 V p-p −109/−105 dBc
f
Input Voltage Noise f = 100 kHz 2.1 nV/√Hz
Input Current Noise f = 100 kHz 1.4 pA/√Hz
Crosstalk f = 100 kHz −117 dB
DC PERFORMANCE
Input Offset Voltage 40 300 μV
Input Offset Voltage Drift 1 μV/°C
Input Bias Current 3 5.3 μA
Input Offset Current 0.1 0.4 μA
Open-Loop Gain VO = 0.5 V to 4.5 V 103 124 dB
INPUT CHARACTERISTICS
Input Resistance, Common Mode 90 MΩ
Input Resistance, Differential Mode 25 kΩ
Input Capacitance, Common Mode 1 pF
Input Capacitance, Differential Mode 3 pF
Input Common-Mode Voltage Range −0.1 +4 V
Common-Mode Rejection Ratio (CMRR) VCM = Δ 1.5 V 88 115 dB
MATCHING CHARACTERISTICS (ADA4841-2)
Input Offset Voltage 70 μV
Input Bias Current 70 nA
POWER DOWN PIN (ADA4841-1)
POWER DOWN Voltage
POWER DOWN Voltage
Input Current
Enable
Power Down
Switching Speed
Enable 1 μs
Power Down 40 μs
OUTPUT CHARACTERISTICS
Output Voltage Swing G > +1 0.08 to 4.92 0.029 to 4.974 V
Output Current Limit Sourcing, VIN = +VS, RL = 50 Ω to V
Sinking, VIN = −VS, RL = 50 Ω to V
Capacitive Load Drive 30% overshoot 15 pF
POWER SUPPLY
Operating Range 2.7 12 V
Quiescent Current/Amplifier
Positive Power Supply Rejection Ratio +VS = +5 V to +6 V, −VS = 0 V 95 110 dB
Negative Power Supply Rejection Ratio +VS = +5 V, −VS = 0 V to −1 V 96 120 dB
= 2 V p-p 3 MHz
O
= 1 MHz, VO = 2 V p-p −78/−66 dBc
C
Enabled >3.6
Power down <3.2 V
POWER DOWN
POWER DOWN
POWER DOWN
POWER DOWN
= 5 V
= 0 V
CM
= 5 V
= 0 V
1 2 μA
−13 −30 μA
30 mA
CM
60 mA
1.1 1.4 mA
35 70 μA
Rev. C | Page 4 of 20
ADA4841-1/ADA4841-2
www.BDTIC.com/ADI
TA = 25°C, VS = 3 V, RL = 1 kΩ, Gain =+1, VCM = 1.5 V, unless otherwise noted.
Table 3.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth VO = 0.02 V p-p 52 80 MHz
Slew Rate G = +1, VO = 2 V step, RL = 1 kΩ 10 12 V/μs
Settling Time to 0.1% G = +1, VO = 1 V step 120 ns
Settling Time to 0.01% G = +1, VO = 1 V step 250 ns
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion HD2/HD3 fC = 100 kHz, VO = 1 V p-p −97/−100 dBc
f
Input Voltage Noise f = 100 kHz 2.1 nV/√Hz
Input Current Noise f = 100 kHz 1.4 pA/√Hz
DC PERFORMANCE
Input Offset Voltage 40 300 μV
Input Offset Voltage Drift 1 μV/°C
Input Bias Current 3 5.3 μA
Input Offset Current 0.1 0.5 μA
Open-Loop Gain VO = 0.5 V to 2.5 V 101 123 dB
INPUT CHARACTERISTICS
Input Resistance, Common Mode 90 MΩ
Input Resistance, Differential Mode 25 kΩ
Input Capacitance, Common Mode 1 pF
Input Capacitance, Differential Mode 3 pF
Input Common-Mode Voltage Range −0.1 +2 V
Common-Mode Rejection Ratio (CMRR) VCM = Δ 0.4 V 86 115 dB
MATCHING CHARACTERISTICS (ADA4841-2)
Input Offset Voltage 70 μV
Input Bias Current 60 nA
POWER DOWN PIN (ADA4841-1)
POWER DOWN Voltage
POWER DOWN Voltage
Input Current
Enable
Power Down
Switching Speed
Enable 1 μs
Power Down 40 μs
OUTPUT CHARACTERISTICS
Output Voltage Swing G > +1 0.045 to 2.955 0.023 to 2.988 V
Output Current Limit Sourcing, VIN = +VS, RL = 50 Ω to V
Sinking, VIN = −VS, RL = 50 Ω to V
Capacitive Load Drive 30% overshoot 30 pF
POWER SUPPLY
Operating Range 2.7 12 V
Quiescent Current/Amplifier
Positive Power Supply Rejection Ratio +VS = +3 V to +4 V, −VS = 0 V 95 110 dB
Negative Power Supply Rejection Ratio +VS = +3 V, −VS = 0 V to −1 V 96 120 dB
= 1 MHz, VO = 1 V p-p −79/−80 dBc
C
Enabled >1.6
Power down <1.2 V
POWER DOWN
POWER DOWN
POWER DOWN
POWER DOWN
= 3 V
= 0 V
CM
= 3 V
= 0 V
1 2 μA
−10 −30 μA
30 mA
CM
60 mA
1.1 1.3 mA
25 60 μA
Rev. C | Page 5 of 20
ADA4841-1/ADA4841-2
(
)
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage 12.6 V
Power Dissipation See Figure 5
Common-Mode Input Voltage −VS − 0.5 V to +VS + 0.5 V
Differential Input Voltage
±1.8 V
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature JEDEC J-STD-20
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for device soldered in circuit board for surface-mount
packages.
Table 5. Thermal Resistance
Package Type θ
JA
Unit
8-lead SOIC_N 125 °C/W
8-lead MSOP 130 °C/W
6-Lead SOT-23 170 °C/W
Maximum Power Dissipation
The maximum safe power dissipation for the ADA4841-1/
ADA4841-2 is limited by the associated rise in junction
temperature (T
) on the die. At approximately 150°C, which is
J
the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
may change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
amplifiers. Exceeding a junction temperature of 150°C for an
extended period can result in changes in silicon devices,
potentially causing degradation or loss of functionality.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 6 of 20
The power dissipated in the package (P
) is the sum of the
D
quiescent power dissipation and the power dissipated in the die
due to the amplifier’s drive at the output. The quiescent power is
the voltage between the supply pins (V
current (I
).
S
= Quiescent Power + (Total Drive Power − Load Power)
P
D
⎛
V
V
OUTS
()
D
⎜
IVP
SS
×+×=
⎜
R
2
⎝
L
) times the quiescent
S
⎞
⎟
⎟
⎠
2
V
OUT
−
R
L
RMS output voltages should be considered. If RL is referenced
to −V
, as in single-supply operation, the total drive power is
S
× I
V
worst case, when V
In single-supply operation with R
is V
Airflow increases heat dissipation, effectively reducing θ
. If the rms signal levels are indeterminate, consider the
S
OUT
= VS/4 for RL to midsupply.
OUT
2
4/
V
()
D
= VS/2.
OUT
+×=
IVP
SS
S
R
L
referenced to −VS, worst case
L
.
JA
In addition, more metal directly in contact with the package
leads and through holes under the device reduces θ
.
JA
Figure 5 shows the maximum safe power dissipation in the
ackage vs. the ambient temperature for the 8-lead MSOP
p
(145°C/W), 8-lead SOIC_N (125°C/W) and the 6-lead SOT-23
(170°C/W) on a JEDEC standard 4-layer board. θ
values are
JA
approximations.
2.0
1.5
SOIC
1.0
0.5
MAXIMUM POWER DISSIPATION (W)
0
–55 125
–45–35–25–15–5 5 152535455565758595105115
Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
AMBIENT TEMPERATURE (°C)
MSOP
SOT-23
05614-061
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