ANALOG DEVICES ADA4830-1, ADA4830-2 Service Manual

High Speed Difference Amplifier with Input

Short-to-Battery Protection

ADA4830-1/ADA4830-2

Rev. C

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STBENA +VS

GND

+VS

R/2

R

R/2

R

INN

INP

VREF

×1

VOUT

ADA4830-1

10020-001

STB1ENA1 +VS1

STB2ENA2 +VS2

GND2

GND1

+VS

R/2

R

R/2

R

INN1

INP1

VREF1

×1

VOUT1

VOUT2

ADA4830-2

+VS

10020-102

R

R/2

R

INN2

INP2

VREF2

×1

R/2

Data Sheet

FEATURES

Input overvoltage (short-to-battery) protection of up to 18 V
Short-to-battery output flag for wire diagnostics
Wide input common-mode range with single 5 V supply
High performance video amplifier with 0.50 V/V gain

−3 dB bandwidth of 84 MHz
250 V/µs slew rate (2 V step)

Excellent video specifications

0.1 dB flatness to 28 MHz
SNR of 73 dB to 15 MHz

Differential gain/phase of 0.1%/0.1°
Wide supply range: 2.9 V to 5.5 V
Enable/output disable mode
Space saving 3 mm × 3 mm LFCSP package
Wide operating temperature range: −40°C to +125°C
Qualified for automotive applications

APPLICATIONS

Automotive vision systems
Automotive infotainment
Surveillance systems

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The ADA4830-1 (single) and ADA4830-2 (dual) are monolithic,
high speed difference amplifiers that integrate input overvoltage
(short-to-battery) protection of up to 18 V with a wide input
common-mode voltage range and excellent ESD robustness.
They are intended for use as receivers for differential or pseudo
differential CVBS and other high speed video signals in harsh,
noisy environments such as automotive infotainment and vision
systems. The ADA4830-1 and ADA4830-2 combine high speed
and precision, which allows for accurate reproduction of CVBS
video signals, yet rejects unwanted common-mode error voltages.

The short-to-battery protection that is integrated into the

ADA4830-1 and ADA4830-2 employs fast switching circuitry to

clamp and hold internal voltage nodes at a safe level when an input
overvoltage condition is detected. This protection allows the inputs
of the ADA4830-1 and ADA4830-2 to be directly connected to a
remote video source, such as a rearview camera, without the
need for large expensive series capacitors. The ADA4830-1 and

ADA4830-2 can withstand direct short-to-battery voltages as

high as 18 V on their input pins.

The ADA4830-1 and ADA4830-2 are designed to operate at supply
voltages as low as 2.9 V and as high as 5.5 V, using only 6.8 mA
of supply current per channel. These devices provide true single­supply capability, allowing the input signal to extend 8.5 V

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Figure 2.

below ground rail and to 8.5 V above ground on a single 5 V
supply. At the output, the amplifier can swing to within 250 mV
of either supply rail into a 150 Ω load.

The ADA4830-1 and ADA4830-2 present a gain of 0.50 V/V at their
output. This is designed to keep the video signal within the allowed
range of the video decoder, which is typically 1 V p-p or less.

The ADA4830-1W and ADA4830-2W are automotive grade
version, qualified for automotive applications. See the
Automotive Products section for more details.

The ADA4830-1 and ADA4830-2 are available in 3 mm × 3 mm
LFCSP packages, 8-lead and 16-lead, respectively, and are specified
for operation over the automotive temperature range of −40°C
to +125°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

ADA4830-1/ADA4830-2 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

5 V Operation ............................................................................... 3

3.3 V Operation ............................................................................ 4

Absolute Maximum Ratings ....................................................... 6

Thermal Resistance ...................................................................... 6

Maximum Power Dissipation ..................................................... 6

ESD Caution .................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 13

Core Amplifier ............................................................................ 13

Overvoltage (Short-to-Battery) Protection ............................. 13

Short-to-Battery Output Flag ................................................... 13

ESD Protection ........................................................................... 13

Power Supply Pins (ADA4830-2).............................................. 13

Applications Information .............................................................. 14

Methods of Transmission .......................................................... 14

Voltage Reference (VREF Pin) ................................................. 14

Input Common-Mode Range ................................................... 15

Short-to-Battery Output Flag Pin ............................................ 15

Enable/Disable Modes (ENA Pin) ........................................... 15

PCB Layout ................................................................................. 15

Exposed Paddle (EPAD) Connection ...................................... 15

Using the ADA4830-2 as a Low Cost Video Switch ............... 16

Driving Capacitive Loads .......................................................... 17

Typical Applications Circuits ........................................................ 18

Fully DC-Coupled Transmission Line .................................... 20

Packaging and Ordering Information ......................................... 21

Outline Dimensions ................................................................... 21

Ordering Guide .......................................................................... 21

Automotive Products ................................................................. 22

REVISION HISTORY

6/12—Rev. B to Rev. C

Added ADA4830-2W......................................................... Universal

Changes to Features ..................................................................................... 1

Changes to Ordering Guide ..................................................................... 21

4/12—Rev. A to Rev. B

Changes to Features Section and Generation Description Section . 1

Changes to Table 1 ....................................................................................... 3

Changes to Table 2 ....................................................................................... 4

Changes to Table 4 ....................................................................................... 6

Changes to Figure 28 ................................................................................. 12

Changes to ESD Protection Section ....................................................... 13

Changes to Ordering Guide ..................................................................... 21

Added Automotive Products Section .................................................... 22

1/12—Rev. 0 to Rev. A

Added ADA4830-2 ............................................................. Universal

Changes to Features Section and Figure 1..................................... 1

Added Figure 2; Renumbered Sequentially .................................. 1

Changes to Table 1 ............................................................................ 3

Changes to Table 2 ............................................................................ 4

Added Supply Voltage Delta Parameter, Table 3; Renumbered

Sequentially ....................................................................................... 5

Added Figure 5 and Table 6 ............................................................. 7

Changes to Typical Performance Characteristics Section ........... 8

Added Figure 23 ............................................................................. 10

Added Figure 24 to Figure 29 ....................................................... 11

Changes to Pseudo Differential Mode (Unbalanced Source
Termination) Section, Fully Differential Mode Section, and

Voltage Reference (VREF Pin) Section ....................................... 13

Changes to Input Common-Mode Range Section, Table 7,

Short-to-Battery Output Flag Pin Section, and Table 9 ............ 14

Added Figure 34 ............................................................................. 15

Added Driving Capacitive Loads Section and Figure 35 to

Figure 38 .......................................................................................... 16

Changes to Figure 39 and Figure 40 ............................................. 17

Changes Typical Application Circuits Section and Figure 41 ......... 18

Added Fully DC-Coupled Transmission Line Section ..................... 19

Changes to Figure 42 ................................................................................. 19

Updated Outline Dimensions ....................................................... 20

Changes to Ordering Guide .......................................................... 20

10/11—Revision 0: Initial Version

Rev. C | Page 2 of 22

Data Sheet ADA4830-1/ADA4830-2

Common-Mode Rejection (CMR)

VIN = ±5 V

42

65 dB

ADA4830-1W/ADA4830-2W only T

to T

−9 +20

V

SPECIFICATIONS

5 V OPERATION

TA = 25°C, +VS = 5 V, RL = 1 kΩ, V

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Large Signal Bandwidth V

ADA4830-1W/ADA4830-2W only T

V

V

ADA4830-1W/ADA4830-2W only T

Bandwidth for 0.1 dB Flatness V

Slew Rate (tR/tF) V

ADA4830-1W/ADA4830-2W only T

Settling Time to 0.1% V
NOISE/DISTORTION PERFORMANCE

Output Voltage Noise f = 1 MHz 28 nV/√Hz

Differential Gain Error (NTSC) RL = 150 Ω, VIN = 1 V p-p 0.1 %

Differential Phase Error (NTSC) RL = 150 Ω, VIN = 1 V p-p 0.1

Signal-to-Noise Ratio f = 100 kHz to 15 MHz, V
DC PERFORMANCE

Nominal Gain VIN to V

ADA4830-1W/ADA4830-2W only T

Output Bias Voltage 2.45 2.50 2.55 V

ADA4830-1W/ADA4830-2W only T
INPUT CHARACTERISTICS

Input Resistance (Differential Mode) 6.7 kΩ

Input Resistance (Common Mode) 2 kΩ

Input Common-Mode Voltage Range V

ADA4830-1W/ADA4830-2W only T

= 2.5 V (floating), V

REF

= 0.5 V p-p, RL = 150 Ω 64 71 MHz

OUT

= 0.1 V p-p, RL = 1 kΩ 84 MHz

OUT

= 0.1 V p-p, RL = 150 Ω 65 74 MHz

OUT

= 0.5 V p-p, RL = 150 Ω 28 MHz

OUT

= 2 V step 196/200 250/300 V/µs

OUT

= 2 V step 25 ns

OUT

OUT

voltage adjusted to optimized range −10 +9.5 V

REF

= +VS/2, R

INCM

OUT

= 5 kΩ to +VS, unless otherwise specified.

STB

MIN

MIN

MIN

to T

MAX

to T

60 MHz

MAX

to T

164/220 V/µs

MAX

56 MHz

Degrees

= 0.5 V p-p 73 dB

0.49 0.50 0.51 V/V
to T

MIN

MIN

MIN

0.49 0.51 V/V

MAX

to T

2.44 2.56 V

MAX

to T

−10 +9.5 V

MAX

ADA4830-1W/ADA4830-2W only T

MIN

to T

42 dB

MAX

SHORT-TO-BATTERY CHARACTERISTICS

Input Current VIN = 18 V (short-to-battery) 4.1 mA
Protected Input Voltage Range −9 +20 V

MIN

MAX

Short-to-Battery Output Flag Trigger

Level

ADA4830-1W/ADA4830-2W only T

Minimum VIN needed to signal an input fault
condition

to T

MIN

MAX

9.8 10.3 10.8 V

9.8 10.8 V

VOLTAGE REFERENCE INPUT

Input Voltage Range 0.2 to 3.9 V
Input Resistance 20 kΩ
Gain V

REF

to V

1 V/V

OUT

LOGIC OUTPUT/INPUT CHARACTERISTICS

STB V

OH

VIN ≤ 9.8 V (normal operation) 5.0 V
STB VOL VIN ≥ 10.8 V (fault condition), ADA4830-1/ADA4830-2 110/253 mV
ENA VIH Voltage to enable device ≥3.0 V
ENA VIL Voltage to disable device ≤1.0 V

Rev. C | Page 3 of 22

ADA4830-1/ADA4830-2 Data Sheet

DYNAMIC PERFORMANCE

ADA4830-1W/ADA4830-2W only T

to T

59

MHz

Bandwidth for 0.1 dB Flatness

V

= 0.5 V p-p, RL = 150 Ω

20 MHz

Signal-to-Noise Ratio

f = 100 kHz to 15 MHz, V

= 0.5 V p-p

73 dB

Nominal Gain

VIN to V

0.49

0.50

0.51

V/V

ADA4830-1W/ADA4830-2W only T

to T

0.49 0.51

V/V

Input Current

VIN = 18 V (short-to-battery)

4.4 mA

Parameter Test Conditions/Comments Min Typ Max Unit

OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 150 Ω to ground 0.01 to 4.75 V
Linear Output Current <1% THD at 100 kHz 125 mA
Short-Circuit Current Sourcing/sinking 248/294 mA
Capacitive Load Drive Peaking ≤ 3 dB 47 pF

POWER SUPPLY

Operating Range Operation outside of this range results in

performance degradation
Quiescent Current per Amplifier Enabled (ENA = 5 V), no load 6.8 10 mA
ADA4830-1W/ADA4830-2W only T

MIN

to T

10.4 mA

MAX

Disabled (ENA = 0 V), no load 90 µA
VIN = 18 V (short-to-battery), no load 5.3 mA
Power Supply Rejection Ratio (PSRR) +VS = 4.5 V to 5.5 V, V

is forced to 2.5 V 53 dB

REF

OPERATING TEMPERATURE RANGE −40 +125 °C

3.3 V OPERATION

TA = 25°C, +VS = 3.3 V, RL = 1 kΩ, V

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

= 1.65 V (floating), V

REF

= +VS/2, R

INCM

= 5 kΩ to +Vs, unless otherwise specified.

STB

2.9 5.5 V

−3 dB Large Signal Bandwidth V
ADA4830-1W/ADA4830-2W only T
V
V

Slew Rate (tR/tF) V
ADA4830-1W/ADA4830-2W only T
Settling Time to 0.1% V

= 0.5 V p-p, RL = 150 Ω 63 73 MHz

OUT

to T

MIN

= 0.1 V p-p, RL = 1 kΩ 89 MHz

OUT

= 0.1 V p-p, RL = 150 Ω 64 78 MHz

OUT

MIN

OUT

= 1 V step 147/155 165/180 V/µs

OUT

MIN

= 1 V step 25 ns

OUT

58 MHz

MAX

MAX

to T

136/145 V/µs

MAX

NOISE/DISTORTION PERFORMANCE

Output Voltage Noise f = 1 MHz 28 nV/√Hz
Differential Gain Error (NTSC) RL = 150 Ω, VIN = 1 V p-p 0.1 %
Differential Phase Error (NTSC) RL = 150 Ω, VIN = 1 V p-p 0.1 Degrees

OUT

DC PERFORMANCE

OUT

MIN

MAX

Output Bias Voltage 1.60 1.65 1.70 V
ADA4830-1W/ADA4830-2W only T

MIN

to T

1.59 1.71 V

MAX

INPUT CHARACTERISTICS

Input Resistance (Differential Mode) 6.7 kΩ
Input Resistance (Common Mode) 2 kΩ
Input Common-Mode Voltage Range V
ADA4830-1W/ADA4830-2W only T

voltage adjusted to optimized range −8 +6 V

REF

to T

MIN

−8 +6 V

MAX

Common-Mode Rejection (CMR) VIN = ±3.3 V 41 54 dB
ADA4830-1W/ADA4830-2W only T

MIN

to T

40 dB

MAX

SHORT-TO-BATTERY CHARACTERISTICS

Protected Input Voltage Range −9 +20 V
ADA4830-1W/ADA4830-2W only T
Short-to-Battery Output Flag Trigger

Level

ADA4830-1W/ADA4830-2W only T

to T

MIN

Minimum VIN needed to signal an input fault

−9 +20 V

MAX

7.4 7.8 8.2 V

condition

to T

MIN

Rev. C | Page 4 of 22

7.4 8.2 V

MAX

Data Sheet ADA4830-1/ADA4830-2

Output Voltage Swing

RL = 150 Ω to ground

0.01 to 3.08

V

ADA4830-1W/ADA4830-2W only T

to T

8.4

mA

Parameter Test Conditions/Comments Min Typ Max Unit

VOLTAGE REFERENCE INPUT

Input Voltage Range 0.2 to 2.2 V
Input Resistance 20 kΩ
Gain V

LOGIC OUTPUT/INPUT CHARACTERISTICS

STB V

OH

STB VOL VIN ≥ 8.2 V (fault condition), ADA4830-1/ADA4830-2 85/178 mV
ENA VIH Voltage to enable device ≥1.8 V
ENA VIL Voltage to disable device ≤0.8 V

OUTPUT CHARACTERISTICS

Linear Output Current <1% THD at 100 kHz 50 mA
Short-Circuit Current Sourcing/sinking 85/180 mA
Capacitive Load Drive Peaking ≤ 4 dB 47 pF

POWER SUPPLY

Operating Range Operation outside of this range results in

Quiescent Current per Amplifier Enabled (ENA = 3.3 V), no load 5.5 8.0 mA

Disabled (ENA = 0 V), no load 60 µA
VIN = 18 V (short-to-battery), no load 4.3 mA
Power Supply Rejection Ratio (PSRR) +VS = 3.0 V to 3.6 V, V
OPERATING TEMPERATURE RANGE −40 +125 °C

to V

REF

1 V/V

OUT

VIN ≤ 7.4 V (normal operation) 3.3 V

2.9 5.5 V

performance degradation

MIN

MAX

forced to 1.65 V 42 dB

REF

Rev. C | Page 5 of 22

ADA4830-1/ADA4830-2 Data Sheet

Supply Voltage (+VS Pin)

6 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent dam age to the device. This is a stress

rating only ; functional operation of the device at these or any
other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect
device reliability.

8-Lead LFCSP

50 5 °C/W

10020-050

0

0.5

1.0

1.5

2.0

2.5

3.0

0 10 20 30 40 50 60 70 80 90 100

MAXIMUM POWER DISSIPATION (W)

AMBIENT TEMPERATURE (°C)

16-LEAD LF CS P

8-LEAD LF CS P

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage Delta

+VS1 to +VS2, ADA4830-2 Only 0.5 V

Input Voltage Positive Direction (INNx, INPx) 22 V
Input Voltage Negative Direction (INNx, INPx) −10 V
Reference Voltage (VREFx Pin) +VS + 0.3 V
Power Dissipation See Figure 3
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Lead Temperature (Soldering, 10 sec) 260°C
Junction Temperature 150°C

The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the supply voltage (+V

) times the quiescent current (IS).

S

The power dissipated due to load drive depends on the particular
application. The power due to load drive is calculated by
multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used
in these calculations.

Airflow increases heat dissipation, effectively reducing θ

Figure 3 shows the maximum power dissipation in the package vs.
the ambient temperature for the 8-lead LFCSP (116°C/W) and
the 16-lead LFCSP (54°C/W) on a JEDEC standard 4-layer board.
θ

values are approximate.

JA

) is the sum of the

D

.

JA

THERMAL RESISTANCE

θJA is specified for the device and its exposed paddle is soldered
to a high thermal conductivity, 4-layer (2s2p) circuit board, as
described in EIA/JESD 51-7.

Table 4.

Package Type θJA θJC Unit

16-Lead LFCSP 54 6 °C/W

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the ADA4830-1 and

ADA4830-2 packages is limited by the associated rise in

junction temperature (T
which is the glass transition temperature, the plastic changes its
properties. Exceeding a junction temperature of 150°C for an
extended time can result in changes in the silicon devices,
potentially causing failure.

) on the die. At approximately 150°C,

J

Figure 3. Maximum Power Dissipation vs.

Ambient Temperature for a 4-Layer Board

ESD CAUTION

Rev. C | Page 6 of 22

Data Sheet ADA4830-1/ADA4830-2

NOTES

1. EXPOSED PAD ON BOTTOM SIDE
OF PACKAGE . NOT CONNECT E D
ELECTRI CALLY, BUT SHOULD BE
SOLDERED TO A METALIZED AREA
ON THE PCB TO MINIMIZE THERMAL
RESISTANCE .

3INN
4GND

1VREF
2INP

6 VOUT
5 STB

8 +VS
7 ENA

ADA4830-1

TOP VIEW

(Not to S cale)

10020-003

3

INN

Negative Input.

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 4. ADA4830-1 Pin Configuration

Table 5. ADA4830-1 Pin Function Descriptions

Pin No. Mnemonic Description

1 VREF Voltage Reference Input. Sets the output dc bias voltage. Internally biased to +VS/2 when left floating. See the

Applications Information section.

2 INP Positive Input.

4 GND Power Supply Ground Pin.
5 STB Short-to-Battery Indicator Output Pin. A logic low indicates an overvoltage condition (short-to-battery), whereas a

logic high indicates normal operation. An open-drain configuration requires external pull-up resistor.
6 VOUT Amplifier Output.
7 ENA Enable Pin. Connect to +VS or float for normal operation. Connect to ground for device disable.
8 +VS Positive Power Supply Pin. Bypass this pin with a 0.1 µF capacitor to ground.
EPAD Exposed Pad. The exposed pad is located on the bottom side of the package. The pad is not connected electrically

but should be soldered to a metalized area on the printed circuit board (PCB) to minimize thermal resistance.

Rev. C | Page 7 of 22

ADA4830-1/ADA4830-2 Data Sheet

10020-004

12
11
10

1

3

4

VOUT1

NOTES

1. EXPOSED PAD ON BOTTOM SIDE
OF PACKAGE . NOT CONNECT E D
ELECTRI CALLY, BUT SHOULD BE
SOLDERED TO A METALIZED AREA
ON THE PCB TO MINIMIZE THERMAL
RESISTANCE .

STB1
STB2

9

VOUT2

INP1

INN2

2

INN1

INP2

6GND2

5VREF2

7+VS2

8

ENA2

16

VREF1

15

GND1

14

+VS1

13

ENA1

TOP

VIEW

ADA4830-2

10, 11

STB2, STB1

Short-to-Battery Indicator Output Pins. A logic low indicates an overvoltage condition (short-to-battery), whereas a

Figure 5. ADA4830-2 Pin Configuration

Table 6. ADA4830-2 Pin Function Descriptions

Pin No. Mnemonic Description

1, 4 INP1, INP2 Positive Inputs.
2, 3 INN1, INN2 Negative Inputs.
5, 16 VREF2, VREF1 Voltage Reference Inputs. Sets the output dc bias voltage. Internally biased to +VS/2 when left floating. See

the Applications Information section.
6, 15 GND2, GND1 Power Supply Ground Pins.
7, 14 +VS2, +VS1 Positive Power Supply Pins. These pins must be connected together, to the same voltage. Bypass these pins

with a 0.1 µF capacitor to ground.
8, 13 ENA2, ENA1 Enable Pins. Connect to +VS or float for normal operation and to ground for device disable.
9, 12 VOUT2, VOUT1 Amplifier Outputs.

logic high indicates normal operation. An open-drain configuration requires an external pull-up resistor.
EPAD Exposed Pad. The exposed pad is located on the bottom side of the package. The pad is not connected

electrically, but should be soldered to a metalized area on the PCB to minimize thermal resistance.

Rev. C | Page 8 of 22

Data Sheet ADA4830-1/ADA4830-2

3

0

–3

–6

–9

–12

–15

–18

0.1 1 10 100
FREQUENCY (MHz)

NORMALIZED GAIN (dB)

10020-005

VIN = 200mV p-p

RL = 150Ω

R

L

= 1kΩ

3

0

–3

–6

–9

–12

–15

–18

0.1 1 10 100

FREQUENCY (MHz)

NORMALIZ E D GAIN (dB)

10020-006

VIN = 200mV p-p

+VS = 3.3V

+VS = 5V

3

0

–3

–6

–9

–12

–15

–18

–21

–24

1 10 100

FREQUENCY (MHz)

NORMALIZED GAIN (dB)

10020-008

+125°C

+25°C

–40°C

VIN = 200mV p-p

3

0

–3

–6

–9

–12

–15

–18

0.1 1 10 100
FREQUENCY (MHz)

NORMALIZED GAIN (dB)

10020-010

V

IN

= 1V p-p

R

L

= 150Ω

R

L

= 1kΩ

3

0

–3

–6

–9

–12

–15

–18

0.1

1 10 100

FREQUENCY (MHz)

NORMALIZ E D GAIN (dB)

10020-011

V

IN

= 1V p-p

+V

S

= 3.3V

+V

S

= 5V

3

0

–3

–6

–9

–12

–15

–18

–21

–24

1 10 100

FREQUENCY (MHz)

NORMALIZED GAIN (dB)

10020-013

+25°C

+125°C

–40°C

+VS = 3.3V
V

IN

= 1V p-p

R

L

= 150Ω

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, +VS = 5 V, RL = 1 kΩ, V

= 2.5 V (floating), V

REF

= +VS/2, R

INCM

= 5 kΩ to +VS, unless otherwise specified.

STB

Figure 6. Small Signal Frequency Response for Various Loads

Figure 7. Small Signal Frequency Response for Various Supply Voltages

Figure 9. Large Signal Frequency Response for Various Loads

Figure 10. Large Signal Frequency Response for Various Supply Voltages

Figure 8. Small Signal Frequency Response for Various Temperatures

Figure 11. Large Signal Frequency Response for Various Temperatures

Rev. C | Page 9 of 22

ADA4830-1/ADA4830-2 Data Sheet

7

6

5
4

3

2
1

0

–1

–2
–3

0.1 1 10 100
FREQUENCY (MHz)

NORMALIZED GAIN (dB)

10020-012

V

IN

= 1V p-p

R

L

= 150Ω

CL = 0pF

C

L

= 68pF

NO SERIES OUTPUT RESISTOR

CL = 47pF

CL = 22pF

CL = 10pF

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

0.1 1 10 100
FREQUENCY (MHz)

NORMALIZED GAIN (dB)

10020-014

VIN = 1V p-p
R

L

= 150Ω

–90

–80

–70

–60

–50

–40

–30

–20

0.1 1 10 100

COMMON-M ODE REJECTIO N ( dB)

FREQUENCY (MHz)

10020-042

VIN = 1V p-p

V

INCM

= −8V

V

INCM

= +8V

V

INCM

= 0V

–70

–65

–60

–55

–50

–45

–40

–35

–30

–25

–12 –10 –8 –6 –4 –2

0 2 4 6 8 10 12 14

COMMON-M ODE REJECTIO N ( dB)

INPUT COMMON-MODE VOLTAGE (V)

VIN = 200mV p-p
f = 5MHz

+VS = 3.3V +VS = 5.0V

10020-017

–70

–60

–50

–40

–30

–20

–10

0

0.1 1 10 100

GAIN (dB)

FREQUENCY (MHz)

10020-019

V

IN

= 1V p-p

ENA = 0V

6

3

0

–3

–6

–9

–12

–15

0.1 1 10 100
FREQUENCY (MHz)

NORMALIZED GAIN (dB)

10020-009

V

REF

= 200mV p-p

+VS = 5.0V
R

L

= 1kΩ

+V

S

= 3.3V

R

L

= 150Ω

+VS = 5.0V

R

L

= 150Ω

+V

S

= 3.3V

R

L

= 1kΩ

Figure 12. Large Signal Frequency Response for Various Capacitor Loads

Figure 13. 0.1 dB Flatness

Figure 15. Small Signal CMR vs. V

for Various Supply Voltages

INCM

Figure 16. Input-to-Output Isolation with Device Disabled

Figure 14. CMR Frequency Response for Various Input Common-Mode

Voltages

Figure 17. V

to V

Frequency Response

REF

OUT

Rev. C | Page 10 of 22

Data Sheet ADA4830-1/ADA4830-2

1.5

1.7

1.9

2.1

2.3

2.5

2.7

2.9

0 10 20 30 40 50 60 70 80

OUTPUT VOLTAGE (V)

TIME (ns)

10020-020

+V

S

= 3.3V

V

OUT

= 1V p-p

R

L

= 1kΩ

R

L

= 150Ω

–2

0

2

4

6

8

10

12

14

16

0 50 100 150 200 250 300 350 500400 450

VOLTAGE (V)

TIME (ns)

10020-022

INP

R

STB

= 500Ω

R

STB

= 1kΩ

C

STB

= 11pF

R

STB

= 5kΩ

6

5

4

3

2

1

0

–1

1000 200 300 400 500 600

TIME (ns)

VOLTAGE (V)

10020-024

ENA

V

OUT

–20

–10

0

10

20

30

40

–12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14

OUTPUT OFFSET VOLTAGE (mV)

INPUT COMMON-MODE VOLTAGE (V)

10020-033

+V

S

= 3.3V

+V

S

= 5V

0

1

2

3

4

5

6

7

8

9

10

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

SUPPLY CURRENT (mA)

ENABLE VOLTAGE (V)

V

INP,VINN

= FLOATING

+VS = 3.3V

+VS = 5V

10020-134

0

20

40

60

80

100

120

140

46 51 56 61 66 71 76 81 86 91

COUNT

CMR (dB)

10020-045

Figure 18. Pulse Response at +VS = 3.3 V

Figure 19. Short-to-Battery Output Flag Response for Va rious R

, ADA4830-1

STB

Figure 21. Output Offset Voltage (V

OUT

− V

Input Common-Mode Voltage

Figure 22. Supply Current vs. Enable Voltage

) vs.

REF

Figure 20. Enable Turn-on/ Turn-off Time

Figure 23. Typical Distribution of Common-Mode Rejection

Rev. C | Page 11 of 22

ADA4830-1/ADA4830-2 Data Sheet

10020-046

–95

–90

–85

–80

–75

–70

–65

–60

–55

–50

–45

0.1 1 10 100

CROSSTALK (dB)

FREQUENCY (MHz)

V

IN

= 2V p-p

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0 10 20 30 40 50 60 70 80 90 100

V

OUT

(V)

TIME (ns)

V

IN

= 4V p-p

C

L

= 0pF

CL = 22pF

C

L

= 10pF

10020-047

10

100

1k

10k

10 100 1k 10k 100k 1M 10M 100M

VOLTAGE NOISE (nV/√Hz)

FREQUENCY (Hz)

10020-048

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

–40 –25 –10 5 20 35 50 65 80 95 110 125

SUPPLY CURRENT (mA)

TEMPERATURE (°C)

10020-051

10020-028

–110

–100

–90

–80

–70

–60

–50

–40

0.01 0.1 1 10

DISTORTION (dBc)

FREQUENCY (MHz)

V

OUT

= 1V p-p

SINGLE - E NDE D INPUT

HD2

SINGLE - E NDE D INPUT

HD3

DIFFERENTIAL INPUT

HD2

DIFFERENTIAL INPUT

HD3

–70

–60

–50

–40

–30

–20

–10

0

10

10 100 1k 10k 100k 1M 10M

PSR (dB)

FREQUENCY (Hz)

10020-029

+VS RIPPLE = 100mV p-p

C

VREF

= 0.1µF

C

VREF

= 10µF

C

VREF

= 4.7µF

Figure 24. Crosstalk (Output-to-Output) vs. Frequency, ADA4830-2

Figure 25. Pulse Response for Various Capacitor Loads

Figure 27. Supply Current vs. Temperature

Figure 28. Harmonic Distortion Vs Frequency

Figure 26. Total Output Voltage Noise vs. Frequency

Figure 29. PSR vs. Frequency for Various VREF Bypass Capacitors

Rev. C | Page 12 of 22

Data Sheet ADA4830-1/ADA4830-2

REF

INNINP

OUT

V

VV

V +

−

=

2

THEORY OF OPERATION

CORE AMPLIFIER

At the core of the ADA4830-1 and ADA4830-2 are high speed,
rail-to-rail op amps that are built on a 0.35 µm CMOS process.
Togeth er with the core amplifier, the ADA4830-1 and ADA4830-2
combine four highly matched on-chip resistors into a difference
amplifier function. Common-mode range extension at its inputs
is achieved by employing a resistive attenuator. The closed-loop
differential to single-ended gain of the video channel is internally
fixed at 0.50 V/V (−6 dB) to ensure compatibility with video
decoders whose input range is constrained to 1 V p-p or less.
The transfer function of the ADA4830-1 and ADA4830-2 is

where:

V

is the voltage at the output pin, VOUT.

OUT

V

INP

and V

are the input voltages at the INP and INN pins,

INN

respectively.

V

is the voltage at the VREF pin.

REF

OVERVOLTAGE (SHORT-TO-BATTERY) PROTECTION

Robust inputs guarantee that sensitive internal circuitry is not
subjected to extreme voltages or currents during a stressful event. A
short-to-battery condition usually consists of a voltage on either
input (or both inputs) that is significantly higher than the power
supply voltage of the amplifier. Duration may vary from a short
transient to a continuous fault.

The ADA4830-1 and ADA4830-2 can withstand voltages of up
to 18 V on the inputs. Critical internal nodes are protected from
exposure to high voltages by circuitry that clamps the inputs at a
safe level and limits internal currents. This protection is available
whether the device is enabled or disabled, even when the supply
voltage is removed.

SHORT-TO-BATTERY OUTPUT FLAG

The short-to-battery output flag (STB pin) is functionally
independent of the short-to-battery protection. Its purpose is
to indicate an overvoltage condition on either input. Because
protection is provided passively, it is always available; the flag
merely indicates the presence or absence of a fault condition.

ESD PROTECTION

All pins on the ADA4830-1 and ADA4830-2 are protected with
internal ESD protection structures connected to the power supply
pins (+VS and GND). These structures provide protection during
the handling and manufacturing process.

The inputs (INN and INP) of the ADA4830-1 and ADA4830-2
can be exposed to dc voltages well above the supply voltage;
therefore, conventional ESD structure protection cannot be used.

The ADA4830-1 and ADA4830-2 employ Analog Devices, Inc.,
proprietary ESD devices at the input pins (INN, INP) to allow
for a wide common-mode voltage range and ESD protection
well beyond the handling and manufacturing requirements.

The inputs of the ADA4830-1 and ADA4830-2 are ESD protected
to survive ±8 kV human body model (HBM)

POWER SUPPLY PINS (ADA4830-2)

As indicated in the Absolute Maximum Ratings section, the voltage
difference between the +VS1 and +VS2 pins of the ADA4830-2
cannot exceed 0.5 V. To ensure compliance with the Absolute
Maximum Ratings, it is recommended that these supply pins be
connected together to the same power supply source.

Rev. C | Page 13 of 22

ADA4830-1/ADA4830-2 Data Sheet

INN

INP

ADA4830-1

75Ω

−

+

75Ω

POSITIVE W IRE

NEGATIVE W IRE

DRIVER PCB

SINGLE-ENDED

AMPLIFIER

10020-034

INN

INP

ADA4830-1

75Ω

−

+

37.5Ω

37.5Ω

POSITIVE W IRE

NEGATIVE W IRE

DRIVER PCB

10020-035

SINGLE-ENDED

AMPLIFIER

INN

INP

ADA4830-1

75Ω

−

+

37.5Ω

37.5Ω

POSITIVE W IRE

NEGATIVE W IRE

DRIVER PCB

10020-036

DIFFERENTIAL

AMPLIFIER

APPLICATIONS INFORMATION

METHODS OF TRANSMISSION

Pseudo Differential Mode (Unbalanced Source Termination)

The ADA4830-1 and ADA4830-2 can be operated in a pseudo
differential configuration with an unbalanced input signal. This
allows the receiver to be driven by a single-ended source. Pseudo
differential mode uses a single conductor to carry an unbalanced
signal and connects the negative input terminal to the ground
reference of the source.

Use the positive wire or coaxial center conductor to connect the
source output to the positive input (INP) of the ADA4830-1 or

ADA4830-2. Next, connect the negative wire or coaxial shield from

the negative input (INN) back to a ground reference on the source
printed circuit board (PCB). The input termination should match
the source impedance and be referenced to the remote ground.
An example of this configuration is shown in Figure 30.

Figure 30. Pseudo Differential Mode

Pseudo Differential Mode (Balanced Source Impedance)

Pseudo differential signaling is typically implemented using
unbalanced source termination, as shown in Figure 30. With
this arrangement, however, common-mode signals on the
positive and negative inputs receive different attenuation due to
unbalanced termination at the source. This effectively converts
some of the common-mode signal into differential mode signal,
degrading the overall common-mode rejection of the system.
System common-mode rejection can be improved by balancing
the output impedance of the driver, as shown in Figure 31.
Splitting the source termination resistance evenly between the
hot and cold conductors results in matched attenuation of the
common-mode signals, ensuring maximum rejection.

Figure 31. Pseudo Differential Mode with Balanced Source Impedance

Rev. C | Page 14 of 22

Fully Differential Mode

The differential inputs of the ADA4830-1 and ADA4830-2 allow
full balanced transmission using a differential source. In this
configuration, the differential input termination is equal to twice
the source impedance of each output. For example, a source
with 37.5 Ω back termination resistors in each leg should be
terminated with a differential resistance of 75 Ω. An illustration
of this arrangement is shown in Figure 32.

Figure 32. Fully Differential Mode

VOLTAGE REFERENCE (VREF PIN)

An internal reference level (V
when the differential input voltage is zero. A resistor divider
connected between the supply rails sets the V
with a pair of matched 40 kΩ resistors, the divider sets this
voltage to +V

S

/2.

The voltage reference pin (VREF) normally floats at its default
value of +V

/2. However, it can be used to vary the output

S

reference level from this default value. A voltage applied to VREF
appears at the output with unity gain, within the bandwidth limit
of the internal reference buffer. Figure 17 shows the frequency
response of the VREF input.

Any noise on the +V

supply rail appears at the output with only

S

6 dB of attenuation (the divide-by-two provided by the reference
divider). Even when this pin is floating, it is recommended that
an external capacitor be connected from the reference node to
ground to provide further attenuation of noise on the power supply
line. A 4.7 µF capacitor combined with the internal 40 kΩ resistor
sets the low-pass corner at under 1 Hz and results in better than
40 dB of supply noise attenuation at 100 Hz.

) determines the output voltage

REF

voltage. Built

REF

Data Sheet ADA4830-1/ADA4830-2

3.3

1.651

–7.6

3.6

–15

–10

–5

0

5

10

15

2.5 3.0 3.5 4.0 4.5 5.0

5

.5 6.0

INPUT COMMON-MODE VOLTAGE (V)

S

UPPLYVOLTAGE (V)

V

INCM (MAX)

V

INCM (MIN)

VREF PIN FLOATING

10020-037

INPUT COMMON-MODE RANGE

In a standard four resistor difference amplifier with 0.50 V/V
gain, the input common-mode (CM) range is three times the CM
range of the core amplifier. In the ADA4830-1 and ADA4830-2,
however, the input CM range has been extended to more than 18 V
(with a 5 V supply). The input CM range can be approximated
by using the following formulas:

For the maximum CM voltage,

5(+V

− 1.25) − 4V

S

For the minimum CM voltage,

−10 V ≤ V

INCM(MIN)

Approximate minimum and maximum CM voltages are shown
in Tabl e 7 for several common supply voltages.

Table 7. Input Common-Mode Range Examples

+VS (V) V

3.0 1.51 –7.0 2.8

3.0 0.97 –4.9 4.9

≈ V

REF

≈ − (1 + 4V

(V) V

REF

INCM(MAX)

REF

INCM(MIN)

≤ 9.5 V

)

(V) V

INCM(MAX)

(V)

In the falling direction, the speed with which the flag output
responds primarily depends on the external capacitance attached to
this node and the sink current that can be provided. For example, if
the load is 10 pF, and the external pull-up voltage is 3.3 V, the fall
time is a few nanoseconds. In the rising direction, the speed is
determined by external capacitance and the magnitude of the
pull-up resistor. For the case of 10 pF of external capacitance
and a pull-up of 5 kΩ, the time constant of the rising edge is
approximately 50 ns.

Table 8. STB Pin Function

STB Pin Output Device State

High (Logic 1) Normal operation
Low (Logic 0) STB fault condition

ENABLE/DISABLE MODES (ENA PIN)

The power-down, or enable/disable (ENA) pin, is internally pulled
up to +V
pin is high, the amplifier is enabled; pulling ENA low disables
the channel. With no external connection, this pin floats high,
enabling the amplifier channel.

through a 250 kΩ resistor. When the voltage on this

S

3.3 1.15 –5.6 5.6

3.6 1.81 –8.2 4.5

3.6 1.34 –6.4 6.4

5.0 2.51 –10 8.7

5.0 2.22 –9.9 9.5

1

Floating (default condition).

Figure 33. Input Common-Mode Range vs. Supply Voltage

SHORT-TO-BATTERY OUTPUT FLAG PIN

The flag output (STB) is an active low, open-drain logic
configuration. A low level on this output indicates that an
overvoltage event has been detected on either the positive or
the negative input or both. Flags from multiple chips can be
wire-OR'ed to form a single fault detection signal. The output is
driven by a grounded source NMOS device, capable of sinking
approximately 10 mA while pulling within a few hundred millivolts
above ground. The output high level is set with an external pull-up
resistor connected to the supply voltage of the logic family that is
used to monitor the state of the flag.

Table 9. ENA Pin Function

ENA Pin Input Device State

High (Logic 1) Enabled
Low (Logic 0) Disabled
High-Z (Floating) Normal operation

PCB LAYOUT

As with all high speed applications, attention to PCB layout is of
paramount importance. Adhere to standard high speed layout
practices in designs using the ADA4830-1 and ADA4830-2. A
solid ground plane is recommended, and placing a 0.1 µF surface­mount, ceramic power supply, decoupling capacitor as close as
possible to the supply pin(s) is recommended.

Connect the GND pin(s) to the ground plane with a trace that is as
short as possible. In cases where the ADA4830-1 and ADA4830-2
drive transmission lines, series terminate the outputs and use
controlled impedance traces of the shortest length possible to
connect to the signal I/O pins, which should not pass over any
voids in the ground plane.

Rev. C | Page 15 of 22

EXPOSED PADDLE (EPAD) CONNECTION

The ADA4830-1 and ADA4830-2 have an exposed thermal pad
(EPAD ) on the bottom of the package. This pad is not electrically
connected to the die and can be left floating or connected to the
ground plane. Should heat dissipation be a concern, thermal
resistance can be minimized by soldering the EPAD to a
metalized pad on the PCB. Connect this pad to the ground
plane with multiple vias. Note that the thermal resistance (θ
of the device is specified with the EPAD soldered to the PCB.

)

JA

ADA4830-1/ADA4830-2 Data Sheet

ADA4830-2

INP1

GND2

VREF2

+VS2

0.1µF

ENA2

ENABLE2

(INPUT)

+V

S

4.7µF

4.7µF

VREF1

+VS1

GND1

ENA1

VOUT1

VOUT2

STB1

STB2

5kΩ5kΩ

+V

S

+V

S

1

2

3

4

6 7 85

12

11

10

9

15 14 13

16

75Ω

75Ω

75Ω

DIFFERENTIAL

INPUT 1

75Ω

75Ω

DIFFERENTIAL

INPUT 2

CONNECT
TO VIDEO
DECODER

75Ω

INN1

INN2

INP2

STB FLAGS
(OUTPUTS)

2.2µF

0.1µF

+

ENABLE1

(INPUT)

10020-049

USING THE ADA4830-2 AS A LOW COST VIDEO SWITCH

Figure 34 shows a video multiplexer/switch using the ADA4830-2,
dual, high speed difference amplifier. This circuit allows the user
to input two remote video sources into a single channel of a video
decoder, such as the ADV7180.

Traditional CMOS multiplexers and switches suffer several
disadvantages at video frequencies where their on-resistance
introduces distortion, degrades differential gain and phase
performance, and interacts with the termination resistor to
attenuate the incoming video signal and affect the luminance.
System designers generally address these issues by adding
external buffers to add gain and increase drive capability.

Video multiplexing can be simplified by using high speed video
amplifiers with a disable/enable function (sometimes called power­down). When the amplifier is disabled, its output stage goes into
a high impedance state, allowing several amplifier outputs to be

wired together. High speed video op amps have all the key features
required to make them ideal for this function. Their high input
impedance does not affect the characteristic impedance of the
transmission line, thus allowing back termination. They also have
inherently good video specifications, including differential gain and
phase, slew rate, bandwidth, and 0.1 dB flatness.

Each channel of the ADA4830-2 is a high speed difference
amplifier circuit that eliminates common-mode noise and phase
noise caused by ground potential differences between the incoming
video signal and the receiver. The ADA4830-2 also offers integrated
short-to-battery protection and heightened ESD tolerance in a
small foot print. The fault detection output (the STB pins) of the

ADA4830-2 allows for proactive wire diagnostics when connected

to a microcontroller or video decoder and are used to generate
an interrupt during a fault condition.

Figure 34. Low Cost Video Switch Using the ADA4830-2

Rev. C | Page 16 of 22

Data Sheet ADA4830-1/ADA4830-2

ADA4830-1

+

–

CL = 47pF

R

S

= 49.9Ω

RL = 1kΩ

10020-052

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0 50 100 150 200 250

V

OUT

(V)

TIME (ns)

10020-135

+VS = 5V
RL = 1kΩ
CL = 47pF

NO R

S

R

S

= 49.9Ω

ADA4830-1

+

–

CL = 47pF

C

SNT

= 0.1uF

RL = 1kΩ

R

SNT

= 73.2Ω

10020-053

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0 50 100 150 200 250

V

OUT

(V)

TIME (ns)

10020-137

+V

S

= 5V

R

L

= 1kΩ

CL = 47pF

NO SNUBBER
CIRCUIT

R

SNT

= 73.2Ω

C

SNT

= 0.1µF

DRIVING CAPACITIVE LOADS

The ADA4830-1 and ADA4830-2 are capable of driving large
capacitive loads while maintaining its rated performance.
Several performance curves vs. capacitive load are shown in
Figure 12 and Figure 25. Capacitive loads interact with an op amp’s
output impedance to create an extra delay in the feedback path.
This reduces circuit stability and can cause unwanted ringing
and oscillation.

The capacitive load drive of the ADA4830-1and ADA4830-2 can
be increased by adding a low valued resistor, R
capacitive load. Figure 35 shows the test circuit.

, in series with the

S

Another method of reducing the resonant peaking caused by
driving large capacitive loads at the output of the ADA4830-1
and ADA4830-2 is with the use of a R-C shunt circuit or a snubber
circuit. This method acts to resistively load the amplifier output,
thus reducing frequency response peaking. One drawback to this
approach is a slight loss of signal bandwidth. Figure 37 shows a
simple circuit representation of the implementation of the R-C
snubber circuit with R
a R-C snubber circuit driving 47 pF, where R

SNT

and C

. Figure 38 shows the effects of

SNT

= 73.2 Ω and C

SNT

SNT

= 0.1 µF.

Figure 35. R

Test Circuit

S

Introducing a series resistor tends to isolate the capacitive load
from the feedback loop, thereby diminishing its influence. One
drawback to this approach is a slight loss of signal amplitude.
Figure 36 shows the effects of a series resistor on the capacitive
drive. For very large capacitive loads, the frequency response of
the amplifier is dominated by the roll-off of the series resistor
and capacitive load.

Figure 37. R-C Test Circuit

Figure 38. Pulse Response With and Without R-C Snubber Circuit

Figure 36. Pulse Response With and Without Series Resistor

Rev. C | Page 17 of 22

ADA4830-1/ADA4830-2 Data Sheet

INN

VOUT

TO VIDEO
DECODER

GND

INP

VREF

ADA4830-1

75Ω

−

+

75Ω

POSITIVE W IRE

NEGATIVE W IRE

DRIVER PCB

+

STBENA +VS

SINGLE ENDED

AMPLIFIER

4.7µF

0.1µF

+VS

ENABLE

(INPUT)

STB FLAG

(OUTPUT)

2.2µF

0.1µF

+V

S

(2.9V TO 5.5V)

5kΩ

×1

10020-038

INN

VOUT

TO VIDEO
DECODER

GND

INP

ADA4830-1

75Ω

−

+

37.5Ω

37.5Ω

DRIVER PCB

STBENA +VS

4.7µF

0.1µF

+VS

+

ENABLE

(INPUT)

STB FLAG

(OUTPUT)

2.2µF

0.1µF

5kΩ

×1

+V

S

(2.9V TO 5.5V)

VREF

DIFFERENTIAL

AMPLIFIER

10020-039

TYPICAL APPLICATIONS CIRCUITS

Figure 39. Typical Application with Pseudo Differential Input

Figure 40. Typical Application with Full y Differential Input

Rev. C | Page 18 of 22

Data Sheet ADA4830-1/ADA4830-2

−

+

ADV7180

INN

VOUT

GND

INP

ADA4830-1

75Ω

+

STBENA +VS

4.7µF

0.1µF

0.1µF

21

25

24

23

19

3

143022

18

A

IN

1

A

IN

2

A

IN

3

20

13

11
32

1

31

4

12

26

28

17

82nF

10nF

2

29

ELPF

27

ALSB

SCLK SCLK

DGND

DGND

SDA

SDATA

XTAL1

XTAL

0.1µF

+VS

ENABLE

(INPUT)

STB FLAG
(OUTPUT)

2.2µF

0.1µF

5kΩ

+V

S

(2.9V TO 5.5V)

VREF

D

VDDIO

0.1µF 10nF

A

VDD

_1.8V

0.1µF 10nF

0.1µF 10nF

D

VDD

_1.8V

D

VDD

_3.3V

D

VDDIO

P

VDD

_1.8V

P

VDD

_1.8V

D

VDD

_1.8V

A

VDD

_1.8V

0.1µF 10nF

KEEP VREFN AND V RE FP CAPACITORS AS CLOSE AS
POSSIBLE TO THE ADV 7180 AND ON THE SAME SI DE
OF THE P CB AS THE ADV7180.

LOCATE CLOSE TO, AND

ON THE SAME SIDE AS,

THE ADV7180

ALSB TIED HI

≥ I2C ADDRE S S = 0x42

ALSB TIED LOW

≥ I

2

C ADDRE S S = 0x40

RESET

RESET

P0
P1
P2
P3
P4
P5
P6
P7

P0

YCrCb

8-BIT

656 DATA

P[0:7]

P1
P2
P3
P4
P5
P6
P7

16
15
10
9
8
7
6
5

VREFN

DVDDIO

DVDD

DVDD

AVDD

PVDD

VREFP

28.63636MHz

47pF

47pF

1MΩ

4kΩ

LLC

1.69kΩ

INTRQ
SFL

VS/FIELD

EXTERNAL
LOOP FILTER

KEEP CLOS E TO THE ADV7180 AND ON

THE SAME SIDE OF PCB AS T HE ADV 7180.

HS

LLC

INTRQ

SFL

VS/FIELD

HS

10020-040

×1

The ADA4830-1 and ADA4830-2 are differential receivers whose
overall performance is independent of the transmitter IC used
and whether the transmission line is ac-coupled or dc-coupled.

The ADA4830-1 and ADA4830-2 are specifically designed to
perform as differential line receivers. The circuit in Figure 41
shows a detailed schematic of the ADA4830-1 and the ADV7180
configured for this function. The signal is received differentially
relative to the common of the source circuitry, and that voltage
is exactly reproduced with an attenuating gain of 0.50 V/V. This
is designed to keep the video signal within the allowed range of
the video decoder, which is typically 1 V p-p or less.

Figure 41. ADA4830-1 Driving an ADV7180 Video Decoder

The common-mode rejection vs. frequency, shown in Figure 14,
typically 65 dB at low frequencies, enables the recovery of video

Rev. C | Page 19 of 22

signals in the presence of large common-mode noise. The high
input impedance permits the ADA4830-1 and ADA4830-2 to
operate as a bridging amplifier across low impedance terminations
with negligible loading.

ADA4830-1/ADA4830-2 Data Sheet

R

T

+V

S

INN

VOUT

TO VIDEO
DECODER

GND

INP

ADA4830-1

75Ω

−

+

GND

LPF

LPF

+

+

STBENA +VS

4.7µF

0.1µF

+VS

ENABLE

(INPUT)

STB FLAG

(OUTPUT)

2.2µF

0.1µF

5kΩ

+V

S

(2.9V TO 5.5V)

STBENA +VS

ENABLE

(INPUT)

STB FLAG

(OUTPUT)

2.2µF

0.1µF

+V

S

(2.7V TO 3.6V)

VREF

+IN

–IN

–OUT

+OUT

−

+

75Ω

TWISTED

PAIR

37.5Ω

37.5Ω

FROM

IMAGER
OR VIDEO
ENCODER

×1

10020-041

FULLY DC-COUPLED TRANSMISSION LINE

The wide input common-mode range and high input impedance of
the ADA4830-1 and ADA4830-2 allow them to be used in fully
dc-coupled transmission line applications in which there may be a
significant discrepancy between voltage levels at the ground pins of
the driver and receiver. As long as the voltage difference between

reference levels at the transmitter and receiver is within the
common-mode range of the receiver, very little current flow
results, and no image degradation should be anticipated.

Figure 42 shows an example configuration of a completely dc­coupled transmission using a low impedance differential dr iver.

Figure 42. Differential Video Filter Driver and ADA4830-1 Difference Amplifier

Rev. C | Page 20 of 22

Data Sheet ADA4830-1/ADA4830-2

2.44

2.34

2.24

TOP VIEW

8

1

5

4

0.30

0.25

0.20

BOTTOM VIEW

PIN 1 INDEX

AREA

SEATING

PLANE

0.80

0.75

0.70

1.70

1.60

1.50

0.203 REF

0.05 MAX

0.02 NOM

0.50 BSC

EXPOSED

PAD

3.10

3.00 SQ

2.90

PIN 1
INDICATOR
(R 0.15)

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.50

0.40

0.30

COMPLIANT

TO

JEDEC STANDARDS MO-229-WEED

01-24-2011-B

3.10

3.00 SQ

2.90

0.30

0.23

0.18

1.75

1.60 SQ

1.45

08-16-2010-E

1

0.50

BSC

BOTTOM VIEWTOP VIEW

16

5

8

9

12

13

4

EXPOSED

PAD

PIN 1
INDICATOR

0.50

0.40

0.30

SEATING

PLANE

0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

COPLANARITY

0.08

PIN 1

INDICATOR

FOR PROP E R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURATION AND
FUNCTIO N DE S CRIPTIONS
SECTION OF THIS DATA SHEET.

0.80

0.75

0.70

COMPLIANT

TO

JEDEC STANDARDS MO-220-WEED-6.

ADA4830-1WBCPZ-R7

−40°C to +125°C

8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

CP-8-11

4H1

1500

PACKAGING AND ORDERING INFORMATION

OUTLINE DIMENSIONS

ORDERING GUIDE

1, 2

Model

ADA4830-1BCP-EBZ Evaluation Board
ADA4830-1BCPZ-R7 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-8-11 H30 1500

ADA4830-1BCPZ-R2 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-8-11 H30 250
ADA4830-2BCPZ-R7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-22 H31 1500
ADA4830-2BCPZ-R2 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-22 H31 250
ADA4830-2WBCPZ-R7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-22 4H2 1500

1

Z = RoHS Compliant Part.

2

W = Qualified for Automotive Applications.

Temperature Range Package Description

Figure 43. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

Figure 44. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

Dimensions shown in millimeters

(CP-8-11)

3 mm × 3 mm Body, Very Very Thin Quad

(CP-16-22)

Dimensions shown in millimeters

Rev. C | Page 21 of 22

Package
Option Branding

Ordering
Quantity

ADA4830-1/ADA4830-2 Data Sheet

©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered

respective owners.

AUTOMOTIVE PRODUCTS

The ADA4830-1W and ADA4830-2W models are available with controlled manufacturing to support the quality and reliability
requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial
model; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products
shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product
ordering information and to obtain the specific Automotive Reliability reports for these models.

trademarks are the proper ty of their

D10020-0-6/12(C)

www.analog.com/ADA4830-1/ADA4830-2

Rev. C | Page 22 of 22