ANALOG DEVICES ADA4817-1, ADA4817-2 Service Manual
Low Noise, 1 GHz
A
–V
A
–V
A
FEATURES
High speed
−3 dB bandwidth (G = 1, R
Slew rate: 870 V/μs
0.1% settling time: 9 ns
Low input bias current: 2 pA
Low input capacitance
Common-mode capacitance: 1.3 pF
Differential-mode capacitance: 0.1 pF
Low noise
4 nV/√Hz @ 100 kHz
2.5 fA/√Hz @ 100 kHz
Low distortion
−90 dBc @ 10 MHz (G = 1, R
Offset voltage: 2 mV maximum
High output current: 40 mA
Supply current per amplifier: 19 mA
Power-down supply current per amplifier: 1.5 mA
APPLICATIONS
Photodiode amplifiers
Data acquisition front ends
Instrumentation
Filters
ADC drivers
CCD output buffers
= 100 Ω): 1050 MHz
L
= 1 kΩ)
L
FastFET Op Amps
ADA4817-1/ADA4817-2
CONNECTION DIAGRAMS
DA4817-1
TOP VIEW
(Not to Scale)
1PD
2FB
3–IN
4+IN
NC = NO CONNECT
Figure 1. 8-Lead LFCSP (CP-8-2)
DA4817-1
TOP VIEW
(Not to Scale)
1
FB
–IN
2
+IN
3
4
S
NC = NO CONNECT
Figure 2. 8-Lead SOIC (RD-8-1)
DA4817-2
TOP VIEW
(Not to Scale)
FB1
PD1
16
15
1–IN1
2+IN1
3NC
4
S2
8+V
S
7OUT
6NC
5–V
S
07756-001
8
PD
+V
7
S
OUT
6
NC
5
07756-002
S1
OUT1
+V
14
13
12 –V
S1
11 NC
10 +IN2
9–IN2
GENERAL DESCRIPTION
The ADA4817-1 (single) and ADA4817-2 (dual) FastFET™
amplifiers are unity-gain stable, ultrahigh speed voltage
feedback amplifiers with FET inputs. These amplifiers were
developed with the Analog Devices, Inc., proprietary eXtra Fast
Complementary Bipolar (XFCB) process, which allows the
amplifiers to achieve ultralow noise (4 nV/√Hz; 2.5 fA/√Hz)
as well as very high input impedances.
With 1.3 pF of input capacitance, low noise (4 nV/√Hz), low
offset voltage (2 mV maximum), and 1050 MHz −3 dB bandwidth, the ADA4817-1/ADA4871-2 are ideal for data acquisition
front ends as well as wideband transimpedance applications,
such as photodiode preamps.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
8
7
5
6
S2
D2
FB2
P
+V
OUT2
NC = NO CONNECT
Figure 3. 16-Lead LFSCP (CP-16-4)
07756-003
With a wide supply voltage range from 5 V to 10 V and the
ability to operate on either single or dual supplies, the
ADA4817-1/ ADA4817-2 are designed to work in a variety of
applications including active filtering and ADC driving.
The ADA4817-1 is available in a 3 mm × 3 mm, 8-lead LFCSP and
8-lead SOIC, and the ADA4817-2 is available in a 4 mm × 4 mm,
16-lead LFCSP. These packages feature a low distortion pinout
that improves second harmonic distortion and simplifies circuit
board layout. They also feature an exposed paddle that provides a
low thermal resistance path to the printed circuit board (PCB).
This enables more efficient heat transfer and increases reliability.
These products are rated to work over the extended industrial
temperature range (−40°C to +105°C).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved.
ADA4817-1/ADA4817-2
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagrams ...................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±5 V Operation ............................................................................. 3
5 V Operation ............................................................................... 4
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Safe Power Dissipation ............................................. 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Test Circuits ..................................................................................... 13
Theory of Operation ...................................................................... 14
Closed-Loop Frequency Response ........................................... 14
Noninverting Closed-Loop Frequency Response .................. 14
Inverting Closed-Loop Frequency Response ............................. 14
Wideband Operation ................................................................. 15
Driving Capacitive Loads .......................................................... 15
Thermal Considerations ............................................................ 15
Power-Down Operation ............................................................ 15
Capacitive Feedback ................................................................... 16
Higher Frequency Attenuation ................................................. 16
Layout, Grounding, and Bypassing Considerations .................. 17
Signal Routing ............................................................................. 17
Power Supply Bypassing ............................................................ 17
Grounding ................................................................................... 17
Exposed Paddle ........................................................................... 17
Leakage Currents ........................................................................ 18
Input Capacitance ...................................................................... 18
Input-to-Input/Output Coupling ............................................. 18
Applications Information .............................................................. 19
Low Distortion Pinout ............................................................... 19
Wideband Photodiode Preamp ................................................ 19
High Speed JFET Input Instrumentation Amplifier.............. 21
Active Low-Pass Filter (LPF) .................................................... 22
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 25
REVISION HISTORY
3/09—Rev. 0 to Rev. A
Added 8-Lead SOIC Package ............................................ Universal
Changes to Features Section and General Description Section . 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Figure 4 .......................................................................... 5
Changes to Figure 9, Figure 11, and Figure 12 ............................. 8
Changes to Figure 21, Figure 22, and Figure 24 ......................... 10
Changes to Figure 33 ...................................................................... 12
Added Figure 34; Renumbered Sequentially .............................. 12
Changes to Thermal Considerations Section and Power-Down
Operation Section ........................................................................... 15
Changes to Capacitive Feedback Section and Figure 46 ........... 16
Added Higher Frequency Attenuation Section, Figure 47,
Figure 48, and Figure 49; Renumbered Sequentially ................. 16
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 25
11/08—Revision 0: Initial Version
Rev. A | Page 2 of 28
ADA4817-1/ADA4817-2
SPECIFICATIONS
±5 V OPERATION
TA = 25°C, +VS = 5 V, −VS = −5 V, G = 1, RF = 348 Ω for G > 1, RL = 100 Ω to ground, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth V
V
V
Gain Bandwidth Product V
Full Power Bandwidth VIN = 3.3 V p-p, G = 2 60 MHz
0.1 dB Flatness V
Slew Rate V
Settling Time to 0.1% V
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion (HD2/HD3) f = 1 MHz, V
f = 10 MHz, V
f = 50 MHz, V
Input Voltage Noise f = 100 kHz 4 nV/√Hz
Input Current Noise f = 100 kHz 2.5 fA/√Hz
DC PERFORMANCE
Input Offset Voltage 0.4 2 mV
Input Offset Voltage Drift 7 μV/°C
Input Bias Current
T
Input Bias Offset Current 1 pA
Open-Loop Gain 62 65 dB
INPUT CHARACTERISTICS
Input Resistance Common mode 500 GΩ
Input Capacitance Common mode 1.3 pF
Differential mode 0.1 pF
Input Common-Mode Voltage Range −VS to +VS − 2.8 V
Common-Mode Rejection VCM = ±0.5 V −77 −90 dB
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time VIN = ±2.5 V, G = 2 8 ns
Output Voltage Swing
R
Linear Output Current 1% output error 40 mA
Short-Circuit Current Sinking/sourcing 100/170 mA
POWER-DOWN
PD Pin Voltage
Powered down <+VS − 3 V
Turn-On/Turn-Off Time 0.3/1 μs
Input Leakage Current
POWER SUPPLY
Operating Range 5 10 V
Quiescent Current per Amplifier 19 21 mA
Powered Down Quiescent Current 1.5 3 mA
Positive Power Supply Rejection +VS = 4.5 V to 5.5 V, −VS = −5 V −67 −72 dB
Negative Power Supply Rejection +VS = 5 V, −VS = −4.5 V to −5.5 V −67 −72 dB
= 0.1 V p-p 1050 MHz
OUT
= 2 V p-p 200 MHz
OUT
= 0.1 V p-p, G = 2 390 MHz
OUT
= 0.1 V p-p ≥410 MHz
OUT
= 2 V p-p, RL = 100 Ω, G = 2 60 MHz
OUT
= 4 V step 870 V/μs
OUT
= 2 V step, G = 2 9 ns
OUT
= 2 V p-p, RL = 1 kΩ −113/−117 dBc
OUT
= 2 V p-p, RL = 1 kΩ −90/−94 dBc
OUT
= 2 V p-p, RL = 1 kΩ −64/−66 dBc
OUT
2 20 pA
to T
MIN
= 1 kΩ
L
Enabled >+V
PD
PD
100 pA
MAX
V
V
= +VS
= −VS
Rev. A | Page 3 of 28
−V
+V
−V
+V
S
S
S
S
+ 1.5 to
− 1.5
+ 1.1 to
− 1.1
+ 1.4 to
−V
S
+V
− 1.3
S
−V
+ 1 to
S
− 1
+V
S
− 1 V
S
0.3 3 μA
34 61 μA
ADA4817-1/ADA4817-2
5 V OPERATION
TA = 25°C, +VS = 3 V, −VS = −2 V, G = 1, RF = 348 Ω for G > 1, RL = 100 Ω to ground, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth V
V
V
Full Power Bandwidth VIN = 1 V p-p, G = 2 95 MHz
0.1 dB Flatness V
Slew Rate V
Settling Time to 0.1% V
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion (HD2/HD3) f = 1 MHz, V
f = 10 MHz, V
f = 50 MHz, V
Input Voltage Noise f = 100 kHz 4 nV/√Hz
Input Current Noise f = 100 kHz 2.5 fA/√Hz
DC PERFORMANCE
Input Offset Voltage 0.5 2.3 mV
Input Offset Voltage Drift 7 μV/°C
Input Bias Current
T
Input Bias Offset Current 1 pA
Open-Loop Gain 61 63 dB
INPUT CHARACTERISTICS
Input Resistance Common mode 500 GΩ
Input Capacitance Common mode 1.3 pF
Differential mode 0.1 pF
Input Common-Mode Voltage Range −VS to +VS − 2.9 V
Common-Mode Rejection VCM = ±0.25 V −72 −83 dB
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time VIN = ±1.25 V, G = 2 13 ns
Output Voltage Swing RL = 100 Ω
R
Linear Output Current 1% output error 20 mA
Short-Circuit Current Sinking/sourcing 40/130 mA
POWER-DOWN
PD Pin Voltage
Powered down <+VS − 3 V
Turn-On/Turn-Off Time 0.2/0.7 μs
Input Leakage Current
POWER SUPPLY
Operating Range 5 10 V
Quiescent Current per Amplifier 14 16 mA
Powered Down Quiescent Current 1.5 2.8 mA
Positive Power Supply Rejection +VS = 4.75 V to 5.25 V, −VS = 0 V −66 −71 dB
Negative Power Supply Rejection +VS = 5 V, −VS = −0.25 V to +0.25 V −63 −69 dB
= 0.1 V p-p 500 MHz
OUT
= 1 V p-p 160 MHz
OUT
= 0.1 V p- p, G = 2 280 MHz
OUT
= 1 V p-p, G = 2 32 MHz
OUT
= 2 V step 320 V/μs
OUT
= 1 V step, G = 2 11 ns
OUT
= 1 V p-p, RL = 1 kΩ −87/−88 dBc
OUT
= 1 V p-p, RL = 1 kΩ −68/−66 dBc
OUT
= 1 V p-p, RL = 1 kΩ −57/−55 dBc
OUT
2 20 pA
to T
MIN
= 1 kΩ
L
Enabled >+V
PD
PD
100 pA
MAX
V
V
= +VS
= −VS
−V
+V
−V
+V
S
S
S
S
+ 1.3 to
− 1.3
+ 1 to
− 1.1
+ 1 to
−V
S
+V
− 1.2
S
−V
+ 0.9 to
S
− 1
+V
S
− 1 V
S
0.2 3 μA
31 53 μA
Rev. A | Page 4 of 28
ADA4817-1/ADA4817-2
(
ABSOLUTE MAXIMUM RATINGS
P
= Quiescent Power + (Total Drive Power – Load Power) (1)
Table 3.
Parameter Rating
Supply Voltage 10.6 V
Power Dissipation See Figure 4
Common-Mode Input Voltage −VS − 0.5 V to +VS + 0.5 V
Differential Input Voltage
±V
S
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +105°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in the circuit board for the
surface-mount packages.
Table 4.
Package Type θJA θ
LFCSP_VD (ADA4817-1) 94 29 °C/W
SOIC_N_EP (ADA4817-1) 79 29 °C/W
LFSCP_VQ (ADA4817-2) 64 14 °C/W
Unit
JC
D
⎛
()
D
⎜
IVP
SS
⎜
⎝
V
2
⎞
V
OUTS
⎟
×+×= (2)
⎟
R
L
⎠
Consider RMS output voltages. If R
in single-supply operation, the total drive power is V
2
V
OUT
–
R
L
is referenced to −VS, as
L
× I
S
OUT
. If
the rms signal levels are indeterminate, consider the worst-case
scenario, when V
()
D
In single-supply operation with R
case situation is V
Airflow increases heat dissipation, effectively reducing θ
= VS/4 for RL to midsupply.
OUT
2
)
V
4/
S
IVP
+×=
SS
OUT
= VS/2.
(3)
R
L
referenced to −VS, the worst-
L
.
JA
More metal directly in contact with the package leads and
exposed paddle from metal traces, throughholes, ground,
and power planes also reduces θ
.
JA
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
LFCSP_VD (single 94°C/W), SOIC_N_EP (single 79°C/W)
and LFCSP_VQ (dual 64°C/W) package on a JEDEC standard
4-layer board. θ
3.5
3.0
2.5
2.0
values are approximations.
JA
ADA4817-2, LFCS P
ADA4817-1, SOIC
MAXIMUM SAFE POWER DISSIPATION
The maximum safe power dissipation for the ADA4817-1/
ADA4817-2 are limited by the associated rise in junction
temperature (T
the glass transition temperature), the properties of the plastic
change. Even temporarily exceeding this temperature limit may
change the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4817-x. Exceeding
a junction temperature of 175°C for an extended period can result
in changes in silicon devices, potentially causing degradation or
loss of functionality.
The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
die due to the ADA4817-1/ADA4817-2 drive at the output.
The quiescent power is the voltage between the supply pins (V
multiplied by the quiescent current (I
) on the die. At approximately 150°C (which is
J
) is the sum of the
D
).
S
Rev. A | Page 5 of 28
1.5
ADA4817-1, LFCS P
1.0
MAXIMUM POW ER DISSIPAT ION (W)
0.5
0
–40
–30 –20 –10 0 10 20 30 40 50 60 70 80 90 100
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Safe Power Dissipation vs. Ambient Temperature for
a 4-Layer Board
07756-008
ESD CAUTION
)
S
ADA4817-1/ADA4817-2
A
A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DA4817-1
TOP VIEW
(Not to Scale)
1PD
2FB
3–IN
4+IN
NC = NO CONNECT
NOTES
1. EXPOSE D PAD CAN BE CONNECTED
TO GROUND PLANE OR NEGATIVE
SUPPLY PLANE.
8+V
S
7OUT
6NC
5–V
S
07756-005
Figure 5. ADA4817-1 Pin Configuration (8-Lead LFCSP)
Table 5. ADA4817-1 Pin Function Descriptions (8-Lead LFCSP)
Pin No. Mnemonic Description
1
PD
Power-Down. Do not leave floating.
2 FB Feedback Pin.
3 −IN Inverting Input.
4 +IN Noninverting Input.
5 −VS Negative Supply.
6 NC No Connect.
7 OUT Output.
8 +VS Positive Supply.
Exposed pad (EPAD) Exposed Pad. Can be connected to GND, −VS plane, or left floating.
DA4817-1
TOP VIEW
(Not to Scale)
1
FB
2
–IN
+IN
3
–V
4
S
NC = NO CONNECT
NOTES
1. EXPOSED PAD CAN BE CONNECTED
TO GROUND PLANE O R NEGATIVE
SUPPLY PLANE.
8
PD
7
+V
S
OUT
6
NC
5
07756-006
Figure 6. ADA4817-1 Pin Configuration (8-Lead SOIC)
Table 6. ADA4817-1 Pin Function Descriptions (8-Lead SOIC)
Pin No. Mnemonic Description
1 FB Feedback Pin.
2 −IN Inverting Input.
3 +IN Noninverting Input.
4 −VS Negative Supply.
5 NC No Connect.
6 OUT Output.
7 +VS Positive Supply.
8
PD
Power-Down. Do not leave floating.
Exposed pad (EPAD) Exposed Pad. Can be connected to GND, −VS plane, or left floating.
Rev. A | Page 6 of 28
ADA4817-1/ADA4817-2
A
DA4817-2
TOP VIEW
(Not to Scale)
S1
OUT1
FB1
PD1
+V
14
13
16
15
1–IN1
2+IN1
3NC
4–V
S2
5
6
S2
+V
OUT2
NOTES
1. EXPOSED PAD CAN BE CONNECTED
SUPPLY PLANE.
NC = NO CONNECT
TO THE GROUND PLANE OR NEGATIVE
12 –V
S1
11 NC
10 +IN2
9–IN2
8
7
FB2
PD2
07756-107
Figure 7. ADA4817-2 Pin Configuration (16-Lead LFCSP)
Table 7. 16-Lead LFCSP Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN1 Inverting Input 1.
2 +IN1 Noninverting Input 1.
3, 11 NC No Connect.
4 −VS2 Negative Supply 2.
5 OUT2 Output 2.
6 +VS2 Positive Supply 2.
7
PD2
Power-Down 2. Do not leave floating.
8 FB2 Feedback Pin 2.
9 −IN2 Inverting Input 2.
10 +IN2 Noninverting Input 2.
12 −VS1 Negative Supply 1.
13 OUT1 Output 1.
14 +VS1 Positive Supply 1.
15
PD1
Power-Down 1. Do not leave floating.
16 FB1 Feedback Pin 1.
Exposed pad (EPAD) Exposed Pad. Can be connected to GND, −VS plane, or left floating.
Rev. A | Page 7 of 28
ADA4817-1/ADA4817-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±5 V, G = 1, (RF = 348 Ω for G > 1), RL = 100 Ω to ground, small signal V
unless noted otherwise.
6
G=1, SINGLEG=1,DUAL
3
0
G = 2
6
3
0
= 100 mV p-p, large signal V
OUT
G=1, SINGLE
G = 2
= 2 V p-p,
OUT
G = 1, DUAL
–3
–6
–9
NORMALIZED CLOSED-LO OP GAIN (dB)
–12
100k 10G
1M 10M 100M 1G
G=5
FREQUENCY (Hz)
Figure 8. Small Signal Frequency Response for Various Gains (LFCSP)
6
3
0
–3
–6
CLOSED-LOOP GAIN (dB)
–9
–12
100k 10G
1M 10M 100M 1G
Figure 9. Small Signal Frequency Response for Various Supplies
= 10V, SOIC
V
S
VS= 10V, LFCSP
VS=5V, LFCSP
VS= 5V, SOIC
FREQUENCY (Hz)
–3
–6
–9
NORMALIZED CLOSED-LO OP GAIN (dB)
–12
100k 10G
07756-066
1M 10M 100M 1G
G = 5
FREQUENCY (Hz)
07756-009
Figure 11. Large Signal Frequency Response for Various Gains
6
3
VS= 10V
0
–3
–6
CLOSED-LOOP GAIN (dB)
–9
V
= 1V p-p
OUT
–12
100k 10G
07756-007
1M 10M 100M 1G
Figure 12. Large Signal Frequency Response for Various Supplies
VS=5V
FREQUENCY (Hz)
07756-010
9
6
3
0
–3
CLOSED-LOOP GAIN (dB)
–6
G = 2
R
=274
F
–9
100k 10G
1M 10M 100M 1G
CL=6.6pF
CL=4.4pF
CL=0pF
FREQUENCY (Hz)
Figure 10. Small Signal Frequency Response for Various C
CL=2.2pF
07756-068
L
Rev. A | Page 8 of 28
9
RF= 348
6
3
0
–3
CLOSED-LOOP GAIN (dB)
–6
G = 2
–9
100k 10G
1M 10M 100M 1G
RF= 200
FREQUENCY (Hz)
RF=274
Figure 13. Small Signal Frequency Response for Various RF
07756-011
ADA4817-1/ADA4817-2
–
–
–
–
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
NORMALIZE D CLOSED-LOOP GAIN (dB)
–0.4
–0.5
100k 10G
G=2,SS
G=2,LS
G=1, SS
G = 1, LS
1M 10M 100M 1G
FREQUENCY (Hz)
07756-012
Figure 14. 0.1 dB Flatness Frequency Response vs. Gain and Output Voltage
6
3
0
–3
–6
CLOSED-LOOP GAIN (dB)
–12
TA = +25°C, SING LE
T
= +25°C, DUAL
A
T
= –40°C, SING LE
–9
A
T
= –40°C, DUAL
A
T
= +105°C, SI NGLE
A
T
= +105°C, DUAL
A
100k 1M 10M 100M 1G 10G
FREQUENCY (Hz)
Figure 17. Small Signal Frequency Response vs. Temperature
07756-036
20
–40
–60
–80
–100
DISTORT ION (dBc)
–120
–140
100k 100M
Figure 15. Distortion vs. Frequency for Various Loads, V
20
–40
–60
–80
–100
DISTORT ION (dBc)
–120
–140
100k 100M
HD2, RL = 100
HD2, RL = 1k
HD3, RL = 100
HD3, RL = 1k
1M 10M
FREQUENCY (Hz)
OUT
HD2, VS = 5V
HD2, VS = 10V
HD3, VS = 5V
HD3, VS = 10V
1M 10M
FREQUENCY (Hz)
Figure 16. Distortion vs. Frequency for Various Supplies, G = 2, V
= 2 V p-p
= 2 V p-p
OUT
20
–40
–60
HD3, VS = 5V
–80
–100
DISTORT ION (dBc)
–120
–140
07756-014
HD2, VS = 10V
100k 100M
Figure 18. Distortion vs. Frequency for Various Supplies, V
20
f
= 1MHz
C
–40
–60
–80
HD2, RL = 1k
–100
DISTORT ION (dBc)
–120
–140
06
07756-016
12345
HD2, VS = 5V
HD3, VS = 10V
1M 10M
FREQUENCY (Hz)
HD2, RL = 100
HD3, RL = 1k
OUTPUT VOLTAGE (V p-p)
HD3, RL = 100
= 2 V p-p
OUT
07756-013
07756-017
Figure 19. Distortion vs. Output Voltage for Various Loads
Rev. A | Page 9 of 28
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