ANALOG DEVICES ADA4424-6 Service Manual

6-Channel SD/ED/HD Video Filter with

V

O

FEATURES

3 SD channels; 18 MHz typical 1 dB bandwidth (BW)
3 ED/HD channels; 25 MHz or 34 MHz typical 1 dB BW
Fixed gain of 6.2 dB (2.042 V/V)
On-board negative supply for output coupling without

capacitors

Minimal dc offset at the output pins
Internal summation of Y and C channels for CVBS output
Flexible input dc offset cancellation for luma channels
D-terminal (EIAJ RC-5237 D5) and S-terminal (S1/S2) support
Capable of driving 2 back-terminated 75 Ω video loads

simultaneously
Separate power-down pins for SD and ED/HD sections
38-lead TSSOP package
Sony Green Partner Environmental Quality Approval

Program compliant

APPLICATIONS

DVD players and recorders
Set-top boxes
Projectors
Personal video recorders

GENERAL DESCRIPTION

The ADA4424-6 is a high performance video reconstruction filter
specifically designed for consumer applications. It consists of a
standard definition (SD) section with two fifth-order Butterworth
filters and a high definition (HD) section with three fifth-order
filters. The SD section contains an internal Y/C summer for CVBS
output, whereas the HD section provides selectable corner
frequencies for either extended definition (ED) or HD signals.

The ADA4424-6 filter/buffer section operates from a single 3.3 V
supply. Full support for D-terminal (EIAJ RC-5237 D5) and S1/S2
signaling is provided, along with a dedicated 5 V supply pin.
Separate enable pins are provided for the SD and HD sections.

Charge Pump

ADA4424-6

FUNCTIONAL BLOCK DIAGRAM

D1
D2
D3

S

Y_IN

C_IN

MODE0
MODE1

FFSET_ENB

HY_IN

HPb_IN

HPr_IN

FC_SEL
SD_ENABLE
HD_ENABLE

The luma channels (Y_IN, HY_IN) of the ADA4424-6 are
capable of detecting and cancelling dc input offsets of up to

1.1 V. Four distinct modes of detection/cancellation are
available.

The output drivers on the ADA4424-6 feature rail-to-rail outputs
with 6.2 dB gain. An on-board charge pump allows the outputs to
swing up to 1.4 V below ground, eliminating the need for large
coupling capacitors. Each output is capable of driving two 75 Ω
doubly terminated cables.

The ADA4424-6 is available in a 38-lead TSSOP and operates in
the industrial temperature range of −40°C to +85°C.

+3.3

VDD3_SD VDD3_HD VDD5

HD_ENB

SD_ENB

×1

×1

OFFSET

CANCELLATION

FC_SEL

×1

FC_SEL

×1

FC_SEL

×1

HD_ENBSD_ENB

POWER

MANAGEMENT

+3.3V

+5V

D/S
TERMINAL
CONTROL

LPF

LPF

LPF

LPF

LPF

CHARGE PUM P

C1b C2/CP_OUTVDD3_CP GND_CP

C1a

C1

Figure 1.

L1

L2

L3

S1/S2

×2

×2

×2

ADA4424-6

×2

×2

×2

C2

L1_OUT

L2_OUT

L3_OUT

S1/S2_OUT

Y_OUT

CVBS_OUT

C_OUT

HY_OUT

HPb_OUT

HPr_OUT

VSS_SD
VSS_HD

08550-001

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009-2010 Analog Devices, Inc. All rights reserved.

ADA4424-6

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6

Maximum Power Dissipation ..................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

REVISION HISTORY

07/10—Rev. B to Rev. C

Change to General Description Section ........................................ 1

05/10—Rev. A to Rev. B

Change to Table 1, Overall Performance ....................................... 3

Change to Ordering Guide ............................................................ 15

12/09—Rev. 0 to Rev. A

Changes to Table 1 ............................................................................ 4

Changes to Table 2 ............................................................................ 5

Changes to Table 5 .......................................................................... 10

Changes to Table 8 to Table 11 ...................................................... 11

Change to Table 12 and Table 13 .................................................. 12

10/09—Revision 0: Initial Version

Typical Performance Characteristics ..............................................9

Applications Information .............................................................. 11

CVBS Output .............................................................................. 11

Corner Frequency Selection ..................................................... 11

Input DC Offset Cancellation ................................................... 11

D-Terminal and S-Terminal Support ...................................... 12

Power-Down ............................................................................... 13

Charge Pump .............................................................................. 13

Printed Circuit Board (PCB) Layout ....................................... 13

Outline Dimensions ....................................................................... 15

Ordering Guide .......................................................................... 15

Rev. C | Page 2 of 16

ADA4424-6

SPECIFICATIONS

V

= 3.3 V, TA = 25°C, VO = 2.042 V p-p, RL = 150 Ω, dc-coupled outputs, unless otherwise noted. Charge pump configured as shown in

DD3

Figure 18.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

OVERALL PERFORMANCE

DC Voltage Gain All channels 6.0 6.2 6.4 dB
Input Voltage Range, All Inputs Not including dc offset −0.6 to +1.4 V
Output Voltage Range, All Outputs −1.6 to +3.0 V
Input Bias Current Y_IN, HY_IN, dc-coupled 30 pA
Input Impedance C_IN, HPb_IN, HPr_IN, ac-coupled 800 kΩ
Output Resistance

L1_OUT, L2_OUT, L3_OUT, S1/S2_OUT, dc-coupled 10.5 kΩ

SD CHANNEL DYNAMIC PERFORMANCE

In-Band Peaking f = 100 kHz to 6.75 MHz 0.00 0.01 dB
1 dB Bandwidth 14 18 MHz
Out-of-Band Rejection f = 148.5 MHz 38 42 dB
Crosstalk f = 1 MHz 67 dB
Total Harmonic Distortion f = 1 MHz, VO = 1.4 V p-p 0.07 %
Signal-to-Noise Ratio f = 100 kHz to 6 MHz, unweighted 68 dB
Group Delay Variation f = 100 kHz to 5 MHz 1 ns
Differential Gain NTSC 0.2 %
Differential Phase NTSC 0.5 Degrees

ED CHANNEL DYNAMIC PERFORMANCE FC_SEL = low (0)

In-Band Peaking f = 100 kHz to 13.5 MHz 0.02 0.1 dB
1 dB Bandwidth 21 25 MHz
Out-of-Band Rejection f = 148.5 MHz 38 42 dB
Crosstalk f = 1 MHz 65 dB
Total Harmonic Distortion f = 5 MHz, VO = 1.4 V p-p 0.45 %
Signal-to-Noise Ratio f = 100 kHz to 13.5 MHz, unweighted 66 dB
Group Delay Variation f = 100 kHz to 13.5 MHz 1.5 ns

HD CHANNEL DYNAMIC PERFORMANCE FC_SEL = high (1)

In-Band Peaking f = 100 kHz to 30 MHz 0.1 0.2 dB
1 dB Bandwidth Y Channel (HY_OUT) 30 39 MHz
P Channels (HPb_OUT, HPr_OUT) 25 34 MHz
Out-of-Band Rejection f = 148.5 MHz 33 37 dB
Crosstalk f = 1 MHz 65 dB
Total Harmonic Distortion f = 10 MHz, VO = 1.4 V p-p 1.2 %
Signal-to-Noise Ratio f = 100 kHz to 30 MHz, unweighted 65 dB
Group Delay Variation f = 100 kHz to 30 MHz 2.2 ns

DC CHARACTERISTICS

Operating Voltage, 3.3 V Supply 3.14 to 3.46 V
Quiescent Supply Current, 3.3 V Supply

SD disabled, SD_ENABLE = low, HD_ENABLE = high 54 mA
HD disabled, SD_ENABLE = high, HD_ENABLE = low 45 mA
Both disabled, SD_ENABLE = low, HD_ENABLE = low 6.1 10 mA
Operating Voltage, 5 V Supply 4.75 to 5.25 V

Y_OUT, C_OUT, CVBS_OUT, HY_OUT, HPb_OUT,
HPr_OUT, dc-coupled

Both active, SD_ENABLE = high, HD_ENABLE = high,
no load, no signal, not including D/S terminal outputs

0.5 Ω

93 133 mA

Rev. C | Page 3 of 16

ADA4424-6

Parameter Test Conditions/Comments Min Typ Max Unit

Quiescent Supply Current, 5 V Supply

SD_ENABLE = high, HD_ENABLE = high,

= 100 kΩ, D1, D2, D3 = high, S = high

R

L

SD_ENABLE = low, HD_ENABLE = low 5 15 μA
PSRR ED/HD channels, output referred −42 dB
SD channels, output referred −41 dB
DC Offset See Table 6 and Table 7

Input Referred, Offset Cancellation

OFFSET_ENB = low

Disabled Mode
SD Channels Y_IN = 0 V dc −60 −20 +60 mV
CVBS Channel Y_IN = 0 V dc −100 −40 +100 mV
ED/HD Channels HY_IN = 0 V dc −60 −20 +60 mV

Input Referred, Fixed Offset

OFFSET_ENB = high, MODE1 = high

Cancellation Mode
SD Fixed High Offset Mode Y_IN = 1.0 V dc, MODE0 = low −100 −30 +100 mV
ED/HD Fixed High Offset Mode HY_IN = 1.1 V dc, MODE0 = low −100 −38 +100 mV
SD Fixed Low Offset Mode Y_IN = 0.33 V dc, MODE0 = high −90 −17 +90 mV
ED/HD Fixed Low Offset Mode HY_IN = 0.33 V dc, MODE0 = high −100 −25 +100 mV

Input Referred, Auto Offset

OFFSET_ENB = high, MODE1 = low

Cancellation Mode
SD Auto Offset Mode

Y_IN = 0 V to 1.0 V dc, MODE0 = low −70 −36 +70 mV

Sync Tip Sampling

ED/HD Auto Offset Mode

HY_IN = 0 V to 1.1 V dc, MODE0 = low −95 −46 +95 mV

Sync Tip Sampling

SD Auto Offset Mode

Y_IN = 0 V to 1.0 V dc, MODE0 = high −25 −6 +25 mV

Back Porch Sampling

ED/HD Auto Offset Mode

HY_IN = 0 V to 1.1 V dc, MODE0 = high −25 −5 +25 mV

Back Porch Sampling
FC_SEL Input Logic Low Level 0 0.6 V
FC_SEL Input Logic High Level 1.2 V
xD_ENABLE, OFFSET_ENB, MODEx

0 0.8 V

Input Logic Low Level

xD_ENABLE, OFFSET_ENB, MODEx

2.0 V

Input Logic High Level
xD_ENABLE Assert Time xD_ENABLE = low to high 95 ns
xD_ENABLE Deassert Time xD_ENABLE = high to low 20 ns
xD_ENABLE Input Bias Current Disabled, xD_ENABLE = low 6.1 μA
Input-to-Output Isolation Disabled, xD_ENABLE = low, f = 5 MHz −100 dB

= 100 kΩ 0 0.6 V

D- and S-Terminal Input Logic

R

L

Low Level

= 100 kΩ 0.9 1.9 V

D- and S-Terminal Input Logic

R

L

Mid Level

= 100 kΩ 2.7 V

D- and S-Terminal Input Logic

R

L

High Level

= 100 kΩ 200 kΩ

D- and S-Terminal Input Logic Open

R

L

(Hi-Z) Resistance Value

V

D-Terminal (L1_OUT, L2_OUT, L3_OUT)

= 5.0 V, RL = 100 kΩ, D1, D2, D3 = low 0.0 V

DD5

Low Level Output

= 5.0 V, RL = 100 kΩ, D1, D3 = mid or open 2.1 V

D-Terminal (L1_OUT, L3_OUT) Mid

V

DD5

Level Output

= 5.0 V, RL = 100 kΩ, D1, D2, D3 = high 4.5 V

D-Terminal (L1_OUT, L2_OUT, L3_OUT)

V

DD5

High Level Output

V

S-Terminal (S1/S2_OUT) Low Level

= 5.0 V, RL = 100 kΩ, S = low 0.0 V

DD5

Output

190 200 μA

V

DD3

V

DD3

V

DD3

Rev. C | Page 4 of 16

ADA4424-6

Parameter Test Conditions/Comments Min Typ Max Unit

= 5.0 V, RL = 100 kΩ, S = mid or open 2.1 V

S-Terminal (S1/S2_OUT) Mid Level

Output

S-Terminal (S1/S2_OUT) High Level

Output

CHARGE PUMP CHARACTERISTICS

Output Voltage −1.66 V
Output Voltage Ripple 180 mV p-p
Output Ripple Frequency 100 kHz

V

DD5

V

= 5.0 V, RL = 100 kΩ, S = high 4.5 V

DD5

All channels operating; C1 = C2 = 4.7 μF, C3 = C4 =

1.0 μF, R1 = 1 Ω (see Figure 18)

Rev. C | Page 5 of 16