Integrated Triple Video Filter and Buffer with Selectable
C
T
www.BDTIC.com/ADI
Cutoff Frequencies and Multiplexed Inputs for RGB, HD/SD
ADA4411-3
FEATURES FUNCTIONAL BLOCK DIAGRAM
Sixth-order adjustable video filters
36 MHz, 18 MHz, and 9 MHz
Many video standards supported: RGB, YPbPr, YUV, SD, Y/C
Y1/G1 IN
Y2/G2 IN
36MHz, 18MHz, 9M Hz
×2
×4
Ideal for 720p and 1080i resolutions
−1 dB bandwidth of 30.5 MHz for HD
Low quiescent power
Pb1/B1 IN
Pb2/B2 IN
36MHz, 18MHz, 9M Hz
×2
×4
Only 265 mW for 3 channels on 5 V supply
Disable feature cuts supply current to 15 μA
2:1 mux on all inputs
Pr1/R1 IN
Pr2/R2 IN
36MHz, 18MHz, 9M Hz
×2
×4
Variable gain: ×2 or ×4
DC output offset adjust: ±0.5 V, input referred
Excellent video specifications
Wide supply range: +4.5 V to ±5 V
Rail-to-rail output
Output can swing 4.5 V p-p on single 5 V supply
Small packaging: 24-lead QSOP
APPLICATIONS
INPUT SELECT
LEVEL1
LEVEL2
UTOFF SELECT
GAIN SELECT
DISABLE
DC
OFFSET
2
ADA4411-3
Figure 1.
Set-top boxes
Personal video recorders
DVD players and recorders
HDTVs
Projectors
GENERAL DESCRIPTION
Y/G OUT
Pb/B OU
Pr/R OUT
05527-001
The ADA4411-3 is a comprehensive filtering solution designed
to give designers the flexibility to easily filter and drive various
video signals, including high definition video. Cutoff frequencies of the sixth-order video filters range from 9 MHz to
36 MHz and can be selected by two logic pins to obtain four
filter combinations that are tuned for RGB, high definition, and
standard definition video signals. The ADA4411-3 has a railto-rail output that can swing 4.5 V p-p on a single 5 V supply.
The ADA4411-3 offers gain and voltage offset adjustments.
ith a single logic pin, the throughput filter gain can be
W
selected to be ×2 or ×4. Output voltage offset is continuously
adjustable over an input-referred range of ±500 mV by applying
a differential voltage to an independent offset control input.
puts, which are useful in applications where filtering is
in
required for multiple sources of video signals.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The ADA4411-3 can operate on a single +5 V supply as well as
o
n ±5 V supplies. Single-supply operation is ideal in
applications where power consumption is critical. The disable
feature allows for further power conservation by reducing the
supply current to typically 15 µA when a particular device is not
in use.
Dual-supply operation is best for applications where the
ne
gative-going video signal excursions must swing at or
below ground while maintaining excellent video performance.
The output buffers have the ability to drive two 75 Ω doubly
terminated cables that are either dc-coupled or ac-coupled.
The ADA4411-3 is available in the 24-lead, wide body
P and is rated for operation over the extended
QSO
industrial temperature range of −40°C to +85°C. The ADA4411-3 offers 2:1 multiplexers on all of its video
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
ADA4411-3
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features .............................................................................................. 1
Overview ..................................................................................... 11
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration And Function Descriptions............................ 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
Applications..................................................................................... 11
REVISION HISTORY
7/05—Revision 0: Initial Version
Multiplexer Select Inputs........................................................... 11
Throughput Gain........................................................................ 11
Disable ......................................................................................... 11
Cutoff Frequency Selection ....................................................... 11
Output DC Offset Control........................................................ 11
Input and Output Coupling ...................................................... 12
Printed Circuit Board Layout ................................................... 13
Video Encoder Reconstruction Filter...................................... 13
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
Rev. 0 | Page 2 of 16
ADA4411-3
www.BDTIC.com/ADI
SPECIFICATIONS
VS = 5 V, @ TA = 25°C, VO = 1.4 V p-p, G = ×2, RL = 150 Ω, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
OVERALL PERFORMANCE
Offset Error Input referred, all channels 12 30 mV
Offset Adjust Range Input referred ±500 mV
Input Voltage Range, All Inputs VS− − 0.1 VS+ − 2.0 V
Output Voltage Swing, All Outputs Positive swing VS+ − 0.33 VS+ − 0.22 V
Negative swing VS− + 0.10 VS− + 0.13 V
Linear Output Current per Channel 30 mA
Integrated Voltage Noise, Referred to Input All channels 0.52 mV rms
Filter Input Bias Current All channels 6.6 μA
Total Harmonic Distortion at 1 MHz FC = 36 MHz, FC = 18 MHz/FC = 9 MHz 0.01/0.04 %
Gain Error Magnitude G = ×2/G = ×4 0.13/0.15 0.38/0.40 dB
FILTER DYNAMIC PERFORMANCE
−1 dB Bandwidth Cutoff frequency select = 36 MHz 26.5 30.5 MHz
Cutoff frequency select = 18 MHz 13.5 15.5 MHz
Cutoff frequency select = 9 MHz 6.5 7.8 MHz
−3 dB Bandwidth Cutoff frequency select = 36 MHz 34 37 MHz
Cutoff frequency select = 18 MHz 16 18 MHz
Cutoff frequency select = 9 MHz 8 9 MHz
Out-of-Band Rejection f = 75 MHz −31 −43 dB
Crosstalk f = 5 MHz, FC = 36 MHz −62 dB
Input Mux Isolation f = 1 MHz, R
Propagation Delay f = 5 MHz, FC = 36 MHz 20 ns
Group Delay Variation Cutoff frequency select = 36 MHz 7 ns
Cutoff frequency select = 18 MHz 11 ns
Cutoff frequency select = 9 MHz 24 ns
Differential Gain NTSC, FC = 9 MHz 0.16 %
Differential Phase NTSC, FC = 9 MHz 0.05 Degrees
CONTROL INPUT PERFORMANCE
Input Logic 0 Voltage All inputs except DISABLE 0.8 V
Input Logic 1 Voltage All inputs except DISABLE 2.0 V
Input Bias Current All inputs except DISABLE 10 15 μA
DISABLE PERFORMANCE
DISABLE Assert Voltage VS+ − 0.5 V
DISABLE Assert Time 100 ns
DISABLE Deassert Time 130 ns
DISABLE Input Bias Current 10 15 μA
Input-to-Output Isolation—Disabled f = 10 MHz 90 dB
POWER SUPPLY
Operating Range 4.5 12 V
Quiescent Current 53 56 mA
Quiescent Current—Disabled 15 150 μA
PSRR, Positive Supply All channels 62 70 dB
PSRR, Negative Supply All channels 57 65 dB
= 300 Ω 91 dB
SOURCE
Rev. 0 | Page 3 of 16
ADA4411-3
www.BDTIC.com/ADI
VS = ±5 V, @ TA = 25°C, VO = 1.4 V p-p, G = ×2, RL = 150 Ω, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
OVERALL PERFORMANCE
Offset Error Input referred, all channels 13 32 mV
Offset Adjust Range Input referred ±500 mV
Input Voltage Range, All Inputs VS− − 0.1 VS+ − 2.0 V
Output Voltage Swing, All Outputs Positive swing VS+ − 0.42 VS+ − 0.24 V
Negative swing VS− + 0.24 VS− + 0.42 V
Linear Output Current per Channel 30 mA
Integrated Voltage Noise, Referred to Input All channels 0.50 mV rms
Filter Input Bias Current All channels 6.3 μA
Total Harmonic Distortion at 1 MHz FC = 36 MHz, FC = 18 MHz/FC = 9 MHz 0.01/0.03 %
Gain Error Magnitude G = ×2/G = ×4 0.13/0.13 0.34/0.36 dB
FILTER DYNAMIC PERFORMANCE
−1 dB Bandwidth Cutoff frequency select = 36 MHz 30.0 MHz
Cutoff frequency select = 18 MHz 15.0 MHz
Cutoff frequency select = 9 MHz 7.8 MHz
−3 dB Bandwidth Cutoff frequency select = 36 MHz 33 36 MHz
Cutoff frequency select = 18 MHz 17 18 MHz
Cutoff frequency select = 9 MHz 8 9 MHz
Out-of-Band Rejection f = 75 MHz −31 −42 dB
Crosstalk f = 5 MHz, FC = 36 MHz −62 dB
Input MUX Isolation f = 1 MHz, R
Propagation Delay f = 5 MHz, FC = 36 MHz 19 25 ns
Group Delay Variation Cutoff frequency select = 36 MHz 7 ns
Cutoff frequency select = 18 MHz 13 ns
Cutoff frequency select = 9 MHz 22 ns
Differential Gain NTSC, FC = 9 MHz 0.04 %
Differential Phase NTSC, FC = 9 MHz 0.16 Degrees
CONTROL INPUT PERFORMANCE
Input Logic 0 Voltage All inputs except DISABLE 0.8 V
Input Logic 1 Voltage All inputs except DISABLE 2.0 V
Input Bias Current All inputs except DISABLE 10 15 μA
DISABLE PERFORMANCE
DISABLE Assert Voltage VS+ − 0.5 V
DISABLE Assert Time 75 ns
DISABLE Deassert Time 125 ns
DISABLE Input Bias Current 34 45 μA
Input-to-Output Isolation—Disabled f = 10 MHz 90 dB
POWER SUPPLY
Operating Range 4.5 12 V
Quiescent Current 57 60 mA
Quiescent Current—Disabled 15 150 μA
PSRR, Positive Supply All channels 64 74 dB
PSRR, Negative Supply All channels 57 65 dB
= 300 Ω 91 dB
SOURCE
Rev. 0 | Page 4 of 16
ADA4411-3
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 12 V
Power Dissipation See Figure 2
Storage Temperature –65°C to +125°C
Operating Temperature Range –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ is specified for the worst-case conditions, that is, θ
JA JA
specified for device soldered in circuit board for surface-mount
packages.
Table 4. Thermal Resistance
Package Type θ Unit
24 Lead QSOP 83 °C/W
JA
Maximum Power Dissipation
The maximum safe power dissipation in the ADA4411-3
package is limited by the associated rise in junction temperature
(T
) on the die. At approximately 150°C, which is the glass
J
transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4411-3.
Exceeding a junction temperature of 150°C for an extended
period can result in changes in the silicon devices potentially
causing failure.
is
The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
quiescent current (I
depends on the particular application. For each output, the
power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the device. The
power dissipated due to all of the loads is equal to the sum of
the power dissipations due to each individual load. RMS
voltages and currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θ
In addition, more metal directly in contact with the package
leads from metal traces, through-holes, ground, and power
planes reduces the θ .
Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 24-lead QSOP
(83°C/W) on a JEDEC standard 4-layer board. θ
approximations.
2.5
2.3
2.1
1.9
1.7
1.5
WATTS
1.3
1.1
0.9
0.7
0.5
–40 –20 0 20 40 60
Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
). The power dissipated due to load drive
S
JA
AMBIENT TEMP E R A TURE (°C)
) is the sum of the
D
) times the
S
values are
JA
.
JA
80
05527-002
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 16
ADA4411-3
A
www.BDTIC.com/ADI
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LEVEL1
DISABLE
Pb1/B1
F_SEL_
F_SEL_B
Pb2/B2
1
2
3
Y1/G1
4
GND
5
ADA4411-3
6
GND
Pr1/R1
Y2/G2
DGND
Figure 3. 24-Lead QSOP Pin
(Not to Scale)
7
8
9
10
11
12
TOP VIEW
Table 5. 24-Lead QSOP Pin Function Descriptions
Pin No. Name Description
1 LEVEL1 DC Level Adjust Pin 1
2 DISABLE Disable/Power Down
3 Y1/G1
4 GND
5 Pb1/B1
6 GND
7 Pr1/R1
8 F_SEL_A
9 F_SEL_B
10 Y2/G2
11 DGND
12 Pb2/B2
13 DGND
14 Pr2/R2
15 MUX
16 VCC
17 Pr/R_OUT
18 VEE
19 Pb/B_OUT
20 VEE
21 Y/G_OUT
22 VCC
23 G_SEL
Channel 1 Y/G Video Input
Signal Ground Reference
Channel 1 Pb/B Video Input
Signal Ground Reference
Channel 1 Pr/R Video Input
Filter Cutoff Select Input A
Filter Cutoff Select Input B
Channel 2 Y/G Video Input
Digital Ground Reference
Channel 2 Pb/B Video Input
Digital Ground Reference
Channel 2 Pr/R Video Input
Input Mux Select Line
Positive Power Supply
Pr/R Video Output
Negative Power Supply
Pb/B Video Output
Negative Power Supply
Y/G Video Output
Positive Power Supply
Gain Select
24 LEVEL2 DC Level Adjust Pin 2
24
LEVEL2
23
G_SEL
22
VCC
21
Y/G_OUT
20
VEE
19
Pb/B_OUT
18
VEE
17
Pr/R_OUT
16
VCC
15
MUX
14
Pr2/R2
13
DGND
Configuration
05527-003
Rev. 0 | Page 6 of 16
ADA4411-3
www.BDTIC.com/ADI
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, G = ×2, RL = 150 , V = 1.4 V p-p, V = 5 V, T = 25°C.
9
6
3
0
–3
–6
–9
–12
–15
–18
–21
–24
GAIN (dB)
–27
–30
–33
–36
–39
–42
–45
–48
110100
6.5
6.0
FC = 9MHz
FC = 18MHz
BLACK LINE: VS = +5V
GRAY LI NE : V
= ±5V
S
FREQUENCY ( MHz)
Figure 4. Frequency Response vs. Power Supply and
Cutoff Freque
ncy (G = ×2)
O S A
FC = 36MHz
FC = 36MHz
15
12
9
6
3
FC = 9MHz
0
–3
–6
–9
–12
–15
–18
GAIN (dB)
–21
–24
–27
BLACK LINE: VS = +5V
–30
GRAY LI NE : V
–33
–36
–39
05527-004
–42
–45
1 10 100
FC = 18MHz
= ±5V
S
FREQUENCY (MHz)
FC = 36MHz
Figure 7. Frequency Response vs. Power Supply and
Cutoff Frequency (G = ×4)
12.5
12.0
05527-007
5.5
FC = 9MHz
5.0
4.5
GAIN (dB)
4.0
BLACK LINE: VS = +5V
GRAY LI NE : V
3.5
3.0
110
FC = 18MHz
= ±5V
S
FREQUENCY ( MHz)
Figure 5. Frequency Response Flatness vs. Power Supply and
Cutoff Freque
9
6
3
0
–3
–6
–9
–12
–15
–18
–21
–24
GAIN (dB)
–27
–30
–33
–36
–39
–42
–45
–48
110100
FC = 9MHz
BLACK LINE:
V
= 100mV p- p
OUT
GRAY LINE:
V
= 2V p-p
OUT
FC = 18MHz
Figure 6. Frequency Response vs. Cut
ncy (G = ×2)
FC = 36MHz
FREQUENCY ( MHz)
off Frequency and Output Amplitude
11.5
11.0
10.5
GAIN (dB)
10.0
9.5
05527-005
100
9.0
FC = 9MHz
FC = 18MHz
BLACK LINE: VS = +5V
GRAY LI NE : V
110
= ±5V
S
FREQUENCY (MHz)
FC = 36MHz
Figure 8. Frequency Response Flatness vs. Power Supply and Cutoff Frequency
(G = ×4)
9
6
3
0
–3
–6
–9
–12
–15
–18
–21
–24
GAIN (dB)
–27
–30
–33
–36
–39
–42
05527-006
–45
–48
110100
FC = 9MHz
FC = 18MHz
–40°C
+25°C
+85°C
FREQUENC Y (MHz)
FC = 36MHz
Figure 9. Frequency Response vs. Temperature and Cutoff Frequency
05527-008
100
05527-009
Rev. 0 | Page 7 of 16
ADA4411-3
–
–
www.BDTIC.com/ADI
100
90
80
FC = 9MHz
70
60
50
FC = 18MHz
40
GROUP DELAY (ns)
30
20
FC = 36MHz
10
110
FREQUENCY (MHz)
Figure 10. Group Delay vs. Frequency, Pow
BLACK LINE : VS = +5V
GRAY LINE : V
er Supply, and Cutoff Frequency
= ±5V
S
05527-010
100
3.5
2 × INPUT
3.3
3.1
2.9
2.7
2.5
2.3
2.1
OUTPUT VOLTAGE (V)
1.9
1.7
1.5
OUTPUT
0.5% (70ns)
ERROR
1% (58ns)
Figure 13. Settling Time
2.5
2.0
1.5
1.0
0.5
0
–0.5
ERROR (%)
–1.0
–1.5
50ns/DIV
–2.0
–2.5
05527-013
30
R
= 300Ω
SOURCE
Y AND Pr SOU RCE CHANNELS
–40
Pb RECEPTOR CHANNEL
–50
–60
–70
–80
–90
–100
CROSSTALK REFER RE D TO INPUT (dB)
–110
0.1 1 10 100
Figure 11. Channel-to-Channel Crossta
FC = 9MHz
FREQUE NC Y ( MHz)
lk vs. Frequency and Cutoff Frequency
3.5
3.3
3.1
F
= 36MHz
C
2.9
2.7
= 18MHz
F
2.5
C
FC = 9MHz
2.3
2.1
OUTPUT VOLTAGE (V)
1.9
1.7
1.5
Figure 12. Transient Response vs.
FC = 36MHz
FC = 18MHz
100ns/DIV
Cutoff Frequency (G = ×2)
40
R
= 300
FC = 9MHz
Ω
FC = 36MHz
FREQUENC Y ( MHz)
FC = 9MHz
FC = 18MHz
uency and Cutoff Frequency
100ns/DIV
05527-012
05527-015
SOURCE
UNSELECTED MUX IS DRIVEN
–50
–60
–70
–80
–90
–100
MUX ISO LATIO N RE FERRED TO INPUT (dB)
05527-011
–110
0.1 1 10 100
Figure 14. MUX Isolation vs. Freq
3.5
3.3
3.1
F
= 36MHz
C
2.9
2.7
= 18MHz
F
C
2.5
2.3
2.1
OUTPUT VOLTAGE (V)
1.9
1.7
05527-014
1.5
Figure 15. Transient Response vs. Cutoff Frequency (G = ×4)
Rev. 0 | Page 8 of 16
ADA4411-3
K
K
www.BDTIC.com/ADI
5
5
–5
–15
–25
–35
–45
–55
PSRR REFE RRE D TO INP UT (dB)
–65
–75
0.1 1 10 100
FC = 9MHz
FC = 36MHz
FREQUENCY (MHz)
Figure 16. Positive Supply PSRR vs. Frequency
6
F
= 36MHz
C
5
4
= 9MHz
F
C
FC = 18MHz
3
2
OUTPUT VOLTAGE (V)
1
2× INPUT
FC = 18MHz
and Cutoff Frequency
–5
–15
–25
–35
–45
–55
PSRR REFERRED TO INPUT (dB)
–65
05527-016
–75
0.1 1 10 100
FC = 9MHz
Figure 18. Negative Supply PSRR vs. Frequen
FC = 18MHz
FC = 36MHz
FREQUENC Y ( M Hz )
cy and Cutoff Frequency
NETWOR
ANALYZER Tx
50Ω 118Ω
DUT
50Ω 86.6Ω
R
L
= 150Ω
NETWOR
ANALYZER Rx
50Ω
05527-017
0
MINIMUM-LOSS MATCHING NETWORK LOSS CALIBRATED OUT
Figure 19. Basic Test Circuit for Swept Frequency Measurements
05527-051
–1
Figure 17. Overdrive Recove
ry vs. Cutoff Frequency
200ns/DIV
05527-022
Rev. 0 | Page 9 of 16
ADA4411-3
www.BDTIC.com/ADI
THEORY OF OPERATION
The ADA4411-3 is an integrated video filtering and driving
solution that offers variable bandwidth to meet the needs of a
number of different video resolutions. There are three filters,
targeted for use with component video signals. The filters
have selectable bandwidths that correspond to the popular
component video standards. Each filter has a sixth-order
Butterworth response that includes group delay optimization.
The group delay variation from 1 MHz to 36 MHz in the
36 MHz section is 7 ns, which produces a fast settling pulse
response.
The ADA4411-3 is designed to operate in many video
e
nvironments. The supply range is 5 V to 12 V, single supply or
dual supply, and requires a relatively low nominal quiescent
current of 15 mA per channel. In single-supply applications,
the PSRR is greater than 60 dB, providing excellent rejection
in systems with supplies that are noisy or under-regulated. In
applications where power consumption is critical, the part
can be powered down to draw typically 15 µA by pulling the
DISABLE pin to the most positive rail. The ADA4411-3 is also
well-suited for high encoding frequency applications because it
maintains a stop-band attenuation of more than 40 dB to 400 MHz.
The ADA4411-3 is intended to take dc-coupled inputs
rom an encoder or other ground referenced video signals.
f
The ADA4411-3 input is high impedance. No minimum or
maximum input termination is required, though input
terminations above 1 kΩ can degrade crosstalk performance
at high frequencies. No clamping is provided internally. For
applications where dc restoration is required, dual supplies
work best. Using a termination resistance of less than a few
hundred ohms to ground on the inputs and suitably adjusting
the level-shifting circuitry provides precise placement of the
output voltage.
For single-supply applications (V
range extends from 100 mV below ground to within 2.0 V of
the most positive supply. Each filter section has a 2:1 input
multiplexer that includes level-shifting circuitry. The levelshifting circuitry adds a dc component to ground-referenced
input signals so that they can be reproduced accurately without
the output buffers hitting the negative rail. Because the filters
have negative rail input and rail-to-rail output, dc level shifting
is generally not necessary, unless accuracy greater than that of
the saturated output of the driver is required at the most
negative edge. This varies with load but is typically 100 mV
in a dc-coupled, single-supply application. If ac coupling is
used, the saturated output level is higher because the drivers
have to sink more current on the low side. If dual supplies are
used (V
applications, the level-shifting circuitry can be used to take a
ground referenced signal and put the blanking level at ground
while the sync level is below ground.
The output drivers on the ADA4411-3 have rail-to-rail output
ca
respect to the ground pins. Gain is controlled by the external
gain select pin. Each output is capable of driving two ac- or dccoupled 75 Ω source-terminated loads. If a large dc output level
is required while driving two loads, ac coupling should be used
to limit the power dissipation.
Input MUX isolation is primarily a function of the source
esistance driving into the ADA4411-3. Higher resistances
r
result in lower isolation over frequency, while a low source
resistance, such as 75 Ω, has the best isolation performance.
See
< GND), no level shifting is required. In dual-supply
S−
pabilities. They provide either 6 dB or 12 dB of gain with
Figure 14 for the MUX isolation performance.
= GND), the input voltage
S−
Rev. 0 | Page 10 of 16
ADA4411-3
www.BDTIC.com/ADI
APPLICATIONS
OVERVIEW CUTOFF FREQUENCY SELECTION
With its high impedance multiplexed inputs and high output
drive, the ADA4411-3 is ideally suited to video reconstruction
and antialias filtering applications. The high impedance inputs
give designers flexibility with regard to how the input signals
are terminated. Devices with DAC current source outputs that
feed the ADA4411-3 can be loaded in whatever resistance
provides the best performance, and devices with voltage outputs
can be optimally terminated as well. The ADA4411-3 outputs
can each drive up to two source-terminated 75 Ω loads and can
therefore directly drive the outputs from set-top boxes, DVD
players, and the like without the need for a separate output
buffer.
Binary control inputs are provided to select cutoff frequency,
throughput gain, and input signal. These inputs are compatible
with 3 V and 5 V TTL and CMOS logic levels referenced to
GND. The disable feature is asserted by pulling the DISABLE
pin to the positive supply.
The LEVEL1 and LEVEL2 inputs comprise a differential input
t controls the dc level at the output pins.
tha
Four combinations of cutoff frequencies are provided for the
video signals. The cutoff frequencies have been selected to
correspond with the most commonly deployed component
video scanning systems. Selection between the cutoff frequency
combinations is controlled by the logic signals applied to the
F_SEL_A and F_SEL_B inputs.
fr
equency selection.
Table 7. Filter Cutoff Frequency Selection
F_SEL_A F_SEL_B Y/G Cutoff Pb/B Cutoff Pr/R Cutoff
0 0 36 MHz 36 MHz 36 MHz
0 1 36 MHz 18 MHz 18 MHz
1 0 18 MHz 18 MHz
1 1 9 MHz 9 MHz 9 MHz
Tabl e 7 summarizes cutoff
18 MHz
OUTPUT DC OFFSET CONTROL
The LEVEL1 and LEVEL2 inputs work as a differential, inputreferred output offset control. In other words, the output offset
voltage of a given channel is equal to the difference in voltage
between the LEVEL1 and LEVEL2 inputs, multiplied by the
overall filter gain. This relationship is expressed in Equation 1.
MULTIPLEXER SELECT INPUTS
Selection between the two multiplexer inputs is controlled by
the logic signals applied to the MUX inputs. Tabl e 6
rizes the multiplexer operation.
summa
THROUGHPUT GAIN
The throughput gain of the ADA4411-3 signal paths can
be either × 2 or × 4. Gain selection is controlled by the logic
signal applied to the G_SEL pin. Tabl e 6 summarizes how the
ga
in is selected.
DISABLE
The ADA4411-3 includes a disable feature that can be used
to save power when a particular device is not in use. As
indicated in the Overview section, the disable feature is
a
sserted by pulling the DISABLE pin to the positive supply.
Tabl e 6 summarizes the disable feature operation. The
DISABLE p
inputs and therefore must be connected to ground when the
device is not disabled.
Table 6. Logic Pin Function Description
DISABLE MUX G_SEL
VS+ = Disabled 1 = Channel 1 Selected 1 = ×2 Gain
GND = Enabled 0 = Channel 2 Selected 0 = ×4 Gain
in also functions as a reference level for the logic
(1)
))(()( GLEVELLEVELOUTV
OS
LEVEL1 and LEVEL2 are the voltages applied to the respective
inputs, and G is the throughput gain.
For example, with the G_SEL input set for ×2 gain, setting
LE
VEL1 to 300 mV and LEVEL2 to 0 V shifts the offset voltages
at the ADA4411-3 outputs to 600 mV. This particular setting
can be used in most single-supply applications to keep the
output swings safely above the negative supply rail.
The maximum differential voltage that can be applied across the
VEL1 and LEVEL2 inputs is ±500 mV. From a single-ended
LE
standpoint, the LEVEL1 and LEVEL2 inputs have the same
range as the filter inputs. See the
ts. The LEVEL1 and LEVEL2 inputs must each be bypassed
limi
to GND with a 0.1 µF ceramic capacitor.
In single-supply applications, a positive output offset must be
a
pplied to keep the negative-most excursions of the output
signals above the specified minimum output swing limit.
21−=
Specifications tables for the
Rev. 0 | Page 11 of 16
ADA4411-3
A
www.BDTIC.com/ADI
Figure 20 and Figure 21 illustrate several ways to use the
LEVEL1 and LEVEL2 inputs.
Figure 20 shows examples of how
to generate fully adjustable LEVEL1 and LEVEL2 voltages from
±5 V and single +5 V supplies. These circuits show a general
case, but a more practical approach is to fix one voltage and
vary the other.
a 600 mV o
Figure 21 illustrates an effective way to produce
utput offset voltage in a single-supply application.
Although the LEVEL2 input could simply be connected to
GND,
Figure 21 includes bypassed resistive voltage dividers for
eac
h input so that the input levels can be changed, if necessary.
Additionally, many in-circuit testers require that I/O signals not
be tied directly to the supplies or GND. DNP indicates do not
populate.
DUAL SUPPLY
+5V
9.53kΩ
1kΩ
9.53kΩ
–5V
+5V
9.09kΩ
1kΩ
Figure 20. Generating Fully Adjusta
LEVEL1
0.1μF
SINGLE SUPPLY
LEVEL1
0.1μF
+5V
9.53kΩ
1kΩ
9.53kΩ
–5V
+5V
9.09kΩ
1kΩ
ble Output Offsets
0.1μF
0.1μF
LEVEL2
LEVEL2
05527-018
+5V
10kΩ
LEVEL1
634Ω
Figure 21. Flexible Circuits to Set the LEVEL1 and LEVEL2 Inputs to
Obt
0.1μF
ain a 600 mV Output Offset on a Single Supply
DNP
0Ω
+5V
DNP
LEVEL2
05527-019
INPUT AND OUTPUT COUPLING
Inputs to the ADA4411-3 are normally dc-coupled. Ac coupling
he inputs is not recommended; however, if ac coupling is
t
necessary, suitable circuitry must be provided following the ac
coupling element to provide proper dc level and bias currents at
the ADA4411-3 input stages. The ADA4411-3 outputs can be
either ac- or dc-coupled.
When driving single ac-coupled loads in standard 75 Ω video
tribution systems, 220 µF coupling capacitors are recom-
dis
mended for use on all but the chrominance signal output. Since
the chrominance signal is a narrow-band modulated carrier, it
has no low frequency content and can therefore be coupled with
a 0.1 µF capacitor.
There are two ac coupling options when driving two loads from
one output. One simply uses the same value capacitor on the
second load, while the other is to use a common coupling
capacitor that is at least twice the value used for the single load
(see
Figure 22 and Figure 23).
75Ω
220μF
470μF
75Ω
220μF
75Ω
75Ω
75Ω
ds with One Common Coupling Capacitor
DA4411-3
Figure 22. Driving Two AC-Coupled Loads with Two Coupling Capacitors
ADA4411-3
Figure 23. Driving Two AC-Coupled Loa
CABLE
CABLE
75Ω
CABLE
75Ω
CABLE
75Ω
75Ω
75Ω
75Ω
75Ω
05527-020
05527-021
Rev. 0 | Page 12 of 16
When driving two parallel 150 Ω loads (75 Ω effective load),
the 3 dB bandwidth of the filters typically varies from that of
the filters with a single 150 Ω load. For the 9 MHz and 18 MHz
filters, the typical variation is within ±1.0%; for the 36 MHz
filters, the typical variation is within ±2.5%.
ADA4411-3
www.BDTIC.com/ADI
PRINTED CIRCUIT BOARD LAYOUT
As with all high speed applications, attention to printed
circuit board layout is of paramount importance. Standard high
speed layout practices should be adhered to when designing
with the ADA4411-3. A solid ground plane is recommended,
and surface-mount, ceramic power supply decoupling
capacitors should be placed as close as possible to the supply
pins. All of the ADA4411-3 GND pins should be connected to
the ground plane with traces that are as short as possible.
Controlled impedance traces of the shortest length possible
should be used to connect to the signal I/O pins and should not
pass over any voids in the ground plane. A 75 Ω impedance
level is typically used in video applications. All signal outputs of
the ADA4411-3 should include series termination resistors
when driving transmission lines.
When the ADA4411-3 receives its inputs from a device
wi
th current outputs, the required load resistor value for
the output current is often different from the characteristic
impedance of the signal traces. In this case, if the interconnections are sufficiently short (<< 0.1 wavelength), the trace
does not have to be terminated in its characteristic impedance.
Traces of 75 can be used in this instance, provided their
lengths are an inch or two at the most. This is easily achieved
because the ADA4411-3 and the device feeding it are usually
adjacent to each other, and connections can be made that are
less than one inch in length.
VIDEO ENCODER RECONSTRUCTION FILTER
The ADA4411-3 is easily applied as a reconstruction filter at
the DAC outputs of a video encoder. Figure 24 illustrates how to
se the ADA4411-3 in this type of application with an ADV7322
u
video encoder in a single-supply application with ac-coupled
outputs.
Rev. 0 | Page 13 of 16
ADA4411-3
www.BDTIC.com/ADI
5V
(ANALOG)
0.1μF
0.1μF
ADV7322
VIDEO ENCODER
10kΩDNP
BINARY
CONTROL
INPUTS
0.1μF
1
24
2
23
15
8
9
3
10
LEVEL1
LEVEL2
DISABLE
G_SEL
MUX
F_SEL_A
F_SEL_B
Y1/G1
Y2/G2
0Ω
R
L
634Ω
0.1μF
16
VCC
ADA4411-3
VCC
22
Y/G_OUT
220μF
75Ω
21
VIDEO
DAC
OUTPUTS
5
CHANNEL 2
VIDEO
INPUTS
Pb1/B1
R
L
R
L
12
14
7
Pb2/B2
Pr1/R1
Pr2/R2
GND
4, 6
DGND
11, 13
Pb/B_OUT
Pr/R_OUT
VEE
18, 20
Figure 24. The ADA4411-3 Applied as a Single-Supply Reconstruction Filter Following the ADV7322
220μF
75Ω
19
220μF
75Ω
17
05527-024
Rev. 0 | Page 14 of 16
ADA4411-3
Y
www.BDTIC.com/ADI
OUTLINE DIMENSIONS
0.341
BSC
PIN 1
0.010
0.004
COPLANARIT
0.004
24 13
1
0.065
0.049
0.025
BSC
COMPLIANT TO JEDEC STANDARDS MO-137AE
Figure 25. 24-Lead Shrink Small Outline Package [QSOP]
0.069
0.053
0.012
0.008
Dimensions shown in inches
(R
12
Q-24)
0.154
BSC
SEATING
PLANE
0.236
BSC
0.010
0.006
8°
0°
0.050
0.016
ORDERING GUIDE
Model Temperature Range Package Description Order Quantity Package Option
ADA4411-3ARQZ –40°C to +85°C 24-Lead QSOP 1 RQ-24
ADA4411-3ARQZ-R7 –40°C to +85°C 24-Lead QSOP 1,000 RQ-24
ADA4411-3ARQZ-RL –40°C to +85°C 24-Lead QSOP 2,500 RQ-24
1
Z = Pb-free part.
1
1
1
Rev. 0 | Page 15 of 16
ADA4411-3
www.BDTIC.com/ADI
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05527–0–7/05(0)
Rev. 0 | Page 16 of 16
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