ANALOG DEVICES ADA4320-1 Service Manual

Low Distortion, DOCSIS 3.0, Upstream CATV

FEATURES

Supports CableLabs® DOCSIS 3.0/2.0 and EuroDOCSIS

3.0/2.0 specifications for customer premises equipment

(CPE) upstream transmission
5 V single-supply operation
Excellent adjacent channel rejection performance

−66 dBc ACPR for a single QPSK channel

−63 dBc ACPR for 4× QAM64 channels

Gain programmable in 1 dB steps over a 59 dB range

Gain range: −27 dB to +32 dB
Current-scaled output stage
Low between-burst output noise level

−70 dB mV in 160 kHz bandwidth

Maintains constant output impedance in enable, disable,

and sleep conditions
Selectable low power modes

12 mA in Tx disable

12 μA in sleep mode (full power-down)
3-wire, SPI-compatible interface
4 mm × 5 mm 24-lead LFCSP, RoHS compliant

VIN–

VIN+

FUNCTIONAL BLOCK DIAGRAM

DIFF O R
SINGLE
INPUT
AMP

(SINGLE) = 320Ω

Z

IN

(DIFF) = 640Ω

Z

IN

ADA4320-1

VERNIER

DATEN TXEN SLEEP

ATTENUATI ON

DATA LATCH

REGISTER

CLKSDATAGND

Figure 1.

CORE

8

DECODE

8

8

SHIFT

Line Driver

ADA4320-1

POWER

AMP

Z

DIFF =

OUT

300Ω

POWER-DO WN

LOGIC

VOUT+

VOUT–

RAMP

08707-001

APPLICATIONS

DOCSIS 3.0 and EuroDOCSIS cable modems/E-MTAs
DOCSIS 3.0 set-top boxes
CATV telephony modems
Coaxial or twisted pair line drivers

GENERAL DESCRIPTION

The ADA4320-1 is a high power, ultralow distortion amplifier
designed for CATV reverse channel line driving. Its features and
specifications make the ADA4320-1 ideally suited for DOCSIS 3.0­and EuroDOCSIS 3.0-based applications. Both gain and output
stage current are controlled via a 3-wire (SPI-compatible) interface.
A single 8-bit serial word selects one of four available supply
current presets and one of sixty gain codes.

The ADA4320-1 has been tailored to address both the high output
drive and stringent fidelity requirements of DOCSIS 3.0. The
part is able to maintain excellent adjacent channel rejection
performance over the full 5 MHz to 85 MHz range, even with
multiple bonded channels at maximum specified output levels.

The ADA4320-1 accepts a differential or single-ended input
signal. The output is specified for driving a single-ended 75 Ω
load through a 4:1 impedance transformer.

The ADA4320-1 features an output driver stage that scales
quiescent current consumption according to gain setting. In
multichannel mode at maximum gain (32 dB), the device draws
260 mA from a single 5 V supply, enabling the high power,
ultralow distortion performance required by multiple DOCSIS 3.0
upstream channels. For lifeline E-MTA applications, the ADA4320-1
output stage current can be throttled via SPI commands, reducing
the power requirement for single-channel transmission by up to
30%. In transmit-disable mode, the ADA4320-1 draws only 12 mA.
The device also features a full power-down sleep mode that
further reduces current draw to12 µA typical.

The ADA4320-1 is packaged in a RoHS-compliant, 24-lead
exposed pad LFCSP and is rated for operation over the −40°C
to +85°C temperature range.

Rev. A

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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

ADA4320-1

TABLE OF CONTENTS

Features .............................................................................................. 1

General Applications ................................................................. 11

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Logic Inputs (TTL-/CMOS-Compatible Logic) ....................... 4

Timing Requirements .................................................................. 5

Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6

Maximum Power Dissipation ..................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Applications Information .............................................................. 11

Circuit Description .................................................................... 11

Programming .............................................................................. 11

Current Level and Gain Adjustment ....................................... 11

Power Saving Features ............................................................... 12

Input Bias, Impedance, and Termination ................................ 12

Output Bias, Impedance, and Termination ............................ 12

Power Supply ............................................................................... 12

Signal Integrity Layout Considerations ................................... 12

Initial Power-Up ......................................................................... 12

RAMP Pin Feature ..................................................................... 13

Output Transformer ................................................................... 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

REVISION HISTORY

10/10—Rev. 0 to Rev. A

Changes to Product Title ................................................................. 1

Changes to Pin 14, Description, Table 6 ........................................ 7

Changes to Current Level and Gain Adjustment Section ......... 11

Changes to Output Bias, Impedance, and

Termination Section ....................................................................... 12

Changes to Figure 24 ...................................................................... 13

Changes to Ordering Guide .......................................................... 14

4/10—Revision 0: Initial Version

Rev. A | Page 2 of 16

ADA4320-1

SPECIFICATIONS

TA = 25°C, VS = 5 V, RL = 75 Ω, VIN (differential) = 29 dB mV sinusoidal, f = 5 MHz to 85 MHz, gain, V
output of Coilcraft PWB-4-BL transformer, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Input Resistance Balanced (differential) input 640 Ω

Unbalanced (single-ended) input 320 Ω

Input Capacitance 2.0 pF

GAIN CONTROL Current Level 3

Gain Range 57.5 59 60 dB

Maximum Gain Gain Code 60 30.5 32 dB

Minimum Gain Gain Code 01 −27 −25.5 dB

Output Step Size 0.6 1.0 1.4 dB/LSB

OUTPUT CHARACTERISTICS

Gain Flatness Referenced to 10 MHz

At Maximum Gain f = 42 MHz, Gain Code 60, Current Level 3 −0.3 dB
f = 65 MHz, Gain Code 60, Current Level 3 −0.7 dB
f = 85 MHz, Gain Code 60, Current Level 3 −1.1 dB

At Minimum Gain f = 42 MHz, Gain Code 01, Current Level 0 −0.4 dB
f = 65 MHz, Gain Code 01, Current Level 0 −0.8 dB
f = 85 MHz, Gain Code 01, Current Level 0 −1.8 dB

1 dB Compression Point (P
Output Noise in 160 kHz Bandwidth f = 10 MHz, 294 Ω resistor across VIN+ and VIN− pins

At Maximum Gain Gain Code 60, Current Level 3, TXEN = high (1) −19 −20 dB mV

Gain Code 60, Current Level 0, TXEN = high (1) −20 −21 dB mV

At Minimum Gain Gain Code 01, Current Level 3, TXEN = high (1) −59 −60 dB mV

Gain Code 01, Current Level 0, TXEN = high (1) −60 −61 dB mV

Transmit Disabled TXEN = low (0) −68 −70 dB mV

Output Impedance (Measured at

Transformer Output)

Output Return Loss (Measured at

Transformer Output)

OVERALL PERFORMANCE

Adjacent Channel Power Ratio (ACPR)

Single QPSK Channel

4x QAM64 Channels

Output Third-Order Intercept Point (OIP3) f1 = 84 MHz, f2 = 85 MHz, Gain Code 60, Current Level 3 93 dB mV
f
Input-to-Output Isolation f = 85 MHz, Gain Code 60, TXEN = Low (0) 107 dB

) f = 10 MHz, Gain Code 60, Current Level 3, output referred 70 dB mV

1dB

TXEN = high (1) or TXEN = low (0) or SLEEP = low (0)

f = 85 MHz

= high (1), TXEN = high (1)

SLEEP

= high (1), TXEN = low (0)

SLEEP

= low (0)

SLEEP

f = 5 MHz to 85 MHz, output level = 61 dB mV,
Gain Code 60, Current Level 3, channel width = 6.4 MHz,
adjacent channel width = 6.4 MHz

f = 5 MHz to 85 MHz, output level = 53 dB mV/channel,
Gain Code 60, Current Level 3, channel width = 1.6 MHz,
adjacent channel width = 1.6 MHz

= 84 MHz, f2 = 85 MHz, Gain Code 60, Current Level 0 87 dB mV

1

(single-ended) measured at

OUT

75 Ω

12 dB
11 dB
10 dB

−66 dBc

−63 dBc

Rev. A | Page 3 of 16

ADA4320-1

Parameter Conditions Min Typ Max Unit

POWER CONTROL

Transmit Enable Settling Time TXEN = 0 to 1, Gain Code 60, no input signal 5.5 µs
Transmit Disable Settling Time TXEN = 1 to 0, Gain Code 60, no input signal 7 µs
Output Switching Transients Gain Code 60 20 mV p-p
Gain Code 01 2 mV p-p

POWER SUPPLY

Operating Range 4.75 5.00 5.25 V
Quiescent Current

At Maximum Gain Gain Code 60, Current Level 3 260 300 mA
Gain Code 60, Current Level 2 235 270 mA
Gain Code 60, Current Level 1 210 250 mA
Gain Code 60, Current Level 0 180 210 mA

At Minimum Gain Gain Code 01, Current Level 3 77 100 mA
Gain Code 01, Current Level 2 73 95 mA
Gain Code 01, Current Level 1 70 90 mA
Gain Code 01, Current Level 0 65 80 mA
TXEN = 0, all gain codes, all current levels 12 15 mA

OPERATING TEMPERATURE RANGE −40 +85 °C

= 0 (power-down)

SLEEP

12 80 µA

LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC)

DATEN

, CLK, SDATA, TXEN,

Table 2.

Parameter Min Typ Max Unit

Logic 1 Voltage 2.0 VS V
Logic 0 Voltage 0 0.8 V
Digital Input Leakage Current (Both Logic Levels, All Digital Pins) −5 +5 µA

SLEEP

, VS = 5 V; full temperature range.

Rev. A | Page 4 of 16

ADA4320-1

A

TIMING REQUIREMENTS

Full temperature range, VCC = 5 V, tR = tF = 4 ns, f

Table 3.

Parameter Min Typ Max Unit

Clock Pulse Width (tWH) 16 ns

Clock Period (tC) 32 ns

Setup Time SDATA vs. Clock (tDS) 5 ns

Setup Time DATEN vs. Clock (tES)

Hold Time SDATA vs. Clock (tDH) 5 ns

Hold Time DATEN vs. Clock (tEH)

Input 10% to 90% Rise and Fall Times, SDATA, DATEN, Clock

t

DS

SDATA

CLK

DATEN

= 8 MHz, unless otherwise noted.

CLK

VALID DATA- WORD G 1

MSB...LSB

t

C

t

WH

t

ES

8 CLOCK CYCLES

t

EH

GAIN TRANSFER (G1) GAIN TRANSFER (G2)

VALID DATA-WORD G2

16 ns

3 ns
10 ns

TXEN

NALOG

OUTPUT

SIGNAL AMPL ITUDE (p-p)

08707-002

Figure 2. Serial Interface Timing

VALID DATA BIT

SDATA MSB MSB – 1 MSB – 2

CLK

t

DS

Figure 3. SDATA Timing

t

DH

08707-003

Rev. A | Page 5 of 16