Datasheet ADA4304-2 Datasheet (ANALOG DEVICES)

1:2 Single-Ended, Low Cost,

V5V

FEATURES

Ideal for CATV and terrestrial applications
Excellent frequency response

1.6 GHz, −3 dB bandwidth

1 dB flatness to 1.0 GHz
Low noise figure: 4.0 dB
Low distortion

Composite second order (CSO): −62 dBc

Composite triple beat (CTB): −72 dBc

1 dB compression point of 8.25 dBm

2.8 dB of gain per output channel
25 dB output-to-output isolation, 50 MHz to 1000 MHz
75 Ω input and outputs
Integrated output resistors
Small package size: 16-lead, 3 mm × 3 mm LFCSP

APPLICATIONS

Set-top boxes
Residential gateways
CATV distribution systems
Splitter modules
Digital cable ready (DCR) TVs

Active RF Splitter

ADA4304-2

FUNCTIONAL BLOCK DIAGRAM

5

0.1µF0.1µF

1µH

VCC

VIN

0.01µF

IL

ADA4304-2

GND

Figure 1.

VOUT1

0.01µF

VOUT2

0.01µF

06539-001

GENERAL DESCRIPTION

The ADA4304-2 is a 75 Ω active splitter for use in applications
where a lossless signal split is required. Typical applications
include multituner digital set-top boxes, cable splitter modules,
multituner/digital cable ready (DCR) televisions, and home
gateways where traditional solutions require discrete passive
splitter modules with separate fixed gain amplifiers.

The ADA4304-2 is fabricated using Analog Devices, Inc.
proprietary silicon-germanium (SiGe), complementary bipolar
process, enabling it to achieve very low levels of distortion with
a noise figure of 4 dB. The part provides a low cost alternative
that simplifies designs and improves system performance by
integrating a signal splitter element and a gain block into a single
IC. The ADA4304-2 is available in a 16-lead LFCSP and operates in
the extended industrial temperature range of −40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

4

3

2

1

0

–1

–2

–3

GAIN (dB)

–4

–5

–6

–7

–8

10050 1000 4000

Figure 2. Gain (S

TA = +85°C

T

= +25°C

A

FREQUENCY (MHz)

, S31) vs. Frequency

21

TA = –40°C

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

06539-011

ADA4304-2

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

Thermal Resistance ...................................................................... 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

REVISION HISTORY

5/07—Revision 0: Initial Version

Typical Performance Characteristics..............................................6

Test Circuits........................................................................................8

Applications........................................................................................9

Circuit Description .......................................................................9

Evaluation Boards .........................................................................9

RF Layout Considerations............................................................9

Power Supply..................................................................................9

Outline Dimensions....................................................................... 11

Ordering Guide .......................................................................... 11

Rev. 0 | Page 2 of 12

ADA4304-2

SPECIFICATIONS

VCC = 5 V, 75 Ω system, TA = 25°C, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Bandwidth (−3 dB) 1600 MHz

Specified Frequency Range 54 865 MHz

Gain (S21, S31) f = 100 MHz; see Figure 17 and Figure 18 2.8 dB

1 dB Gain Flatness 1000 MHz
NOISE/DISTORTION PERFORMANCE

Noise Figure1 @ 54 MHz 4.0 dB

@ 550 MHz 4.5 dB

@ 865 MHz 4.6 dB

Output IP3 f1 = 97.25 MHz, f2 = 103.25 MHz 26 dBm

Output IP2 f1 = 97.25 MHz, f2 = 103.25 MHz 44.5 dBm

Composite Triple Beat (CTB) 135 channels, 15 dBmV/channel, f = 865 MHz −72 dBc

Composite Second Order (CSO) 135 channels, 15 dBmV/channel, f = 865 MHz −62 dBc

Cross Modulation (CXM)

INPUT CHARACTERISTICS See Figure 17, Figure 18, and Figure 19

Input Return Loss (S11) @ 54 MHz −15 −11 dB

@ 550 MHz −35.5 −22 dB

@ 865 MHz −13.3 −8 dB

Output-to-Input Isolation (S12, S13) Either output, 54 MHz to 865 MHz

@ 54 MHz −32 −30 dB

@ 550 MHz −32 −29 dB

@ 865 MHz −33 −31 dB
OUTPUT CHARACTERISTICS See Figure 17, Figure 18, and Figure 19

Output Return Loss (S22, S33) Either output, 54 MHz to 865 MHz

@ 54 MHz −26.7 −21 dB

@ 550 MHz −22 −15 dB

@ 865 MHz −20 −12 dB

Output-to-Output Isolation (S23, S32) Either output, 54 MHz to 865 MHz dB

@ 54 MHz −26.7 dB

@ 550 MHz −25.1 dB

@ 865 MHz −25 dB

1 dB Compression (P
POWER SUPPLY

Nominal Supply Voltage 4.75 5.0 5.25 V

Quiescent Supply Current 88 105 mA

1

Characterized with 50 Ω noise figure analyzer.

) Output referred, f = 100 MHz 8.25 dBm

1dB

135 channels, 15 dBmV/channel, 100% modulation
@ 15.75 kHz, f = 865 MHz

−69 dBc

Rev. 0 | Page 3 of 12

ADA4304-2

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage 5.5 V
Power Dissipation See Figure 3
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C

Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the device (including exposed pad)
soldered to a high thermal conductivity 2s2p circuit board,
as described in EIA/JESD 51-7.

Table 3. Thermal Resistance

Package Type θJA Unit

16-Lead LFCSP (Exposed Pad) 98 °C/W

Maximum Power Dissipation

The maximum safe power dissipation in the ADA4304-2
package is limited by the associated rise in junction
temperature (T
which is the glass transition temperature, the plastic changes
its properties. Even temporarily exceeding this temperature
limit can change the stresses that the package exerts on the
die, permanently shifting the parametric performance of
the ADA4304-2. Exceeding a junction temperature of 150°C
for an extended period can result in changes in the silicon
devices, potentially causing failure.

) on the die. At approximately 150°C,

J

The power dissipated in the package (P
the quiescent power dissipation; the supply voltage (V
the quiescent current (I

). In Tab le 1 , the maximum power

S

dissipation of the ADA4304-2 can be calculated as

P

= 5.25 V × 105 mA = 551 mW

D (MAX)

Airflow increases heat dissipation, effectively reducing θ
In addition, more metal directly in contact with the package
leads/exposed pad from metal traces, through-holes, ground,
and power planes reduces the θ

JA

Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 16-lead LFCSP
(98°C/W) on a JEDEC standard 4-layer board.

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

MAXIMUM POWER DISSIPATION (W)

0.2

0

10 20 30 40 50 60 70 80 90

0 100

AMBIENT TEMPERATURE (°C)

Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

ESD CAUTION

) is essentially equal to

D

.

) times

S

.

JA

06539-004

Rev. 0 | Page 4 of 12

ADA4304-2

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NC

IL

VCC

VCC

13

14

16

15

PIN 1
INDICATOR

1VCC

ADA4304-2

2VCC

TOP VIEW

3GND

(Not to Scale)

4VIN

5

6

ND

GND

NC = NO CONNECT

G

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1, 2, 15, 16 VCC Supply Pin
3, 5 to 7, 9, 11 GND Ground
4 VIN Input
8, 13 NC No Connection
10 VOUT2 Output 2
12 VOUT1 Output 1
14 IL Bias Pin

12 VOUT1

11 GN D

10 VOUT2

9GND

8

7

NC

GND

06539-002

Rev. 0 | Page 5 of 12

ADA4304-2

–

–

TYPICAL PERFORMANCE CHARACTERISTICS

VCC = 5 V, 75 Ω system, TA = 25°C, unless otherwise noted.

54

–56

–58

CSO (dBc)

–60

–62

–64

–66

–68

–70

–72

–74

T

= +85°C

A

TA= –40°C

10050 1000

FREQUENCY (MHz )

Figure 5. Composite Second Order (CSO) vs. Frequency

–

60

–

63

–

66

–

69

–

CTB (dBc)

72

–

75

–

78

–

81

–

84

–

87

–

90

TA = +85°C

T

= –40°C

A

10050 1000

FREQUENCY (MHz )

TA= +25°C

Figure 6. Composite Triple Beat (CTB) vs. Frequency

60

–

63

–

66

–

69

–

72

–

75

CXM (dBc)

–

78

–

81

–

84

–

87

–

90

TA = +85°C

T

= –40°C

A

10050 1000

FREQUENCY (MHz )

TA= +25°C

Figure 7. Cross Modulation (CXM) vs. Frequency

TA= +25°C

06539-005

06539-007

06539-006

NOISE FI GURE (dB)

OUTPUT IP2 (dBm)

OUTPUT I P3 (dBm)

10

50 Ω SYSTEM

8

6

4

2

0

60

55

50

45

40

35

30

25

20

40

35

30

25

20

15

10

5

0

TA = +85°C

10050 1000

FREQUENCY (MHz)

TA = +25°C

TA = –40°C

Figure 8. Noise Figure vs. Frequency

10050 1000

FREQUENCY (M Hz)

Figure 9. Output IP2 vs. Frequency

10050 1000

FREQUENCY (MHz)

Figure 10. Output IP3 vs. Frequency

06539-008

6539-009

6539-010

Rev. 0 | Page 6 of 12

ADA4304-2

–

4

3

2

1

0

–1

–2

–3

GAIN (dB)

–4

–5

–6

–7

–8

10050 1000 4000

TA = +85°C

Figure 11. Gain (S

30

–31

–32

–33

–34

–35

–36

ISOLATION (dB)

–37

–38

–39

–40

10050 1000 4000

Figure 12. Output-to-Input Isolation (S

0

–5

–10

–15

–20

–25

ISOLATION (dB)

–30

–35

–40

–45

10050 1000 4000

`Figure 13. Output-to-Output Isolation (S

T

= +25°C

A

FREQUENCY (MHz)

, S31) vs. Frequency

21

FREQUENCY (MHz )

FREQUENCY (M Hz)

TA = –40°C

, S13) vs. Frequency

12

, S32) vs. Frequency

23

06539-011

6539-012

06539-013

0

–5

–10

–15

–20

–25

–30

INPUT RETURN LOSS (dB)

–35

–40

10050 1000

FREQUENCY (M Hz)

Figure 14. Input Return Loss (S

) vs. Frequency

11

0

–5

–10

–15

–20

–25

–30

OUTPUT RET URN LOSS (d B)

–35

–40

Figure 15. Output Return Loss (S

10050 1000

FREQUENCY (M Hz)

, S33) vs. Frequency

22

95

90

85

80

75

QUIESCENT SUPPLY CURRENT ( mA)

70

–60 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100

TEMPERATURE ( °C)

Figure 16. Quiescent Supply Current vs. Temperature

6539-014

06539-015

06539-016

Rev. 0 | Page 7 of 12

ADA4304-2

TEST CIRCUITS

RF NETWORK ANAL YZER

75Ω S-PARAMETER

TEST SET

VOUT1

PORT 2

VIN

4

PORT 1

Figure 17. Test Circuit for S

RF NETWORK ANAL YZER

12

DUT

10

VOUT2

PORT 3

, S12, S21, S22 Measurements

11

75Ω

06539-017

75Ω S-PARAMETER

TEST SET

VOUT1

PORT 2

VIN

PORT 1

DUT

4

Figure 18. Test Circuit for S

12

10

VOUT2

PORT 3

, S31, S33 Measurements

13

75Ω

06539-018

RF NETWORK ANAL YZER

75Ω S-PARAMETER

TEST SET

VOUT1

PORT 2

VIN

4

PORT 1

75Ω

Figure 19. Test Circuit for S

12

DUT

10

23

VOUT2

PORT 3

, S32 Measurements

06539-019

Rev. 0 | Page 8 of 12

ADA4304-2

V

APPLICATIONS

The ADA4304-2 active splitter is primarily intended for use in
the downstream path of television set-top boxes (STBs) that
contain multiple tuners. It is typically located directly after the
diplexer in a bidirectional CATV customer premise unit. The
ADA4304-2 provides a single-ended input and two single­ended outputs that allow the delivery of the RF signal to two
different signal paths. These paths can include, but are not
limited to, a main picture tuner, the picture-in-picture (PIP)
tuner, an out-of-band (OOB) tuner, a digital video recorder
(DVR), and a cable modem (CM).

The ADA4304-2 exhibits composite second order (CSO) and
composite triple beat (CTB) products that are −62 dBc and

−72 dBc, respectively. The use of the SiGe bipolar process also
allows the ADA4304-2 to achieve a noise figure (NF) of 4 dB.

CIRCUIT DESCRIPTION

The ADA4304-2 consists of a low noise buffer amplifier followed
by a resistive power divider. This arrangement provides 2.8 dB
of gain relative to the RF signal present at the input of the device.
The input and each output must be properly matched to a 75 Ω
environment for distortion and noise performance to match the
data sheet specifications. AC coupling capacitors of 0.01 μF are
recommended for the input and outputs.

A 1 μH RF choke (Coilcraft chip inductor 0805LS-102X) is
required to correctly bias internal nodes of the ADA4304-2. It
should be connected between the 5 V supply and the IL pin
(Pin 14). The choke should be placed as close as possible to
the ADA4304-2 to minimize parasitic capacitance on the
IL pin, which is critical for achieving the specified bandwidth
and flatness.

GND

CC

EVALUATION BOARDS

The ADA4304-2 evaluation board allows designers to assess the
performance of the parts in their particular application. The
board includes 75 Ω coaxial connectors and 75 Ω controlled­impedance signal traces that carry the input and output signals.
Power (5 V) is applied to the red VCC loop connector, and
ground is connected to the black GND loop connector.

Figure 20 is
a schematic of the ADA4304-2 evaluation board. On the
ADA4304-2 evaluation board, connectors VO1 and VO4 are
not populated.

RF LAYOUT CONSIDERATIONS

Appropriate impedance matching techniques are mandatory
when designing circuit boards for the ADA4304-2. Improper
characteristic impedances on traces can cause reflections that
can lead to poor linearity. The characteristic impedance of the
signal trace to the input and from each output should be 75 Ω.
Any ground metal on the top surface near signal lines should be
stitched with vias to the internal ground plane, as shown in
Figure 21.

POWER SUPPLY

The 5 V supply should be applied to each of the VCC pins and
RF choke via a low impedance power bus. The power bus should
be decoupled to ground using a 10 μF tantalum capacitor and a

0.1 μF ceramic chip capacitor located close to the ADA4304-2. In
addition, the VCC pins should be decoupled to ground with a

0.1 μF ceramic chip capacitor located as close to each of the pins
as possible.

NC

GND

GND

12

11

10

9

C1

0.1µF

C3

0.01μF

C4

0.01μF

VO2

VO3

06539-003

0.1µF

VIN

NC = NO CONNECT

C2

0.01μF

+

C5

10µF

C8

1

VCC

2

VCC

ADA4304-2

3

GND

4

VIN

5

Figure 20. Evaluation Board Schematic

L1

1.0μH

15

14IL13

VCC16VCC

VOUT1

VOUT2

GND6GND7GND8NC

Rev. 0 | Page 9 of 12

ADA4304-2

Figure 21. ADA4304-2 Evaluation Board

06539-020

Figure 22. Evaluation Board Component Layout

06539-021

Rev. 0 | Page 10 of 12

ADA4304-2

R

OUTLINE DIMENSIONS

0.50

0.40

PIN 1

INDICATO

1.00

0.85

0.80

SEATING

PLANE

12° MAX

3.00

BSC SQ

TOP

VIEW

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2

2.75

BSC SQ

0.80 MAX

0.65 TYP

0.20 REF

0.05 MAX

0.02 NOM

0.45

0.50

BSC

1.50 REF

0.60 MAX

13

12

(BOTTOM VIEW)

9

8

Figure 23. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

3 mm × 3 mm Body, Very Thin Quad

(CP-16-1)

Dimensions shown in millimeters

EXPOSED

PA D

0.30

16

1

4

5

PIN 1
INDICATOR

1.25

1.10 SQ

0.95

0.25 MIN

ORDERING GUIDE

Model Temperature Range Package Description Package Option Ordering Quantity Branding

ADA4304-2ACPZ-RL
ADA4304-2ACPZ-R7
ADA4304-2ACPZ-R2

1

Z = RoHS Compliant Part.

1

−40°C to +85°C 16-Lead LFCSP_VQ CP-16-1 5,000 H0Z

1

−40°C to +85°C 16-Lead LFCSP_VQ CP-16-1 1,500 H0Z

1

−40°C to +85°C 16-Lead LFCSP_VQ CP-16-1 250 H0Z

Rev. 0 | Page 11 of 12

ADA4304-2

NOTES

©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06539-0-5/07(0)

Rev. 0 | Page 12 of 12