Ideal for CATV applications
Excellent frequency response
1.7 GHz, −3 dB bandwidth
1 dB flatness to 1.2 GHz
Low noise figure: 4.4 dB
Low distortion
Composite second order (CSO): −62 dBc
Composite triple beat (CTB): −72 dBc
1 dB compression point of 8.5 dBm
3 dB of gain per output channel
24 dB isolation between output channels
75 Ω input and outputs
Small package size
12-lead, 3 mm × 3 mm lead frame chip scale package
APPLICATIONS
Set-top boxes
Home gateways
CATV distribution systems
Splitter modules
Digital cable ready (DCR) TVs
Active RF Splitter
ADA4303-2
FUNCTIONAL BLOCK DIAGRAM
5
0.1µF0.1µF
1µH
VCC
VIN
0.01µF
IL
VO1
ADA4303-2
VO2
GND
Figure 1.
0.01µF
0.01µF
249
249
06364-001
GENERAL DESCRIPTION
The ADA4303-2 is a 75 Ω, two-output active splitter for use
in applications where a lossless signal split is required. Typical
applications include multituner digital set-top boxes, cable
splitter modules, multituner/digital cable ready (DCR)
televisions, and home gateways where traditional solutions
require discrete passive splitter modules with separate fixed
gain amplifiers.
The ADA4303-2 is a low cost alternative that simplifies designs
and improves system performance by integrating a signal
splitter element and a gain block into a single IC. The ADA4303-2
is available in a 12-lead chip scale package (LFCSP_VQ) and
operates in the extended industrial temperature range of −40°C
to +85°C.
4
3
2
1
0
–1
–2
–3
GAIN (dB)
–4
–5
–6
–7
–8
5010040001000
FREQUENCY (MHz )
Figure 2. Gain (S21) vs. Frequency
= +25°C
T
A
TA = +85°C
= –40°C
T
A
06364-010
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Supply Voltage 5.5 V
Power Dissipation See Figure 3
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum
Rating may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions; that is, θJA is
specified for a device (including exposed pad) soldered to
the circuit board.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the
voltage between the supply pins (V
current (I
). The power dissipated due to the load drive depends
S
) times the quiescent
S
upon the particular application. The power due to load drive is
calculated by multiplying the load current by the associated
voltage drop across the device. RMS voltages and currents must
be used in these calculations.
. In
addition, more metal directly in contact with the package
leads/exposed pad from metal traces, through-holes, ground,
and power planes reduces the θ
.
JA
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 12-lead LFCSP_VQ
(99.2°C/W) on a JEDEC standard 4-layer board.
2.5
2.0
Table 3. Thermal Resistance
Package Type θJA Unit
12-Lead LFCSP_VQ (exposed pad) 99.2 °C/W
Maximum Power Dissipation
The maximum safe power dissipation in the ADA4303-2
package is limited by the associated rise in junction
temperature (T
) on the die. At approximately 150°C, which
J
is the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature
limit can change the stresses that the package exerts on the
die, permanently shifting the parametric performance of
the ADA4303-2. Exceeding a junction temperature of 150°C
for an extended period can result in changes in the silicon
devices, potentially causing failure.
1.5
1.0
0.5
MAXIMUM POWER DISSIPATIO N (W)
0
–60020406080100 120
–40 –20
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
AMBIENT TEM PERATURE (° C)
ESD CAUTION
06364-016
Rev. 0 | Page 4 of 12
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