ANALOG DEVICES ADA4303-2 Service Manual

1:2 Single-Ended, Low Cost

V5V

FEATURES

Ideal for CATV applications
Excellent frequency response

1.7 GHz, −3 dB bandwidth

1 dB flatness to 1.2 GHz
Low noise figure: 4.4 dB
Low distortion

Composite second order (CSO): −62 dBc

Composite triple beat (CTB): −72 dBc

1 dB compression point of 8.5 dBm
3 dB of gain per output channel
24 dB isolation between output channels
75 Ω input and outputs
Small package size

12-lead, 3 mm × 3 mm lead frame chip scale package

APPLICATIONS

Set-top boxes
Home gateways
CATV distribution systems
Splitter modules
Digital cable ready (DCR) TVs

Active RF Splitter

ADA4303-2

FUNCTIONAL BLOCK DIAGRAM

5

0.1µF0.1µF

1µH

VCC

VIN

0.01µF

IL

VO1

ADA4303-2

VO2

GND

Figure 1.

0.01µF

0.01µF

249

249

06364-001

GENERAL DESCRIPTION

The ADA4303-2 is a 75 Ω, two-output active splitter for use
in applications where a lossless signal split is required. Typical
applications include multituner digital set-top boxes, cable
splitter modules, multituner/digital cable ready (DCR)
televisions, and home gateways where traditional solutions
require discrete passive splitter modules with separate fixed
gain amplifiers.

The ADA4303-2 is a low cost alternative that simplifies designs
and improves system performance by integrating a signal
splitter element and a gain block into a single IC. The ADA4303-2
is available in a 12-lead chip scale package (LFCSP_VQ) and
operates in the extended industrial temperature range of −40°C
to +85°C.

4

3

2

1

0

–1

–2

–3

GAIN (dB)

–4

–5

–6

–7

–8

50 100 40001000

FREQUENCY (MHz )

Figure 2. Gain (S21) vs. Frequency

= +25°C

T

A

TA = +85°C

= –40°C

T

A

06364-010

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADA4303-2

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

Thermal Resistance ...................................................................... 4

ESD Caution.................................................................................. 4

REVISION HISTORY

10/06—Revision 0: Initial Version

Pin Configuration and Function Descriptions..............................5

Typical Performance Characteristics..............................................6

Applications........................................................................................8

Circuit Description .......................................................................8

Evaluation Board ...........................................................................8

RF Layout Considerations............................................................8

Power Supply..................................................................................8

Outline Dimensions..........................................................................9

Ordering Guide .............................................................................9

Rev. 0 | Page 2 of 12

ADA4303-2

SPECIFICATIONS

VCC = 5 V, RIN = RL = 75 Ω, TA = 25°C, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Bandwidth (−3 dB) 1700 MHz

Specified Frequency Range 54 865 MHz

Gain (S21) f = 100 MHz 2.0 3.0 4.0 dB

1 dB Gain Flatness 1200 MHz
NOISE/DISTORTION PERFORMANCE

Noise Figure @ 54 MHz 4.0 4.3 dB

@ 550 MHz 4.3 4.9 dB

@ 865 MHz 4.4 5.1 dB

Output IP3 f1 = 97.25 MHz, f2 = 103.25 MHz 26.5 dBm

Output IP2 f1 = 97.25 MHz, f2 = 103.25 MHz 44.0 dBm

Composite Triple Beat (CTB) 135 Channels, 15 dBmV/Channel, f = 865 MHz −72 −66 dBc

Composite Second-Order (CSO) 135 Channels, 15 dBmV/Channel, f = 865 MHz −62 −60 dBc

Cross Modulation (CXM)

INPUT CHARACTERISTICS

Input Return Loss (S11) Referenced to 75 Ω

@ 54 MHz −15.0 −11.5 dB

@ 550 MHz −19.5 −14.0 dB

@ 865 MHz −12.0 −7.5 dB

Output-to-Input Isolation (S12) Any output, 54 MHz to 865 MHz

@ 54 MHz −31.8 −29.0 dB

@ 550 MHz −32.0 −29.5 dB

@ 865 MHz −32.5 −30.0 dB
OUTPUT CHARACTERISTICS

Output Return Loss (S22) Referenced to 75 Ω

@ 54 MHz −31.2 −23.0 dB

@ 550 MHz −19.4 −14.0 dB

@ 865 MHz −15.5 −11.0 dB

Output-to-Output Isolation Between any two outputs, 54 MHz to 865 MHz

@ 54 MHz −24.6 dB

@ 550 MHz −24.0 dB

@ 865 MHz −24.5 dB

1 dB Compression Output referred, f = 100 MHz 8.5 dBm
POWER SUPPLY

Nominal Supply Voltage 4.5 5.0 5.5 V

Quiescent Supply Current 78 90 mA

135 Channels, 15 dBmV/Channel, 100% modulation
@ 15.75 kHz, f = 865 MHz

−68 −65 dBc

Rev. 0 | Page 3 of 12

ADA4303-2

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage 5.5 V
Power Dissipation See Figure 3
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C

Stresses above those listed under Absolute Maximum
Rating may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions; that is, θJA is
specified for a device (including exposed pad) soldered to
the circuit board.

The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the
voltage between the supply pins (V
current (I

). The power dissipated due to the load drive depends

S

) times the quiescent

S

upon the particular application. The power due to load drive is
calculated by multiplying the load current by the associated
voltage drop across the device. RMS voltages and currents must
be used in these calculations.

Airflow increases heat dissipation, effectively reducing θ

JA

. In
addition, more metal directly in contact with the package
leads/exposed pad from metal traces, through-holes, ground,
and power planes reduces the θ

.

JA

Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 12-lead LFCSP_VQ
(99.2°C/W) on a JEDEC standard 4-layer board.

2.5

2.0

Table 3. Thermal Resistance

Package Type θJA Unit

12-Lead LFCSP_VQ (exposed pad) 99.2 °C/W

Maximum Power Dissipation

The maximum safe power dissipation in the ADA4303-2
package is limited by the associated rise in junction
temperature (T

) on the die. At approximately 150°C, which

J

is the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature
limit can change the stresses that the package exerts on the
die, permanently shifting the parametric performance of
the ADA4303-2. Exceeding a junction temperature of 150°C
for an extended period can result in changes in the silicon
devices, potentially causing failure.

1.5

1.0

0.5

MAXIMUM POWER DISSIPATIO N (W)

0

–60 0 20 40 60 80 100 120

–40 –20

Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

AMBIENT TEM PERATURE (° C)

ESD CAUTION

06364-016

Rev. 0 | Page 4 of 12

ADA4303-2

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VCC

NC

IL
11

10

12

PIN 1

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 VCC Supply Pin
2 VIN Input
3 GND Ground
4 GND Ground
5 GND Ground
6 NC No Connection
7 GND Ground
8 VO2 Output 2
9 VO1 Output 1
10 NC No Connection
11 IL Bias Pin
12 VCC Supply Pin

INDICATOR

1VCC
2VIN

ADA4303-2

3GND

TOP VIEW

4

5

GND

GND

NC = NO CONNECT

Figure 4. Pin Configuration

9VO1
8VO2
7GND

6
NC

06364-002

Rev. 0 | Page 5 of 12

ADA4303-2

–

–

–

TYPICAL PERFORMANCE CHARACTERISTICS

50

–53

–56

–59

–62

–65

CSO (d Bc)

–68

–71

–74

–77

–80

50 100 1000

TA = +25°C

TA = +85°C

= –40°C

T

A

FREQUENCY (MHz )

Figure 5. Composite Second-Order (CSO) vs. Frequency

60

–63

–66

–69

–72

–75

CTB (dBc)

–78

–81

–84

–87

–90

50 100 1000

TA = +85°C

TA = +25°C

FREQUENCY (MHz )

TA = –40°C

Figure 6. Composite Triple Beat (CTB) vs. Frequency

60

–63

–66

–69

–72

–75

CXM (dBc)

–78

–81

–84

–87

–90

50 100 1000

TA = +85°C

TA = +25°C

FREQUENCY (MHz )

= –40°C

T

A

Figure 7. Cross Modulation (CXM) vs. Frequency

06364-004

06364-005

06364-006

10

8

6

4

NOISE FI GURE (dB)

2

0

50 100 1000

TA = +85°C

TA = +25°C

FREQUENCY (MHz )

T

A

= –40°C

Figure 8. Noise Figure vs. Frequency

60

55

50

45

40

35

OUTPUT I P2 (dBm)

30

25

20

50 100 1000

FREQUENCY (MHz )

Figure 9. Output IP2 vs. Frequency

40

35

30

25

20

15

OUTPUT I P3 (dBm)

10

5

0

50 100 1000

FREQUENCY (MHz )

Figure 10. Output IP3 vs. Frequency

06364-007

06364-008

06364-009

Rev. 0 | Page 6 of 12

ADA4303-2

–

4

3

2

1

0

–1

–2

–3

GAIN (dB)

–4

–5

–6

–7

–8

50 100 40001000

FREQUENCY (MHz )

T

= +25°C

A

TA = +85°C

T

= –40°C

A

06364-010

Figure 11. Gain (S21) vs. Frequency

30

–31

–32

–33

–34

–35

–36

ISOLATION (dB)

–37

–38

–39

–40

50 100 40001000

FREQUENCY (MHz )

06364-011

Figure 12. Output-to-Input Isolation (S12) vs. Frequency

0

–5

–10

–15

–20

–25

ISOLATION (dB)

–30

–35

–40

–45

50 100 40001000

FREQUENCY (MHz )

06364-012

Figure 13. Output-to-Output Isolation vs. Frequency

0

–5

–10

–15

–20

INPUT RETURN LOSS (dB)

–25

–30

50 100 1000

FREQUENCY (MHz )

Figure 14. Input Return Loss (S11) vs. Frequency

0

–5

–10

–15

–20

–25

–30

OUTPUT RET URN LOSS (d B)

–35

–40

50 100 1000

FREQUENCY (MHz )

Figure 15. Output Return Loss (S22) vs. Frequency

90

85

80

75

70

QUIESCENT S UPPLY CURRENT (mA)

65

–60 –50 90 100

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80

TEMPERATURE ( °C)

Figure 16. Quiescent Supply Current vs. Temperature

06364-013

06364-014

06364-015

Rev. 0 | Page 7 of 12

ADA4303-2

APPLICATIONS

The ADA4303-2 active splitter is primarily intended for use
in the downstream path of television set-top boxes (STBs) that
contain multiple tuners. It is typically located directly after the
diplexer in a CATV customer premise unit. The ADA4303-2
provides a single-ended input and two single-ended outputs
that allow the delivery of the RF signal to two different signal
paths. These paths can include, but are not limited to, a main
picture tuner, a picture-in-picture (PIP) tuner, an out-of-band
(OOB) tuner, a digital video recorder (DVR), and a cable
modem (CM).

The ADA4303-2 exhibits composite second-order (CSO) and
composite triple beat (CTB) products that are −62 dBc and

−72 dBc, respectively. The use of the SiGe process also allows
the ADA4303-2 to achieve a noise figure (NF) of less than 4.5 dB.

CIRCUIT DESCRIPTION

The ADA4303-2 consists of a low noise buffer amplifier followed
by a resistive power divider. This arrangement provides 3 dB of
gain relative to the RF signal present at the input of the device.
The input and each output must be properly matched to a 75 Ω
environment for distortion and noise performance to match the
data sheet specifications. In addition, to achieve the specified gain,
a 1% 249 Ω resistor should be installed to ground on each output.
AC coupling capacitors of 0.01 μF are recommended for the
input and outputs.

A 1 μH RF choke (Coilcraft chip inductor 0805LS-102X) is
required to correctly bias internal nodes of the ADA4303-2.
It should be connected between the 5 V supply and IL (Pin 11).

EVALUATION BOARD

The ADA4303-2 evaluation board allows designers to assess the
performance of the part in their particular applications. The board
includes 75 Ω coaxial connectors and 75 Ω controlled-impedance
signal traces that carry the input and output signals. Power (5 V)
is applied to the red VCC loop connector, and ground is connected
to the black GND loop connector.

The board has two 249 Ω resistors between each output and
ground that set the gain of the overall circuit to 3 dB and
improve output-to-output isolation. A schematic of the
ADA4303-2 evaluation board is shown in

Figure 17.

RF LAYOUT CONSIDERATIONS

Appropriate impedance matching techniques are mandatory
when designing a circuit board for the ADA4303-2. Improper
characteristic impedances on traces can cause reflections that
can lead to poor linearity. The characteristic impedance of the
signal trace from each output should be 75 Ω.

POWER SUPPLY

The 5 V supply should be applied to each of the VCC pins and
RF choke via a low impedance power bus. The power bus should
be decoupled to ground using a 10 μF tantalum capacitor and
a 0.1 μF ceramic chip capacitor located close to the ADA4303-2.
In addition, the VCC pins should be decoupled to ground with
a 0.1 μF ceramic chip capacitor located as close to each of the
pins as possible.

VCC

GND

C1

C5

10µF

C6

0.1µF

J1

NC = NO CONNECT

C2

0.01F

+

1

VCC

2

VIN

3

GND

Figure 17. ADA4303-2 Evaluation Board Schematic

0.1µF

IL

VCC

ADA4303-2

GND

GND

45

L1

1.0H

101112

NC

9

VO1

8

VO2

7

GND

NC

6

C3

0.01F

C4

0.01F

249

249

J2

J3

06364-003

Rev. 0 | Page 8 of 12

ADA4303-2

OUTLINE DIMENSIONS

0.75

0.55

0.35

11

12

1

2

3

5

4

PIN 1
INDICATOR

*

1.45

1.30 SQ

1.15

0.25 MIN

PIN 1

INDICATOR

1.00

0.85

0.80

SEATING

PLANE

12° MAX

3.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

*
EXCEPT FO R EXPOSED PAD DI MENSION.

2.75

BSC SQ

EXPOSED PAD

(BOTTOM VIEW )

0.05 MAX

0.02 NOM

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1

0.45

0.60 MAX

10

9

8

7

6

0.50

BSC

COPLANARITY

0.08

Figure 18. 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

3 mm × 3 mm Body, Very Thin Quad

(CP-12-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Ordering Quantity Branding

ADA4303-2ACPZ-RL
ADA4303-2ACPZ-R7
ADA4303-2ACPZ-R2
ADA4303-2ACPZ-EB

1

Z = Pb-free part.

1

−40°C to +85°C 12-Lead LFCSP_VQ CP-12-1 5000 H0V

1

−40°C to +85°C 12-Lead LFCSP_VQ CP-12-1 1500 H0V

1

−40°C to +85°C 12-Lead LFCSP_VQ CP-12-1 250 H0V

1

Evaluation Board

Rev. 0 | Page 9 of 12

ADA4303-2

NOTES

Rev. 0 | Page 10 of 12

ADA4303-2

NOTES

Rev. 0 | Page 11 of 12

ADA4303-2

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06364-0-10/06(0)

Rev. 0 | Page 12 of 12