ANALOG DEVICES ADA4062-4 Service Manual

A

2

Low Power JFET-Input Op Amps

FEATURES

Low input bias current: 50 pA maximum
Offset voltage

1.5 mV maximum for B grade (ADA4062-2 SOIC package)

2.5 mV maximum for A grade
Offset voltage drift: 5 μV/°C typical
Slew rate: 3.3 V/μs typical
CMRR: 90 dB typical
Low supply current: 165 μA typical
High input impedance
Unity-gain stable
±5 V to ±15 V dual-supply operation
Packaging

8-lead SOIC, 8-lead MSOP, 10-lead LFCSP, 14-lead TSSOP, and

16-lead LFCSP packages

APPLICATIONS

Power controls and monitoring
Active filters
Industrial/process controls
Body probe electronics
Data acquisition
Integrators
Input buffering

GENERAL DESCRIPTION

The ADA4062-2 and ADA4062-4 are dual and quad JFET-input
amplifiers with industry-leading performance. They offer lower
power, offset voltage, drift, and ultralow bias current. The
ADA4062-2 B grade (SOIC package) features a typical low offset
voltage of 0.5 mV, an offset drift of 5 μV/°C, and a bias current
of 2 pA.

The ADA4062 family is ideal for various applications, including
process controls, industrial and instrumentation equipment,
active filtering, data conversion, buffering, and power control
and monitoring. With a low supply current of 165 μA per
amplifier, they are well suited for lower power applications.

The ADA4062 family is also specified for the extended industrial
temperature range of −40°C to +125°C. The ADA4062-2 is
available in lead-free, 8-lead SOIC, 8-lead MSOP, and 10-lead
LFCSP (1.6 mm × 1.3 mm × 0.55 mm) packages, while the
ADA4062-4 is available in lead-free, 14-lead TSSOP and
16-lead LFCSP packages.

ADA4062-2/ADA4062-4

PIN CONFIGURATIONS

OUT A

1

ADA4062-2

–IN A

2

V–

TOP VIEW

3

(Not to Scale)

4

+IN A

Figure 1. 8-Lead Narrow-Body SOIC and 8-Lead MSOP

OUT
1

N A

–I

2

ADA4062-2

3

+IN A

C = NO CONNECT

N

TOP VIE W

(Not to Scal e)

4

V–

Figure 2. 10-Lead LFCSP

1

OUT A

2

–IN A

3

+IN A

+IN B

–IN B

OUT B

V+

ADA4062-4

TOP VIEW

4

(Not to Scale)

5

6

7

Figure 3. 14-Lead TSSOP

NC

OUT A

16

15

1

–IN A

V+

ADA4062-4

2

3

(Not to Scale)

4

TOP VIEW

5

6

–IN B

OUT B

+IN A

+IN B

NOTES

1. NC = NO CONNECT.
. IT IS RECOMMENDED TO CONNECT THE EXPOSED PAD T O V–.

Figure 4. 16-Lead LFCSP

Table 1. Low Power Op Amps

Precision
CMOS

Precision
High Bandwidth

Single AD8663 AD8641
Dual AD8667 AD8642 AD8682
Quad AD8669 AD8643 AD8684

OUT D

14

7

OUT C

V+

8

OUT B

7

–IN B

6

5

+IN B

07670-001

V+

NC

9

10

OUT B

8

7

–IN B

6

5

NC

+IN B

14

OUT D

13

–IN D

12

+IN D

11

V–

10

+IN C

9

–IN C

8

OUT C

NC

13

12

11

10

9

8

–IN C

–IN D

+IN D

V–

+IN C

07670-065

07670-064

07670-068

High
Bandwidth

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008–2010 Analog Devices, Inc. All rights reserved.

ADA4062-2/ADA4062-4

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Pin Configurations ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics ............................................................. 3

Absolute Maximum Ratings ............................................................ 5

Thermal Resistance ...................................................................... 5

Power Sequencing ........................................................................ 5

REVISION HISTORY

2/10—Rev. A to Rev. B

Added 16-Lead LFCSP Package........................................ Universal

Changes to Features Section, General Description Section, and

Table 1 ................................................................................................ 1

Changes to Offset Voltage Drift Parameter, Table 2 .................... 3

Changes to Table 4 ............................................................................ 5

Changes to Typical Performance Characteristics Layout ............ 6

Added Figure 6 and Figure 9; Renumbered Sequentially ........... 6

Changes to Figure 7, Figure 8, and Figure 10 ............................... 6

Changes to Figure 25 and Figure 28 ............................................... 9

Changes to Figure 37 and Figure 40 ............................................. 11

Changes to Figure 41 to Figure 46 ................................................ 12

Changes to Figure 47 and Figure 50 ............................................. 13

Changes to Figure 53 to Figure 58 ................................................ 14

Changes to Notch Filter Section and Micropower Instrumentation

Amplifier Section ............................................................................ 15

Updated Outline Dimensions ....................................................... 18

Changes to Ordering Guide .......................................................... 20

ESD Caution...................................................................................5

Typical Performance Characteristics ..............................................6

Applications Information .............................................................. 15

Notch Filter ................................................................................. 15

High-Side Signal Conditioning ................................................ 15

Micropower Instrumentation Amplifier ................................. 15

Phase Reversal ............................................................................ 16

Schematic ......................................................................................... 17

Outline Dimensions ....................................................................... 18

Ordering Guide .......................................................................... 20

7/09—Rev. 0 to Rev. A

Added ADA4062-4 ............................................................. Universal

Added 14-Lead TSSOP Package ....................................... Universal

Added 10-Lead LFCSP Package ....................................... Universal

Changes to Features Section and Table 1 ....................................... 1

Changes to Table 2 ............................................................................. 3

Changes to Thermal Resistance Section ........................................ 5

Changes to Figure 5, Figure 6, Figure 8, and Figure 9 .................. 6

Changes to Figure 37 and Figure 40............................................. 11

Changes to Figure 41 and Figure 44............................................. 12

Changes to Figure 47, Figure 48, Figure 50, and Figure 51....... 13

Added Figure 49 and Figure 52; Renumbered Sequentially ..... 13

Changes to Figure 57 and Figure 59............................................. 15

Changes to Phase Reversal Section and Figure 61 ..................... 16

Changes to Figure 63 ...................................................................... 17

Updated Outline Dimensions ....................................................... 18

Changes to Ordering Guide .......................................................... 19

10/08—Revision 0: Initial Version

Rev. B | Page 2 of 20

ADA4062-2/ADA4062-4

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VSY = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS

B Grade (ADA4062-2, 8-Lead SOIC Only) 0.5 1.5 mV

−40°C ≤ TA ≤ +125°C 3 mV
A Grade 0.75 2.5 mV

−40°C ≤ TA ≤ +125°C 5 mV

Offset Voltage Drift ∆VOS/∆T −40°C ≤ TA ≤ +125°C 5 μV/°C
Input Bias Current IB 2 50 pA

−40°C ≤ TA ≤ +125°C 5 nA

Input Offset Current IOS 0.5 25 pA

−40°C ≤ TA ≤ +125°C 2.5 nA

Input Voltage Range −40°C ≤ TA ≤ +125°C −11.5 +15 V
Common-Mode Rejection Ratio CMRR

B Grade (ADA4062-2, 8-Lead SOIC Only) VCM = −11.5 V to +11.5 V 80 90 dB

−40°C ≤ TA ≤ +125°C 80 dB
A Grade VCM = −11.5 V to +11.5 V 73 90 dB

−40°C ≤ TA ≤ +125°C 70 dB

Large-Signal Voltage Gain AVO R

−40°C ≤ TA ≤ +125°C 72 dB

Input Resistance RIN 10 TΩ
Input Capacitance, Differential Mode C
Input Capacitance, Common Mode C

1.5 pF

INDM

4.8 pF

INCM

OUTPUT CHARACTERISTICS

Output Voltage High VOH R

−40°C ≤ TA ≤ +125°C 12.5 V

Output Voltage Low VOL R

−40°C ≤ TA ≤ +125°C −12.5 V

Short-Circuit Current ISC 20 mA
Closed-Loop Output Impedance Z

f = 1 kHz, AV = 1 1 Ω

OUT

POWER SUPPLY

Power Supply Rejection Ratio PSRR

B Grade (ADA4062-2, 8-Lead SOIC Only) VSY = ±4 V to ±18 V 80 90 dB

−40°C ≤ TA ≤ +125°C 80 dB
A Grade VSY = ±4 V to ±18 V 74 90 dB

−40°C ≤ TA ≤ +125°C 70 dB

Supply Current per Amplifier ISY I

−40°C ≤ TA ≤ +125°C 260 μA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 10 kΩ, CL = 100 pF, AV = 1 3.3 V/μs
Settling Time tS

Gain Bandwidth Product GBP RL = 10 kΩ, AV = 1 1.4 MHz
Phase Margin ΦM R
Channel Separation (ADA4062-2 Only) CS f = 1 kHz 135 dB
Channel Separation (ADA4062-4 Only) CS f = 1 kHz 130 dB

= 10 kΩ, VO = −10 V to +10 V 76 83 dB

L

= 10 kΩ to VCM 13 13.5 V

L

= 10 kΩ to VCM −13.8 −13 V

L

= 0 mA 165 220 μA

O

To 0.1%, V

= 10 kΩ, AV = 1

R

L

= 10 kΩ, AV = 1 78 Degrees

L

= 10 V step, CL = 100 pF,

IN

3.5 μs

Rev. B | Page 3 of 20

ADA4062-2/ADA4062-4

Parameter Symbol Conditions Min Typ Max Unit

NOISE PERFORMANCE

Voltage Noise en p-p f = 0.1 Hz to 10 Hz 1.5 μV p-p
Voltage Noise Density en f = 1 kHz 36 nV/√Hz
Current Noise Density in f = 1 kHz 5 fA/√Hz

Rev. B | Page 4 of 20

ADA4062-2/ADA4062-4

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage ±18 V
Input Voltage ±VSY
Differential Input Voltage ±VSY
Input Current ±10 mA
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. It was
measured using a standard 4-layer board.

Table 4. Thermal Resistance

Package Type θJA θ

8-Lead SOIC 120 45 °C/W
8-Lead MSOP 142 45 °C/W
10-Lead LFCSP 132 46 °C/W
14-Lead TSSOP 112 35 °C/W
16-Lead LFCSP 75 12 °C/W

Unit

JC

POWER SEQUENCING

The supply voltages of the op amps must be established
simultaneously with, or before, any input signals are applied. If
this is not possible, the input current must be limited to 10 mA.

ESD CAUTION

Rev. B | Page 5 of 20

ADA4062-2/ADA4062-4

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, unless otherwise noted.

70

VSY = ±5V
V

= 0V

CM

BASED ON 600 OP AMPS

60

280

VSY = ±15V
V

= 0V

CM

BASED ON 600 OP AM PS

240

50

40

30

20

NUMBER OF AMPLI FERS

10

0

–4 –3 –2 –1 0 1 2 43

VOS (mV)

Figure 5. Input Offset Voltage Distribution

40

ADA4062-2 ONLY
V

= ±5V

SY

–40°C  T
BASED ON 200 OP AMP S

30

20

NUMBER OF AMPLIFERS

10

 +125°C

A

200

160

120

80

NUMBER OF AMPLI FERS

40

0

–4 –3 –2 –1 0 1 2 43

07670-054

VOS (mV)

07670-003

Figure 8. Input Offset Voltage Distribution

40

30

20

NUMBER OF AMPLIFERS

10

ADA4062-2 ONLY
V

= ±15V

SY

–40°C  T
BASED ON 200 OP AM PS

 +125°C

A

0

–20246810

TCVOS (µV/°C)

Figure 6. Input Offset Voltage Drift Distribution

NUMBER OF AMPLIF IERS

25

20

15

10

5

0

2 4 6 8 10 12 14 16

0

TCV

ADA4062-4 ONLY
V

= ±5V

SY

–40°C  T  125°C
BASED ON 200 O P AMPS

(µV/°C)

OS

Figure 7. Input Offset Voltage Drift Distribution

07670-055

18

07670-070

Rev. B | Page 6 of 20

0

–2 0 2 4 6 8 10

TCVOS (µV/°C)

Figure 9. Input Offset Voltage Drift Distribution

25

20

15

10

NUMBER OF AMPLIF IERS

5

0

0 2 4 6 8 1012141618

TCVOS (µV/°C)

ADA4062-4 ONLY
V

= ±15V

SY

–40°C  T  125°C
BASED ON 200 OP AMPS

Figure 10. Input Offset Voltage Drift Distribution

07670-005

07670-069

ADA4062-2/ADA4062-4

5

= ±5V

V

SY

4

3

2

1

0

(mV)

OS

V

–1

–2

–3

–4

–5

–4 –3 –2 –1 0 1 2 3 4 5

VCM (V)

Figure 11. Input Offset Voltage vs. Common-Mode Voltage

10000

VSY = ±5V

07670-056

5

VSY = ±15V

4

3

2

1

0

(mV)

OS

V

–1

–2

–3

–4

–5

–15 –12 –9 –6 –3 0 3 6 9 12 15

VCM (V)

Figure 14. Input Offset Voltage vs. Common-Mode Voltage

10000

VSY = ±15V

07670-006

1000

100

(pA)

B

I

10

1

0.1
–50 –25 0 25 50 75 100 125

TEMPERATURE (°C)

Figure 12. Input Bias Current vs. Temperature

3

VSY = ±5V

2

1

(pA)

B

I

0

–1

1000

100

(pA)

B

I

10

1

0.1
–50 –25 0 25 50 75 100 125

07670-012

TEMPERATURE (°C)

07670-009

Figure 15. Input Bias Current vs. Temperature

5

VSY = ±15V

4

3

(pA)

B

I

2

1

–2

–3–2–1012345

VCM (V)

Figure 13. Input Bias Current vs. Common-Mode Voltage

07670-013

Rev. B | Page 7 of 20

0

–12–10–8–6–4 –2 0 2 4 6 810121416

VCM (V)

Figure 16. Input Bias Current vs. Common-Mode Voltage

07670-010

ADA4062-2/ADA4062-4

10

VSY = ±5V

10

VSY = ±15V

V+ – V

OH

1

OUTPUT VOLTAGE TO SUPPLY RAIL (V)

0.1

0.01 0.1 1 10 100

VOL – V–

LOAD CURRENT (mA)

Figure 17. Output Voltage to Supply Rail vs. Load Current

220

200

180

160

140

120

100

80

60

SUPPLY CURRENT/AM P (µA)

40

20

0

0 2 4 6 8 1012141618

SUPPLY VOLTAGE (±V)

+85°C

+125°C

+25°C

–40°C

Figure 18. Supply Current/Amp vs. Supply Voltage

2.0

1.5

1.0

V+ – V

VOL – V–

OH

VSY = ±5V
R

= 10k

L

V+ – V

OH

1

OUTPUT VOLTAGE TO SUPPLY RAIL (V)

0.1

0.01 0.1 1 10 100

07670-014

VOL – V–

LOAD CURRENT (mA)

07670-011

Figure 20. Output Voltage to Supply Rail vs. Load Current

200

190

180

170

160

150

140

130

SUPPLY CURRENT/AM P (µA)

120

110

100

–50 –25 0 25 50 75 100 125 150

07670-146

VSY = ±15V

= ±5V

V

SY

TEMPERATURE (° C)

07670-149

Figure 21. Supply Current/Amp vs. Temperature

2.0

1.5

1.0

V+ – V

VOL – V–

OH

V

SY

R

L

= ±15V

= 10k

0.5

OUTPUT VOTL AGE TO SUPPLY RAIL (V)

0

–50 –25 1250 25 50 75 100

TEMPERATURE

(°C)

Figure 19. Output Voltage to Supply Rail vs. Temperature

07670-018

Rev. B | Page 8 of 20

0.5

OUTPUT VOTLAGE TO SUPPLY RAIL (V)

0

–50 –25 1250 25 50 75 100

TEMPERATURE (°C)

Figure 22. Output Voltage to Supply Rail vs. Temperature

07670-015

ADA4062-2/ADA4062-4

120

100

80

60

40

20

GAIN (dB)

0

–20

–40

–60

1k 10k 100k 1M 10M 100M

PHASE

GAIN

FREQUENCY (Hz)

Figure 23. Open-Loop Gain and Phase vs. Frequency

50

AV = +100

40

30

AV = +10

20

10

GAIN (dB)

AV = +1

0

VSY = ±5V

VSY = ±5V

120

100

80

60

40

20

0

–20

–40

–60

120

100

80

60

40

20

GAIN (dB)

PHASE (Degrees)

07670-019

0

–20

–40

–60

1k 10k 100k 1M 10M 100M

PHASE

GAIN

FREQUENCY (Hz)

VSY = ±15V

120

100

80

60

40

20

0

–20

–40

–60

PHASE (Degrees)

07670-016

Figure 26. Open-Loop Gain and Phase vs. Frequency

50

AV = +100

40

30

AV = +10

20

10

GAIN (dB)

AV = +1

0

VSY = ±15V

–10

–20

10 10 0 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 24. Closed-Loop Gain vs. Frequency

1000

VSY = ±5V

100

AV = +100

()

10

AV = +10

OUT

Z

1

AV = +1

0.1
100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 25. Output Impedance vs. Frequency

–10

–20

10 10 0 1k 10k 100k 1M 10M 100M

07670-020

FREQUENCY (Hz)

07670-017

Figure 27. Closed-Loop Gain vs. Frequency

1000

VSY = ±15V

100

AV = +100

()

10

AV = +10

OUT

Z

1

AV = +1

0.1
100 1k 10k 100k 1M 10M

07670-021

FREQUENCY (Hz)

07670-018

Figure 28. Output Impedance vs. Frequency

Rev. B | Page 9 of 20

ADA4062-2/ADA4062-4

100

90

80

70

60

50

CMRR (dB)

40

30

20

10

0

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

VSY = ±5V

Figure 29. CMRR vs. Frequency

120

100

80

60

PSRR+

40

PSRR (dB)

20

0

PSRR–

07670-025

VSY = ±5V

100

90

80

70

60

50

CMRR (dB)

40

30

20

10

0

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

VSY = ±15V

Figure 32. CMRR vs. Frequency

140

120

100

80

60

PSRR (dB)

40

20

0

PSRR–

VSY = ±15V

PSRR+

07670-022

–20

10 100

1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 30. PSRR vs. Frequency

60

VSY = ±5V
A

= +1

V

R

= 10k

L

50

40

30

OVERSHOOT (%)

20

10

0

10 100 1000 10000

CL (pF)

Figure 31. Small-Signal Overshoot vs. Load Capacitance

–20

10 100

07670-026

1k 10k 100k 1M 10M

FREQUENCY (Hz)

07670-023

Figure 33. PSRR vs. Frequency

60

VSY = ±15V
A

= +1

V

R

= 10k

L

50

40

30

OVERSHOOT (%)

20

10

0

10 100 1000 10000

07670-030

CL (pF)

07670-027

Figure 34. Small-Signal Overshoot vs. Load Capacitance

Rev. B | Page 10 of 20

ADA4062-2/ADA4062-4

VSY = ±5V
V

= 4V p-p

IN

A

= +1

V

R

= 10k

L

C

= 100pF

L

VOLTAGE (1V/DIV )

TIME (4µs/DIV)

Figure 35. Large-Signal Transient Response

VSY = ±5V
V

= 100mV p-p

IN

A

= +1

V

R

= 10k

L

C

= 100pF

L

VOLTAGE (20mV/DIV)

VSY = ±15V
V

= 20V p-p

IN

A

= +1

V

R

= 10k

L

C

= 100pF

L

VOLTAGE (5V/DIV)

07670-031

TIME (10µs/DIV)

07670-028

Figure 38. Large-Signal Transient Response

VSY = ±15V
V

= 100mV p-p

IN

A

= +1

V

R

= 10k

L

C

= 100pF

L

VOLTAGE (20mV/DIV)

TIME (10µs/DIV)

Figure 36. Small-Signal Transient Response

4

2

0

INPUT VOLTAGE (V)

INPUT

OUTPUT

TIME (2µs/DIV)

VSY = ±5V
A

=–10

V

Figure 37. Negative Overload Recovery

07670-032

TIME (10µs/DIV)

07670-029

Figure 39. Small-Signal Transient Response

4

2

0

0

OUTPUT VOLTAGE (V)

–2

–4

–6

07670-036

INPUT VOLTAGE (V )

INPUT

OUTPUT

TIME (2µs/DIV)

VSY = ±15V

=–10

A

V

0

–5

–10

–15

–20

OUTPUT VOLTAGE (V)

07670-033

Figure 40. Negative Overload Recovery

Rev. B | Page 11 of 20

ADA4062-2/ADA4062-4

2

0

INPUT

VSY = ±5V
A

=–10

V

2

0

INPUT

VSY = ±15V
A

=–10

V

INPUT VOLTAGE (V)

–2

VOLTAGE (1V/DIV)

INPUT

OUTPUT

VSY = ±5V

= 100pF

C

L

= 10k

R

L

OUTPUT

TIME (2µs/DIV)

Figure 41. Positive Overload Recovery

ERROR BAND

TIME (2µs/DIV)

Figure 42. Positive Settling Time to 0.1%

4

2

0

–2

+20mV

0V

–20mV

–2

15

10

OUTPUT VOLTAGE (V)

07670-037

INPUT VOLTAGE (V)

OUTPUT

TIME (2µs/DIV)

5

OUTPUT VOLTAGE (V)

0

–5

07670-034

Figure 44. Positive Overload Recovery

INPUT

+100mV

OUTPUT

VOLTAGE (5V/DIV)

VSY = ±15V

= 100pF

C

L

= 10k

R

L

07670-075

TIME (2µs/DIV)

ERROR BAND

0V

–100mV

07670-077

Figure 45. Positive Settling Time to 0.1%

VOLTAGE (1V/DIV)

INPUT

OUTPUT

ERROR BAND

TIME (2µs/DIV)

Figure 43. Negative Settling Time to 0.1%

VSY = ±5V

= 100pF

C

L

= 10k

R

L

+20mV

0V

–20mV

07670-076

Rev. B | Page 12 of 20

VOLTAGE (5V/DIV)

INPUT

OUTPUT

ERROR BAND

TIME (2µs/DIV)

Figure 46. Negative Settling Time to 0.1%

VSY = ±15V

= 100pF

C

L

= 10k

R

L

+100mV

0V

–100mV

07670-078

ADA4062-2/ADA4062-4

1000

VSY = ±5V

1000

VSY = ±15V

100

VOLTAGE NOISE DENSITY (nV/Hz)

10

1101001k

FREQUENCY (Hz)

Figure 47. Voltage Noise Density

VSY = ±5V

INPUT NOISE VOLTAGE (0.5µV/DIV)

TIME (1s/ DIV)

07670-044

Figure 48. 0.1 Hz to 10 Hz Noise

0

VSY = ±5V
V

IN

–20

R

= 10k

L

ADA4062-2 ONLY

–40

–60

= 5V p-p

100k

1k

R

L

100

VOLTAGE NOISE DENSI TY (nV/ Hz)

10

1101001k

07670-043

FREQUENCY (Hz)

07670-040

Figure 50. Voltage Noise Density

VSY = ±15V

INPUT NOISE VOLTAGE (0.5µV/DIV)

TIME (1s/ DIV)

07670-041

Figure 51. 0.1 Hz to 10 Hz Noise

0

VSY = ±15V
V

IN

–20

R

= 10k

L

ADA4062-2 ONLY

–40

–60

= 10V p-p

100k

1k

R

L

–80

–100

–120

CHANNEL SEPARATION (dB)

–140

–160

100 1k 10k 100k

FREQUENCY (Hz)

Figure 49. Channel Separation vs. Frequency (ADA4062-2 Only)

07670-049

Rev. B | Page 13 of 20

–80

–100

–120

CHANNEL SEPARATION (dB)

–140

–160

100 1k 10k 100k

FREQUENCY (Hz)

Figure 52. Channel Separation vs. Frequency (ADA4062-2 Only)

07670-046

ADA4062-2/ADA4062-4

0

VSY = ±5V
V

= 5V p-p

IN

–20

R

= 10k

L

ADA4062-4 ONLY

–40

–60

–80

–100

–120

CHANNEL SEPARATIO N (dB)

–140

–160

100 1k 10k 100k

FREQUENCY (Hz)

100k

R

L

Figure 53. Channel Separation vs. Frequency (ADA4062-4 Only)

100

VS = ±5V
f = 1kHz

= 10k

R

L

10

1

0.1

THD + N (%)

1k

0

VSY = ±15V
V

= 10V p-p

IN

–20

R

= 10k

L

ADA4062-4 ONLY

–40

–60

–80

–100

–120

CHANNEL SEPARATION (dB)

–140

–160

100 1k 10k 100k

07670-067

FREQUENCY (Hz)

100k

1k

R

L

07670-066

Figure 56. Channel Separation vs. Frequency (ADA4062-4 Only)

10

1

0.1

THD + N (%)

0.01

0.001

0.001 0.01 0.1 1 10

AMPLITUDE (V rms)

Figure 54. THD + N vs. Amplitude

1

VSY = ±5V
V

= 0.5V rms

IN

R

= 10k

L

0.1

THD + N (%)

0.01

0.001
10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 55. THD + N vs. Frequency

0.01

VS = ±15V
f = 1kHz
R

= 10k

L

0.001

0.001 0.01 0.1 1 10

07670-071

AMPLITUDE (V rms)

07670-072

Figure 57 THD + N vs. Amplitude

1

VS = ±15V
V

= 2V rms

IN

R

= 10k

L

0.1

THD + N (%)

0.01

0.001
100 1k 10k 100k 1M

07670-073

FREQUENCY (Hz)

7670-074

Figure 58. THD + N vs. Frequency

Rev. B | Page 14 of 20

ADA4062-2/ADA4062-4

V

APPLICATIONS INFORMATION

NOTCH FILTER

A notch filter rejects a specific interfering frequency and can be
implemented using a single op amp. Figure 59 shows a 60 Hz
notch filter that uses the twin-T network with the ADA4062-x
configured as a voltage follower. The ADA4062-x works as a buffer
that provides high input resistance and low output impedance.
The low bias current (2 pA typical) and high input resistance
(10 TΩ typical) of the ADA4062-x enable large resistors and small
capacitors to be used.

Alternatively, different combinations of resistor and capacitor
values can be used to achieve the desired notch frequency.
However, the major drawback to this circuit topology is the
need to ensure that all the resistors and capacitors be closely
matched. If they are not closely matched, the notch frequency
offset and drift cause the circuit to attenuate at a frequency
other than the ideal notch frequency.

Therefore, to achieve the desired performance, 1% or better
component tolerances are usually required. In addition, a notch
filter requires an op amp with a bandwidth of at least 100× to
200× the center frequency. Hence, using the ADA4062-x with
a bandwidth of 1.4 MHz is excellent for a 60 Hz notch filter.
Figure 60 shows the frequency response of the notch filter. At
60 Hz, the notch filter has about 50 dB attenuation of signal.

+V

SY

R1

804k

IN

C1

3.3nF

1

f

=

O

2 R

1 C1

R1 = R2 = 2R3

C3

C1 = C2 =

2

Figure 59. Notch Filter Circuit

20

10

0

–10

–20

–30

GAIN (dB)

–40

–50

–60

–70

–80

10 100 1k

Figure 60. Frequency Response of the Notch Filter

R2

804k

C3

6.6nF

R3
402k

C2

3.3nF

FREQUENCY (Hz)

ADA4062-x

–V

SY

V

O

07670-060

07670-057

HIGH-SIDE SIGNAL CONDITIONING

Many applications require the sensing of signals near the positive
rail. The ADA4062-x can be used in high-side current sensing
applications. Figure 61 shows a high-side signal conditioning
circuit using the ADA4062-x. The ADA4062-x has an input
common-mode range that includes the positive supply (−11.5 V ≤
V

≤ +15 V). In the circuit, the voltage drop across a low value

CM

resistor, such as the 0.1 Ω shown in Figure 61, is amplified by a
factor of 5 using the ADA4062-x.

+15

100k

500k

Figure 61. High-Side Signal Conditioning

0.1

100k

500k

+15V

ADA4062-x

–15V

R

L

V

O

07670-058

MICROPOWER INSTRUMENTATION AMPLIFIER

The ADA4062-2 is a dual amplifier and is perfectly suited for
applications that require lower supply currents. For supply
voltages of ±15 V, the supply current per amplifier is 165 μA
typical. The ADA4062-2 also offers a typical low offset voltage
drift of 5 μV/°C and a very low bias current of 2 pA, which
make it well suited for instrumentation amplifiers.

Figure 62 shows the classic 2-op-amp instrumentation amplifier
with four resistors using the ADA4062-2. The key to high CMRR
for this instrumentation amplifier are resistors that are well
matched to both the resistive ratio and relative drift. For true
difference amplification, matching of the resistor ratio is very
important, where R3/R4 = R1/R2. Assuming perfectly matched
resistors, the gain of the circuit is 1 + R2/R1, which is approximately

100. Tighter matching of two op amps in one package, as is the
case with the ADA4062-2, offers a significant boost in performance
over the classical 3-op-amp configuration. Overall, the circuit only
requires about 330 μA of supply current.

R3

10.1k

+15V

R4

1M

1/2

R1

10.1k

ADA4062-2

V1

V2

VO = 100(V2 – V1)
TYPICAL: 0.5mV < V2 – V1< 135mV
TYPICAL: –13.8V < V
USE MATCHED RESIS TORS

–15V

< +13.5V

O

Figure 62. Micropower Instrumentation Amplifier

R2

1M

+15V

1/2

ADA4062-2

–15V

V

O

07670-059

Rev. B | Page 15 of 20

ADA4062-2/ADA4062-4

T

PHASE REVERSAL

Phase reversal occurs in some amplifiers when the input common­mode voltage range is exceeded. When the voltage driving the
input to these amplifiers exceeds the maximum input common­mode voltage range, the output of the amplifiers changes polarity.
Most JFET input amplifiers have phase reversal if either input
exceeds the input common-mode range.

For the ADA4062-x, the output does not phase reverse if one
or both of the inputs exceeds the input voltage range but remains
within the positive supply rail and 0.5 V above the negative
supply rail. In other words, for an application with a supply
voltage of ±15 V, the input voltage can be as high as +15 V
without any output phase reversal. However, when the voltage
of the inputs is driven beyond −14.5 V, phase reversal occurs
due to saturation of the input stage leading to forward biasing
of the gate-drain diode. Phase reversal in ADA4062-x can be
prevented by using a Schottky diode to clamp the input terminals
to each other. In the simple buffer circuit in Figure 63, D1
protects the op amp against phase reversal, and R limits the
input current that flows into the op amp.

+V

SY

R

IN5711

D1

ADA4062-x

–V

SY

10k

Figure 63. Phase Reversal Solution Circuit

V

O

07670-053

V

IN

V

OUT

AGE (5V/DIV)

VOL

TIME (40µs/DIV)

Figure 64. No Phase Reversal

VSY = ±15V

07670-063

Rev. B | Page 16 of 20

ADA4062-2/ADA4062-4

–

V

SCHEMATIC

+

OUT

IN

Figure 65. Simplified Schematic of the ADA4062-x

+IN

V–

07670-062

Rev. B | Page 17 of 20

ADA4062-2/ADA4062-4

OUTLINE DIMENSIONS

3.20

3.00

2.80

8

5

3.20

3.00

2.80

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

1

0.65 BSC

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 66. 8-Lead Mini Small Outline Package [MSOP]

5.00 (0.1968)

4.80 (0.1890)

5.15

4.90

4.65

4

15° MAX

6°
0°

0.23

0.09

0.40

0.25

1.10 MAX

(RM-8)

Dimensions shown in millimeters

0.80

0.55

0.40

100709-B

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

Figure 67. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

0.40

BSC

0.05 MAX

0.02 NOM

(CP-10-10)

0.55

0.40

0.30

9

1

46

BOTTOM VIEW

N

I

1

P

E

I

R

F

I

E

N

T

D

I

0.35

0.30

0.25

033007-A

0.20 DIA
TYP

0.60

0.55

0.50

SEATING

PLANE

1.30

1.60

TOP VI EW

0.20 BSC

Figure 68. 10-Lead Lead Frame Chip Scale Package [LFCSP_UQ]

1.30 mm × 1.60 mm, Body, Ultra Thin Quad

Dimensions shown in millimeters

Rev. B | Page 18 of 20

ADA4062-2/ADA4062-4

4.50

4.40

4.30

PIN 1

1.05

1.00

0.80

0.15

0.05

COPLANARITY

0.10

5.10

5.00

4.90

14

1

0.65 BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

8

6.40
BSC

7

1.20

0.20

MAX

0.09

SEATING
PLANE

8°
0°

0.75

0.60

0.45

061908-A

Figure 69. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

PIN 1

INDICATOR

0.80

0.75

0.70

SEATING

PLANE

3.10

3.00 SQ

2.90

0.50

BSC

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

0.30

0.23

0.18

13

12

9

8

BOTTOM VIEWTOP VIEW

COPLANARITY

0.08

1

P

N

I

D

C

I

A

N

I

16

1

EXPOSED

PAD

5

FORPROPERCONNECTIONOF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

1.75

1.60 SQ

1.45

4

0.20 MIN

R

O

T

COMPLIANTTOJEDEC STANDARDS MO-220-WEED-6.

01-13-2010-D

Figure 70. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

3 mm × 3 mm Body, Very Very Thin Quad

(CP-16-22)

Dimensions shown in millimeters

Rev. B | Page 19 of 20

ADA4062-2/ADA4062-4

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option Branding

ADA4062-2ARMZ −40°C to +125°C 8-Lead MSOP RM-8 A25
ADA4062-2ARMZ-RL −40°C to +125°C 8-Lead MSOP RM-8 A25
ADA4062-2ARMZ-RL7 −40°C to +125°C 8-Lead MSOP RM-8 A25
ADA4062-2ARZ −40°C to +125°C 8-Lead SOIC_N R-8
ADA4062-2ARZ-R7 −40°C to +125°C 8-Lead SOIC_N R-8
ADA4062-2ARZ-RL −40°C to +125°C 8-Lead SOIC_N R-8
ADA4062-2BRZ −40°C to +125°C 8-Lead SOIC_N R-8
ADA4062-2BRZ-R7 −40°C to +125°C 8-Lead SOIC_N R-8
ADA4062-2BRZ-RL −40°C to +125°C 8-Lead SOIC_N R-8
ADA4062-2ACPZ-R2 −40°C to +125°C 10-Lead LFCSP_UQ CP-10-10 J
ADA4062-2ACPZ-RL −40°C to +125°C 10-Lead LFCSP_UQ CP-10-10 J
ADA4062-2ACPZ-R7 −40°C to +125°C 10-Lead LFCSP_UQ CP-10-10 J
ADA4062-4ARUZ −40°C to +125°C 14-Lead TSSOP RU-14
ADA4062-4ARUZ-RL −40°C to +125°C 14-Lead TSSOP RU-14
ADA4062-4ACPZ-R2 −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 A2K
ADA4062-4ACPZ-R7 −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 A2K
ADA4062-4ACPZ-RL −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 A2K

1

Z = RoHS Compliant Part.

©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07670-0-2/10(B)

Rev. B | Page 20 of 20