A
2
Low Power JFET-Input Op Amps
FEATURES
Low input bias current: 50 pA maximum
Offset voltage
1.5 mV maximum for B grade (ADA4062-2 SOIC package)
2.5 mV maximum for A grade
Offset voltage drift: 5 μV/°C typical
Slew rate: 3.3 V/μs typical
CMRR: 90 dB typical
Low supply current: 165 μA typical
High input impedance
Unity-gain stable
±5 V to ±15 V dual-supply operation
Packaging
8-lead SOIC, 8-lead MSOP, 10-lead LFCSP, 14-lead TSSOP, and
16-lead LFCSP packages
APPLICATIONS
Power controls and monitoring
Active filters
Industrial/process controls
Body probe electronics
Data acquisition
Integrators
Input buffering
GENERAL DESCRIPTION
The ADA4062-2 and ADA4062-4 are dual and quad JFET-input
amplifiers with industry-leading performance. They offer lower
power, offset voltage, drift, and ultralow bias current. The
ADA4062-2 B grade (SOIC package) features a typical low offset
voltage of 0.5 mV, an offset drift of 5 μV/°C, and a bias current
of 2 pA.
The ADA4062 family is ideal for various applications, including
process controls, industrial and instrumentation equipment,
active filtering, data conversion, buffering, and power control
and monitoring. With a low supply current of 165 μA per
amplifier, they are well suited for lower power applications.
The ADA4062 family is also specified for the extended industrial
temperature range of −40°C to +125°C. The ADA4062-2 is
available in lead-free, 8-lead SOIC, 8-lead MSOP, and 10-lead
LFCSP (1.6 mm × 1.3 mm × 0.55 mm) packages, while the
ADA4062-4 is available in lead-free, 14-lead TSSOP and
16-lead LFCSP packages.
ADA4062-2/ADA4062-4
PIN CONFIGURATIONS
OUT A
1
ADA4062-2
–IN A
2
V–
TOP VIEW
3
(Not to Scale)
4
+IN A
Figure 1. 8-Lead Narrow-Body SOIC and 8-Lead MSOP
OUT
1
N A
–I
2
ADA4062-2
3
+IN A
C = NO CONNECT
N
TOP VIE W
(Not to Scal e)
4
V–
Figure 2. 10-Lead LFCSP
1
OUT A
2
–IN A
3
+IN A
+IN B
–IN B
OUT B
V+
ADA4062-4
TOP VIEW
4
(Not to Scale)
5
6
7
Figure 3. 14-Lead TSSOP
NC
OUT A
16
15
1
–IN A
V+
ADA4062-4
2
3
(Not to Scale)
4
TOP VIEW
5
6
–IN B
OUT B
+IN A
+IN B
NOTES
1. NC = NO CONNECT.
. IT IS RECOMMENDED TO CONNECT THE EXPOSED PAD T O V–.
Figure 4. 16-Lead LFCSP
Table 1. Low Power Op Amps
Precision
CMOS
Precision
High Bandwidth
Single AD8663 AD8641
Dual AD8667 AD8642 AD8682
Quad AD8669 AD8643 AD8684
OUT D
14
7
OUT C
V+
8
OUT B
7
–IN B
6
5
+IN B
07670-001
V+
NC
9
10
OUT B
8
7
–IN B
6
5
NC
+IN B
14
OUT D
13
–IN D
12
+IN D
11
V–
10
+IN C
9
–IN C
8
OUT C
NC
13
12
11
10
9
8
–IN C
–IN D
+IN D
V–
+IN C
07670-065
07670-064
07670-068
High
Bandwidth
Rev. B
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved.
ADA4062-2/ADA4062-4
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Power Sequencing ........................................................................ 5
REVISION HISTORY
2/10—Rev. A to Rev. B
Added 16-Lead LFCSP Package........................................ Universal
Changes to Features Section, General Description Section, and
Table 1 ................................................................................................ 1
Changes to Offset Voltage Drift Parameter, Table 2 .................... 3
Changes to Table 4 ............................................................................ 5
Changes to Typical Performance Characteristics Layout ............ 6
Added Figure 6 and Figure 9; Renumbered Sequentially ........... 6
Changes to Figure 7, Figure 8, and Figure 10 ............................... 6
Changes to Figure 25 and Figure 28 ............................................... 9
Changes to Figure 37 and Figure 40 ............................................. 11
Changes to Figure 41 to Figure 46 ................................................ 12
Changes to Figure 47 and Figure 50 ............................................. 13
Changes to Figure 53 to Figure 58 ................................................ 14
Changes to Notch Filter Section and Micropower Instrumentation
Amplifier Section ............................................................................ 15
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 20
ESD Caution...................................................................................5
Typical Performance Characteristics ..............................................6
Applications Information .............................................................. 15
Notch Filter ................................................................................. 15
High-Side Signal Conditioning ................................................ 15
Micropower Instrumentation Amplifier ................................. 15
Phase Reversal ............................................................................ 16
Schematic ......................................................................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 20
7/09—Rev. 0 to Rev. A
Added ADA4062-4 ............................................................. Universal
Added 14-Lead TSSOP Package ....................................... Universal
Added 10-Lead LFCSP Package ....................................... Universal
Changes to Features Section and Table 1 ....................................... 1
Changes to Table 2 ............................................................................. 3
Changes to Thermal Resistance Section ........................................ 5
Changes to Figure 5, Figure 6, Figure 8, and Figure 9 .................. 6
Changes to Figure 37 and Figure 40............................................. 11
Changes to Figure 41 and Figure 44............................................. 12
Changes to Figure 47, Figure 48, Figure 50, and Figure 51....... 13
Added Figure 49 and Figure 52; Renumbered Sequentially ..... 13
Changes to Figure 57 and Figure 59............................................. 15
Changes to Phase Reversal Section and Figure 61 ..................... 16
Changes to Figure 63 ...................................................................... 17
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 19
10/08—Revision 0: Initial Version
Rev. B | Page 2 of 20
ADA4062-2/ADA4062-4
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VSY = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS
B Grade (ADA4062-2, 8-Lead SOIC Only) 0.5 1.5 mV
−40°C ≤ TA ≤ +125°C 3 mV
A Grade 0.75 2.5 mV
−40°C ≤ TA ≤ +125°C 5 mV
Offset Voltage Drift ∆VOS/∆T −40°C ≤ TA ≤ +125°C 5 μV/°C
Input Bias Current IB 2 50 pA
−40°C ≤ TA ≤ +125°C 5 nA
Input Offset Current IOS 0.5 25 pA
−40°C ≤ TA ≤ +125°C 2.5 nA
Input Voltage Range −40°C ≤ TA ≤ +125°C −11.5 +15 V
Common-Mode Rejection Ratio CMRR
B Grade (ADA4062-2, 8-Lead SOIC Only) VCM = −11.5 V to +11.5 V 80 90 dB
−40°C ≤ TA ≤ +125°C 80 dB
A Grade VCM = −11.5 V to +11.5 V 73 90 dB
−40°C ≤ TA ≤ +125°C 70 dB
Large-Signal Voltage Gain AVO R
−40°C ≤ TA ≤ +125°C 72 dB
Input Resistance RIN 10 TΩ
Input Capacitance, Differential Mode C
Input Capacitance, Common Mode C
1.5 pF
INDM
4.8 pF
INCM
OUTPUT CHARACTERISTICS
Output Voltage High VOH R
−40°C ≤ TA ≤ +125°C 12.5 V
Output Voltage Low VOL R
−40°C ≤ TA ≤ +125°C −12.5 V
Short-Circuit Current ISC 20 mA
Closed-Loop Output Impedance Z
f = 1 kHz, AV = 1 1 Ω
OUT
POWER SUPPLY
Power Supply Rejection Ratio PSRR
B Grade (ADA4062-2, 8-Lead SOIC Only) VSY = ±4 V to ±18 V 80 90 dB
−40°C ≤ TA ≤ +125°C 80 dB
A Grade VSY = ±4 V to ±18 V 74 90 dB
−40°C ≤ TA ≤ +125°C 70 dB
Supply Current per Amplifier ISY I
−40°C ≤ TA ≤ +125°C 260 μA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ, CL = 100 pF, AV = 1 3.3 V/μs
Settling Time tS
Gain Bandwidth Product GBP RL = 10 kΩ, AV = 1 1.4 MHz
Phase Margin ΦM R
Channel Separation (ADA4062-2 Only) CS f = 1 kHz 135 dB
Channel Separation (ADA4062-4 Only) CS f = 1 kHz 130 dB
= 10 kΩ, VO = −10 V to +10 V 76 83 dB
L
= 10 kΩ to VCM 13 13.5 V
L
= 10 kΩ to VCM −13.8 −13 V
L
= 0 mA 165 220 μA
O
To 0.1%, V
= 10 kΩ, AV = 1
R
L
= 10 kΩ, AV = 1 78 Degrees
L
= 10 V step, CL = 100 pF,
IN
3.5 μs
Rev. B | Page 3 of 20
ADA4062-2/ADA4062-4
Parameter Symbol Conditions Min Typ Max Unit
NOISE PERFORMANCE
Voltage Noise en p-p f = 0.1 Hz to 10 Hz 1.5 μV p-p
Voltage Noise Density en f = 1 kHz 36 nV/√Hz
Current Noise Density in f = 1 kHz 5 fA/√Hz
Rev. B | Page 4 of 20
ADA4062-2/ADA4062-4
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage ±18 V
Input Voltage ±VSY
Differential Input Voltage ±VSY
Input Current ±10 mA
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. It was
measured using a standard 4-layer board.
Table 4. Thermal Resistance
Package Type θJA θ
8-Lead SOIC 120 45 °C/W
8-Lead MSOP 142 45 °C/W
10-Lead LFCSP 132 46 °C/W
14-Lead TSSOP 112 35 °C/W
16-Lead LFCSP 75 12 °C/W
Unit
JC
POWER SEQUENCING
The supply voltages of the op amps must be established
simultaneously with, or before, any input signals are applied. If
this is not possible, the input current must be limited to 10 mA.
ESD CAUTION
Rev. B | Page 5 of 20
ADA4062-2/ADA4062-4
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
70
VSY = ±5V
V
= 0V
CM
BASED ON 600 OP AMPS
60
280
VSY = ±15V
V
= 0V
CM
BASED ON 600 OP AM PS
240
50
40
30
20
NUMBER OF AMPLI FERS
10
0
–4 –3 –2 –1 0 1 2 43
VOS (mV)
Figure 5. Input Offset Voltage Distribution
40
ADA4062-2 ONLY
V
= ±5V
SY
–40°C T
BASED ON 200 OP AMP S
30
20
NUMBER OF AMPLIFERS
10
+125°C
A
200
160
120
80
NUMBER OF AMPLI FERS
40
0
–4 –3 –2 –1 0 1 2 43
07670-054
VOS (mV)
07670-003
Figure 8. Input Offset Voltage Distribution
40
30
20
NUMBER OF AMPLIFERS
10
ADA4062-2 ONLY
V
= ±15V
SY
–40°C T
BASED ON 200 OP AM PS
+125°C
A
0
–20246810
TCVOS (µV/°C)
Figure 6. Input Offset Voltage Drift Distribution
NUMBER OF AMPLIF IERS
25
20
15
10
5
0
2 4 6 8 10 12 14 16
0
TCV
ADA4062-4 ONLY
V
= ±5V
SY
–40°C T 125°C
BASED ON 200 O P AMPS
(µV/°C)
OS
Figure 7. Input Offset Voltage Drift Distribution
07670-055
18
07670-070
Rev. B | Page 6 of 20
0
–2 0 2 4 6 8 10
TCVOS (µV/°C)
Figure 9. Input Offset Voltage Drift Distribution
25
20
15
10
NUMBER OF AMPLIF IERS
5
0
0 2 4 6 8 1012141618
TCVOS (µV/°C)
ADA4062-4 ONLY
V
= ±15V
SY
–40°C T 125°C
BASED ON 200 OP AMPS
Figure 10. Input Offset Voltage Drift Distribution
07670-005
07670-069
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