Analog Devices AD9991 Datasheet

10-Bit CCD Signal Processor with

FEATURES 6-Phase Vertical Transfer Clock Support Correlated Double Sampler (CDS) 6 dB to 42 dB 10-Bit Variable Gain Ampliﬁ er (VGA) 10- Bit 27 MHz A/D Converter Black Level Clamp with Variable Level Control Complete On-Chip Timing Generator Precision Timing Core with 800 ps Resolution On-Chip 3 V Horizontal and RG Drivers 2-Phase and 4-Phase H-Clock Modes Electronic and Mechanical Shutter Modes On-Chip Driver for External Crystal On-Chip Sync Generator with External Sync Input 56-Lead LFCSP Package

APPLICATIONS Digital Still Cameras Digital Video Camcorders Industrial Imaging

FUNCTIONAL BLOCK DIAGRAM

Precision Timing

™

Generator

AD9991

GENERAL DESCRIPTION

The AD9991 is a highly integrated CCD signal processor for digital still camera and camcorder applications. It includes a complete analog front end with A/D conversion, combined with a full-function programmable timing generator. The timing generator is capable of supporting both 4- and 6-phase vertical clocking. A Precision Timing core allows adjustment of high speed clocks with 800 ps resolution at 27 MHz operation.

The AD9991 is speciﬁ ed at pixel rates of up to 27 MHz. The analog front end includes black level clamping, CDS, VGA, and a 10-bit A/D converter. The timing generator provides all the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate pulses, substrate clock, and substrate bias control. Operation is programmed using a 3-wire serial interface.

Packaged in a space-saving 56-lead LFCSP, the AD9991 is speciﬁ ed over an operating temperature range of –20°C to +85°C.

VRT VRB

REV. 0

CCDIN

H1–H4

V1–V6

VSG1–VSG5

RG

6dB TO 42dB

CDS

HORIZONTAL

DRIVERS

4

6

V- H

CONTROL

5

VSUB SUBCK HD VD SYNC

VGA

INTERNAL CLOCKS

VREF

PRECISION

TIMING

GENERATOR

SYNC

GENERATOR

10-BIT

ADC

CLAMP

CLOCLI

AD9991

INTERNAL

REGISTERS

SL SCK DATA

10

DOUT

DCLK

MSHUT

STROBE

Information furnished by Analog Devices is be lieved to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

AD9991

SYSTEM PERFORMANCE Includes entire signal chain. Gain Accuracy Low Gain (VGA Code 0) 5.0 5.5 6.0 dB Gain = (0.0351  Code) + 6 dB Max Gain (VGA Code 1023) 40.5 41.5 42.5 dB Peak Nonlinearity, 500 mV Input Signal 0.2 % 12 dB gain applied. Total Output Noise 0.25 LSB rms AC grounded input, 6 dB gain applied. Power Supply Rejection (PSR) 50 dB Measured with step change on supply.

*Input signal characteristics deﬁ ned as follows:

500mV TYP

RESET TRANSIENT

Speciﬁ cations subject to change without notice.

50mV MAX

OPTICAL BLACK PIXEL

1V MAX

INPUT SIGNAL RANGE

–4–

REV. 0

AD9991

TIMING SPECIFICATIONS

(CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, f

= 27 MHz, unless otherwise noted.)

CLI

Parameter Symbol Min Typ Max Unit

MASTER CLOCK, CLI (Figure 4) CLI Clock Period t

CONV

37 ns CLI High/Low Pulsewidth 14.8 18.5 21.8 ns Delay from CLI Rising Edge to Internal Pixel Position 0 t

AFE CLPOB Pulsewidth

AFE SAMPLE LOCATION

1, 2

(Figures 9 and 14) 2 20 Pixels

1

(Figure 7)

SHP Sample Edge to SHD Sample Edge t

DATA OUTPUTS (Figures 8a and 8b) Output Delay from DCLK Rising Edge

1

tOD 8 ns

CLIDLY

S1

17 18.5 ns

6 ns

Pipeline Delay from SHP/SHD Sampling to DOUT 11 Cycles

SERIAL INTERFACE (Figures 40a and 40b) Maximum SCK Frequency f SL to SCK Setup Time t SCK to SL Hold Time t SDATA Valid to SCK Rising Edge Setup t SCK Falling Edge to SDATA Valid Hold t SCK Falling Edge to SDATA Valid Read t

NOTES

1

Parameter is programmable.

2

Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.

Speciﬁ cations subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

With Respect Parameter To Min Max Unit

10 MHz

SCLK

10 ns

LS

10 ns

LH

DS

10 ns

DH

10 ns

DV

10 ns

PA CKAGE THERMAL CHARACTERISTICS Thermal Resistance

JA = 25°C/W*

*

is measured using a 4-layer PCB with the exposed paddle soldered to the

JA

board.

AVDD AVSS –0.3 +3.9 V TCVDD TCVSS –0.3 +3.9 V HVDD HVSS –0.3 +3.9 V RGVDD RGVSS –0.3 +3.9 V DVDD DVSS –0.3 +3.9 V DRVDD DRVSS –0.3 +3.9 V RG Output RGVSS –0.3 RGVDD + 0.3 V

Temperature Package Package Model Range Description Option

AD9991KCP –20°C to +85°C LFCSP CP-56 AD9991KCPRL –20°C to +85°C LFCSP CP-56

ORDERING GUIDE

H1–H4 Output HVSS –0.3 HVDD + 0.3 V Digital Outputs DVSS –0.3 DVDD + 0.3 V Digital Inputs DVSS –0.3 DVDD + 0.3 V SCK, SL, SDATA DVSS –0.3 DVDD + 0.3 V REFT, REFB, CCDIN AVSS –0.3 AVDD + 0.3 V Junction Temperature 150 °C Lead Temperature, 10 sec 350 °C

*Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions above those listed in the operational sections of this speciﬁ cation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise speciﬁ ed, all other voltages are referenced to GND.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily ac cu mu late on the human body and test equipment and can discharge without detection. Although the AD9991 features proprietary ESD pro tec tion circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD pre cau tions are rec om mend ed to avoid per for mance deg ra da tion or loss of functionality.

REV. 0

–5–

AD9991

PIN CONFIGURATION

48 DVSS

52 NC

51 DCLK

49 DVDD

50 HD

55 D1

56 D2

54 D0

53 NC

47 VD

46 SYNC

44 MSHUT

43 SCK

45 STROBE

D3 1

D4 2

D5 3

D6 4

D7 5

D8 6

D9 7

DRVDD 8

DRVSS 9

VSUB 10

SUBCK 11

V1 12

V2 13

V3 14

PIN 1 IDENTIFIER

V4 15

V5 16

V6 17

VSG1 18

AD9991

TOP VIEW

VSG2 19

VSG3 20

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Type2 Description

1 D3 DO Data Output 2 D4 DO Data Output 3 D5 DO Data Output 4 D6 DO Data Output 5 D7 DO Data Output 6 D8 DO Data Output 7 D9 DO Data Output (MSB) 8 DRVDD P Data Output Driver Supply 9 DRVSS P Data Output Driver Ground 10 VSUB DO CCD Substrate Bias 11 SUBCK DO CCD Substrate Clock (E-Shutter) 12 V1 DO CCD Vertical Transfer Clock 1 13 V2 DO CCD Vertical Transfer Clock 2 14 V3 DO CCD Vertical Transfer Clock 3 15 V4 DO CCD Vertical Transfer Clock 4 16 V5 DO CCD Vertical Transfer Clock 5 17 V6 DO CCD Vertical Transfer Clock 6 18 VSG1 DO CCD Sensor Gate Pulse 1 19 VSG2 DO CCD Sensor Gate Pulse 2 20 VSG3 DO CCD Sensor Gate Pulse 3 21 VSG4 DO CCD Sensor Gate Pulse 4 22 VSG5 DO CCD Sensor Gate Pulse 5 23 H1 DO CCD Horizontal Clock 1 24 H2 DO CCD Horizontal Clock 2 25 HVSS P H1–H4 Driver Ground 26 HVDD P H1–H4 Driver Supply 27 H3 DO CCD Horizontal Clock 3 28 H4 DO CCD Horizontal Clock 4 29 RGVSS P RG Driver Ground 30 RG DO CCD Reset Gate Clock 31 RGVDD P RG Driver Supply 32 TCVSS P Analog Ground for Timing Core 33 TCVDD P Analog Supply for Timing Core 34 CLO DO Clock Output for Crystal 35 CLI DI Reference Clock Input

42 SDI

41 SL

40 REFB 39 REFT

38 AVSS

37 CCDIN

36 AVDD

35 CLI

34 CLO

33 TCVDD

32 TCVSS

31 RGVDD

30 RG

29 RGVSS

H1 23

VSG4 21

VSG5 22

H2 24

HVSS 25

H3 27

H4 28

HVDD 26

1

Pin Mnemonic Type2 Description

36 AVDD P Analog Supply for AFE 37 CCDIN AI CCD Signal Input 38 AVSS P Analog Ground for AFE 39 REFT AO Voltage Reference Top Bypass 40 REFB AO Voltage Reference Bottom Bypass 41 SL DI 3-Wire Serial Load Pulse 42 SDI DI 3-Wire Serial Data Input 43 SCK DI 3-Wire Serial Clock 44 MSHUT DO Mechanical Shutter Pulse 45 STROBE DO Strobe Pulse 46 SYNC DI External System Sync Input 47 VD DIO Vertical Sync Pulse

(Input for Slave Mode,

Output for Master Mode) 48 DVSS P Digital Ground 49 DVDD P Power Supply for VSG, V1–V6,

HD/VD, MSHUT, STROBE,

SYNC, and Serial Interface 50 HD DIO Horizontal Sync Pulse

(Input for Slave Mode, Output for

Master Mode) 51 DCLK DO Data Clock Output 52 NC Not Internally Connected 53 NC Not Internally Connected 54 D0 DO Data Output (LSB) 55 D1 DO Data Output 56 D2 DO Data Output

NOTES

1

See Figure 38 for circuit conﬁ guration.

2

AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, DIO = Digital Input/Output, P = Power.

–6–

REV. 0

AD9991

T

TERMINOLOGY Differential Nonlinearity (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a ﬁ nite width. No missing codes guaranteed to 10-bit resolution indicates that all 1024 codes must be present over all operating conditions.

Peak Nonlinearity

Peak nonlinearity, a full signal chain speciﬁ cation, refers to the peak deviation of the output of the AD9991 from a true straight line. The point used as zero scale occurs 0.5 LSB before the ﬁ rst code transition. Positive full scale is deﬁ ned as a level 1.5 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percent-

EQUIVALENT CIRCUITS

AV DD

R

age of the 2 V ADC full-scale signal. The input signal is always appropriately gained up to ﬁ ll the ADC’s full-scale range.

Total Output Noise

The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and represents the rms noise level of the total signal chain at the speciﬁ ed gain setting. The output noise can be converted to an equivalent voltage using the relationship 1 LSB = (ADC Full

n

Scale/2

codes), where n is the bit resolution of the ADC. For the

AD9991, 1 LSB is 1.95 mV.

Power Supply Rejection (PSR)

The PSR is measured with a step change applied to the supply pins. The PSR speciﬁ cation is calculated from the change in the data outputs for a given step change in the supply voltage.

DVD D

DATA

THREE-

STATE

AVSS AVSS

Circuit 1. CCDIN

DVD D

DVSS

Circuit 2. Digital Data Outputs

DRVDD

DRVSS

DOUT

RG, H1–H4

ENABLE

DVSS

Circuit 3. Digital Inputs

HVDD OR

RGVDD

HVSS OR

RGVSS

Circuit 4. H1–H4, RG Drivers

OUTPU

REV. 0

–7–

AD9991–Typical Performance Characteristics

350

TOTA L H1-4 LOAD = 400 pF

300

250

200

POWER DISSIPATION (mW)

150

100

10

VDD = 3.3V

15

SAMPLE RATE (MHz)

VDD = 3.0V

21

TPC 1. Power Dissipation vs. Sample Rate

1.0

0.5

VDD = 2.7V

10

7.5

5

OUTPUT NOISE (LSB)

2.5

27

0

200

400

VGA GAIN CODE (LSB)

600 800

1000

TPC 3. Output Noise vs. VGA Gain

0

DNL (LSB)

–0.5

–1.0

0

200 600 800

400

CODES

TPC 2. Typical DNL Performance

1000

–8–

REV. 0

AD9991

SYSTEM OVERVIEW

Figure 1 shows the typical system block diagram for the AD9991 used in Master mode. The CCD output is processed by the AD9991’s AFE circuitry, which consists of a CDS, VGA, black level clamp, and A/D converter. The digitized pixel information is sent to the digital image processor chip, which performs the postprocessing and compression. To operate the CCD, all CCD timing parameters are programmed into the AD9991 from the system microprocessor through the 3-wire serial interface. From the system master clock, CLI, provided by the image processor or external crystal, the AD9991 generates all of the CCD’s horizontal and vertical clocks and all internal AFE clocks. External synchronization is provided by a SYNC pulse from the microprocessor, which will reset internal counters and resync the VD and HD outputs.

Alternatively, the AD9991 may be operated in Slave mode, in which VD and HD are provided externally from the image processor. In this mode, all AD9991 timing will be synchronized with VD and HD.

V1–V6, VSG1–VSG5, SUBCK

AD9991

AFETG

SYNC

SERIAL INTERFACE

DOUT

DCLK

HD, VD

CLI

DIGITAL

IMAGE

PROCESSING

ASIC

CCD

V- DRIVER

H1–H4, RG, VSUB

CCDIN

MSHUT

STROBE

The H-drivers for H1–H4 and RG are included in the AD9991, allowing these clocks to be directly connected to the CCD. H-drive voltage of up to 3.3 V is supported. An external V-driver is required for the vertical transfer clocks, the sensor gate pulses, and the substrate clock.

The AD9991 also includes programmable MSHUT and STROBE outputs, which may be used to trigger mechanical shutter and strobe (ﬂ ash) circuitry.

Figures 2 and 3 show the maximum horizontal and vertical counter dimensions for the AD9991. All internal horizontal and vertical clocking is controlled by these counters to specify line and pixel locations. Maximum HD length is 4095 pixels per line, and maximum VD length is 4095 lines per ﬁ eld.

MAXIMUM FIELD DIMENSIONS

12-BIT HORIZONTAL = 4096 PIXELS MAX

12-BIT VERTICAL = 4096 LINES MAX

Figure 1. Typical System Block Diagram, Master Mode

MAX VD LENGTH IS 4095 LINES

VD

HD

CLI

MAX HD LENGTH IS 4095 PIXELS

Figure 3. Maximum VD/HD Dimensions

Figure 2. Vertical and Horizontal Counters

REV. 0

–9–

AD9991

PRECISION TIMING HIGH SPEED TIMING GENERATION

The AD9991 generates high speed timing signals using the ﬂ exible Precision Timing core. This core is the foundation for generating the timing used for both the CCD and the AFE: the reset gate RG, horizontal drivers H1–H4, and the SHP/SHD sample clocks. A unique architecture makes it routine for the system designer to optimize image quality by providing precise control over the horizontal CCD readout and the AFE correlated double sampling.

The high speed timing of the AD9991 operates the same in either Master or Slave mode conﬁ guration. For more information on synchronization and pipeline delays, see the Power-Up and Synchronization section.

Timing Resolution

The Precision Timing core uses a 1 master clock input (CLI) as a reference. This clock should be the same as the CCD pixel clock frequency. Figure 4 illustrates how the internal timing core divides the master clock period into 48 steps or edge positions. Using a 20 MHz CLI frequency, the edge resolution of the Precision Timing core is 1 ns. If a 1 system clock is not available, it is also possible to use a 2 reference clock by programming the

POSITION

CLI

P[0] P[48] = P[0]P[12] P[24] P[36]

CLIDIVIDE register (Addr 0x30). The AD9991 will then internally divide the CLI frequency by 2.

The AD9991 also includes a master clock output, CLO, which is the inverse of CLI. This output is intended to be used as a crystal driver. A crystal can be placed between the CLI and CLO pins to generate the master clock for the AD9991. For more information on using a crystal, see Figure 39.

High Speed Clock Programmability

Figure 5 shows how the high speed clocks RG, H1–H4, SHP, and SHD are generated. The RG pulse has programmable rising and falling edges, and may be inverted using the polarity control. The horizontal clocks H1 and H3 have programmable rising and falling edges and polarity control. The H2 and H4 clocks are always inverses of H1 and H3, respectively. Table I summarizes the high speed timing registers and their parameters. Figure 6 shows the typical 2-phase H-clock arrangement in which H3 and H4 are programmed for the same edge location as H1 and H2.

The edge location registers are six bits wide, but there are only 48 valid edge locations available. Therefore, the register values aremapped into four quadrants, with each quadrant containing

t

CLIDLY

1 PIXEL PERIOD

NOTES PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (

t

CLIDLY

= 6ns TYP).

Figure 4. High Speed Clock Resolution from CLI Master Clock Input

3

CCD

SIGNAL

12

RG

56

H1

H2

78

H3

4

H4

PROGRAMMABLE CLOCK POSITIONS:

1. RG RISING EDGE

2. RG FALLING EDGE

3. SHP SAMPLE LOCATION

4. SHD SAMPLE LOCATION

Figure 5. High Speed Clock Programmable Locations

5. H1 RISING EDGE POSITION

6. H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1)

7. H3 RISING EDGE POSITION

8. H3 FALLING EDGE POSITION (H4 IS INVERSE OF H3)

–10–

REV. 0

AD9991

12 edge locations. Table II shows the correct register values for the corresponding edge locations.

Figure 7 shows the default timing locations for all of the high speed clock signals.

H-Driver and RG Outputs

In addition to the programmable timing positions, the AD9991 features on-chip output drivers for the RG and H1–H4 outputs. These drivers are powerful enough to directly drive the CCD inputs. The H-driver and RG current can be adjusted for optimum rise/fall time into a particular load by using the DRVCONTROL register (Addr 0x35). The 3-bit drive setting for each output is adjustable in 4.1 mA increments, with the minimum setting of 0 equal to OFF or three-state, and the maximum setting of 7 equal to 30.1 mA.

As shown in Figures 5, 6, and 7, the H2 and H4 outputs are inverses of H1 and H3, respectively. The H1/H2 crossover voltage is approximately 50% of the output swing. The crossover voltage is not programmable.

Ta b le I. Timing Core Register Parameters for H1, H3, RG, SHP/SHD

Digital Data Outputs

The AD9991 data output and DCLK phases are programmable using the DOUTPHASE register (Addr 0x37, Bits [5:0]). Any edge from 0 to 47 may be programmed, as shown in Figure 8a. Normally, the DOUT and DCLK signals will track in phase based on the DOUTPHASE register contents. The DCLK output phase can also be held ﬁ xed with respect to the data outputs by changing the DCLKMODE register HIGH (Addr 0x37, Bit 6). In this mode, the DCLK output will remain at a ﬁ xed phase equal to CLO (the inverse of CLI) while the data output phase is still programmable.

There is a ﬁ xed output delay from the DCLK rising edge to the DOUT transition, called t

. This delay can be programmed to

OD

four values between 0 ns and 12 ns, by using the DOUTDELAY register (Addr 0x037, Bits [8:7]). The default value is 8 ns.

The pipeline delay through the AD9991 is shown in Figure 8b. After the CCD input is sampled by SHD, there is an 11-cycle delay until the data is available.

Parameter Length Range Description

Polarity 1b High/Low Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion) Positive Edge 6b 0–47 Edge Location Positive Edge Location for H1, H3, and RG Negative Edge 6b 0–47 Edge Location Negative Edge Location for H1, H3, and RG Sampling Location 6b 0-47 Edge Location Sampling Location for Internal SHP and SHD Signals Drive Strength 3b 0–47 Current Steps Drive Current for H1–H4 and RG Outputs (4.1 mA per Step)

CCD

SIGNAL

RG

H1/H3

H2/H4

USING THE SAME TOGGLE POSITIONS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKING.

Figure 6. 2-Phase H-Clock Operation

Ta b le II. Precision Timing Edge Locations

Quadrant Edge Location (Dec) Register Value (Dec) Register Value (Bin)

I 0 to 11 0 to 11 000000 to 001011 II 12 to 23 16 to 27 010000 to 011011 III 24 to 35 32 to 43 100000 to 101011 IV 36 to 47 48 to 59 110000 to 111011

REV. 0

–11–

AD9991

POSITION

PIXEL

PERIOD

RG

H1/H3

H2/H4

CCD

SIGNAL

P[0]

RGr[0]

Hr[0]

NOTES ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.

RGf[12]

P[24]P[12] P[36]

Hf[24]

SHP[24]

t

S1

P[48] = P[0]

SHD[0]

Figure 7. High Speed Timing Default Locations

P[0] P[48] = P[0]

P[12] P[24] P[36]

CLI

CCDIN

SHD

(INTERNAL)

DCLK

DOUT

PIXEL

PERIOD

DCLK

t

OD

DOUT

NOTES DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS.

OUTPUT DELAY (

t

) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.

OD

Figure 8a. Digital Output Phase Adjustment

t

CLIDLY

N-1

N N+1

SAMPLE PIXEL N

N-13

N-12

NOTES DEFAULT TIMING VALUES ARE SHOWN: SHDLOC = 0, DOUT PHASE = 0, DCLKMODE = 0. HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.

N+2

N+3

PIPELINE LATENCY=11 CYCLES

N-3N-4N-5N-6N-7N-8N-9N-10N-11

N-2

N-1

N+12N+11N+10N+9N+8N+7N+6N+5N+4

N

N+13

N+1

N+2

Figure 8b. Pipeline Delay

–12–

REV. 0

AD9991

HORIZONTAL CLAMPING AND BLANKING

The AD9991’s horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. Individual control is provided for CLPOB, PBLK, and HBLK during the different regions of each ﬁ eld. This allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout in order to accommodate different image transfer timing and high speed line shifts.

Individual CLPOB and PBLK Patterns

The AFE horizontal timing consists of CLPOB and PBLK, as shown in Figure 9. These two signals are independently programmed using the registers in Table III. SPOL is the start polarity for the signal, and TOG1 and TOG2 are the ﬁ rst and second toggle positions of the pulse. Both signals are active low and should be programmed accordingly.

A separate pattern for CLPOB and PBLK may be programmed for each 10 V-sequence. As described in the Vertical Timing Generation section, up to 10 separate V-sequences can be created,

HD

CLPOB

PBLK

(1)

(3)(2)

ACTIVE

each containing a unique pulse pattern for CLPOB and PBLK. Figure 9 shows how the sequence change positions divide the readout ﬁ eld into different regions. A different V-Sequence can be assigned to each region, allowing the CLPOB and PBLK signals to be changed accordingly with each change in the vertical timing.

Individual HBLK Patterns

The HBLK programmable timing shown in Figure 10 is similar to CLPOB and PBLK. However, there is no start polarity control. Only the toggle positions are used to designate the start and stop positions of the blanking period. Additionally, there is a polarity control HBLKMASK that designates the polarity of the horizontal clock signals H1–H4 during the blanking period. Setting HBLKMASK high will set H1 = H3 = Low and H2 = H4 = High during the blanking, as shown in Figure 11. As with the CLPOB and PBLK signals, HBLK registers are available in each V-sequence, allowing different blanking signals to be used with different vertical timing sequences.

. . .

ACTIVE

NOTES PROGRAMMABLE SETTINGS: (1) START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW) (2) FIRST TOGGLE POSITION (3) SECOND TOGGLE POSITION

Figure 9. Clamp and Pre-Blank Pulse Placement

Ta b le III. CLPOB and PBLK Pattern Registers

Register Length Range Description

SPOL 1b High/Low Starting Polarity of CLPOB/PBLK for V-Sequence 0–9 TOG1 12b 0–4095 Pixel Location First Toggle Position within Line for V-Sequence 0–9 TOG2 12b 0–4095 Pixel Location Second Toggle Position within Line for V-Sequence 0–9

Ta b le IV. HBLK Pattern Registers

Register Length Range Description

HBLKMASK 1b High/Low Masking Polarity for H1/H3 (0 = H1/H3 Low, 1 = H1/H3 High) HBLKALT 2b 0–3 Alternation Mode Enables Odd/Even Alternation of HBLK Toggle Positions 0 = Disable Alternation. 1 = TOG1–TOG2 Odd, TOG3–TOG6 Even. 2 = 3 = TOG1–TOG2 Even, TOG3–TOG6 Odd HBLKTOG1 12b 0–4095 Pixel Location First Toggle Position within Line for Each V-Sequence 0–9 HBLKTOG2 12b 0–4095 Pixel Location Second Toggle Position within Line for Each V-Sequence 0–9 HBLKTOG3 12b 0–4095 Pixel Location Third Toggle Position within Line for Each V-Sequence 0–9 HBLKTOG4 12b 0–4095 Pixel Location Fourth Toggle Position within Line for Each V-Sequence 0–9 HBLKTOG5 12b 0–4095 Pixel Location Fifth Toggle Position within Line for Each V-Sequence 0–9 HBLKTOG6 12b 0–4095 Pixel Location Sixth Toggle Position within Line for Each V-Sequence 0–9

REV. 0

–13–

AD9991

Generating Special HBLK Patterns

There are six toggle positions available for HBLK. Normally, only two of the toggle positions are used to generate the standard HBLK interval. However, the additional toggle positions may be used to generate special HBLK patterns, as shown in Figure 12. The pattern in this example uses all six toggle positions to generate two extra groups of pulses during the HBLK interval. By changing the toggle positions, different patterns can be created.

HD

12

HBLK

PROGRAMMABLE SETTINGS:

1. FIRST TOGGLE POSITION = START OF BLANKING

2. SECOND TOGGLE POSITION = END OF BLANKING

BLANK BLANK

Figure 10. Horizontal Blanking (HBLK) Pulse Placement

HD

Generating HBLK Line Alternation

One further feature of the AD9991 is the ability to alternate different HBLK toggle positions on odd and even lines. This may be used in conjunction with V-pattern odd/even alternation or on its own. When a 1 is written to the HBLKALT register, TOG1 and TOG2 are used on odd lines only, while TOG3–TOG6 are used on even lines. Writing a 2 to the HBLKALT register gives the opposite result: TOG1 and TOG2 are used on even lines, while TOG3–TOG6 are used on odd lines. See the Vertical Timing Generation, Line Alternation section for more information.

HBLK

H1/H3

H2/H4

THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1).

Figure 11. HBLK Masking Control

TOG1

HBLK

H1/H3

H2/H4

TOG2 TOG3

TOG4 TOG5 TOG6

SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS

Figure 12. Generating Special HBLK Patterns

–14–

REV. 0

AD9991

HORIZONTAL TIMING SEQUENCE EXAMPLE

Figure 13 shows an example CCD layout. The horizontal register contains 28 dummy pixels, which will occur on each line clocked from the CCD. In the vertical direction, there are 10 optical black (OB) lines at the front of the readout and two at the back of the readout. The horizontal direction has four OB pixels in the front and 48 in the back.

Figure 14 shows the basic sequence layout, to be used during the effective pixel readout. The 48 OB pixels at the end of each line are used for the CLPOB signals. PBLK is optional and is often used to blank the digital outputs during the noneffective CCD pixels. HBLK is used during the vertical shift interval.

V

4 OB PIXELS

EFFECTIVE IMAGE AREA

H

HORIZONTAL CCD REGISTER

The HBLK, CLPOB, and PBLK parameters are programmed in the V-sequence registers.

More elaborate clamping schemes may be used, such as adding in a separate sequence to clamp during the entire shield OB lines. This requires conﬁ guring a separate V-sequence for reading out the OB lines.

2 VERTICAL OB LINES

10 VERTICAL OB LINES

48 OB PIXELS

HD

CCDIN

SHP

SHD

H1/H3

H2/H4

HBLK

PBLK

CLPOB

OPTICAL BLACK

28 DUMMY PIXELS

VERTICAL SHIFT

Figure 13. Example CCD Conﬁ guration

OB

DUMMY

EFFECTIVE PIXELS

Figure 14. Horizontal Sequence Example

OPTICAL BLACK

VERT SHIFT

REV. 0

–15–

AD9991

VERTICAL TIMING GENERATION

The AD9991 provides a very ﬂ exible solution for generating vertical CCD timing, and can support multiple CCDs and different system architectures. The 6-phase vertical transfer clocks V1–V6 are used to shift each line of pixels into the horizontal output register of the CCD. The AD9991 allows these outputs to be individually programmed into various readout conﬁ gurations using a four step process.

Figure 15 shows an overview of how the vertical timing is generated in four steps. First, the individual pulse patterns for V1–V6

CREATE THE VERTICAL PATTERN GROUPS (MAXIMUM OF 10 GROUPS).

V1

V2

VPAT 0

VPAT 9

V3

V4

V5

V6

V1

V2

V3

V4

V5

V6

are created by using the vertical pattern group registers. Second, the V-pattern groups are used to build the sequences, where additional information is added. Third, the readout for an entire ﬁ eld is constructed by dividing the ﬁ eld into different regions and then assigning a sequence to each region. Each ﬁ eld can contain up to seven different regions to accommodate different steps of the readout such as high speed line shifts and unique vertical line transfers. Up to six different ﬁ elds may be created. Finally, the Mode register allows the different ﬁ elds to be combined into any order for various readout conﬁ gurations.

BUILD THE V-SEQUENCES BY ADDING LINE START POSITION, # OF REPEATS, AND HBLK/CLPOB PULSES (MAXIMUM OF 10 V-SEQUENCES).

V1

V2

V-SEQUENCE 0

(VPAT0, 1 REP)

V-SEQUENCE 1

(VPAT9, 2 REP)

V-SEQUENCE 2

(VPAT9, N REP)

V3

V4

V5

V6

V1

V2

V3

V4

V5

V6

V1

V2

V3

V4

V5

V6

USE THE MODE REGISTER TO CONTROL WHICH FIELDS ARE USED, AND IN WHAT ORDER (MAXIMUM OF 7 FIELDS MAY BE COMBINED IN ANY ORDER).

FIELD 0

FIELD 3

FIELD 5

FIELD 1 FIELD 2

FIELD 4

FIELD 1 FIELD 4

FIELD 2

Figure 15. Summary of Vertical Timing Generation

–16–

BUILD EACH FIELD BY DIVIDING INTO DIFFERENT REGIONS, AND ASSIGNING A DIFFERENT V-SEQUENCE TO EACH (MAXIMUM OF 7 REGIONS IN EACH FIELD) (MAXIMUM OF 6 FIELDS).

FIELD 0

REGION 0: USE V-SEQUENCE 2

REGION 0: USE V-SEQUENCE 3

REGION 1: USE V-SEQUENCE 0

REGION 0: USE V-SEQUENCE 3

REGION 2: USE V-SEQUENCE 3

REGION 1: USE V-SEQUENCE 2

REGION 3: USE V-SEQUENCE 0

REGION 2: USE V-SEQUENCE 1

REGION 4: USE V-SEQUENCE 2

FIELD 1

FIELD 2

REV. 0

AD9991

Ve r tical Pattern Groups (VPAT)

The vertical pattern groups deﬁ ne the individual pulse patterns for each V1–V6 output signal. Table V summarizes the registers available for generating each of the 10 V-pattern groups. The start polarity (VPOL) determines the starting polarity of the vertical sequence, and can be programmed high or low for each V1–V6 output. The ﬁ rst, second, and third toggle position (VTOG1, VTOG2, VTOG3) are the pixel locations within the line where the pulse transitions. A fourth toggle position (VTOG4) is also available for V-Pattern Groups 8 and 9. All toggle positions are 12-bit values, allowing their placement anywhere in the horizontal line. A separate register, VPATSTART, speciﬁ es the start position of the V-pattern group within the line (see the Ve rtical Sequences section). The VPATLEN register designates

the total length of the V-pattern group, which will determine the number of pixels between each of the pattern repetitions, when repetitions are used (see the Vertical Sequences section).

The FREEZE and RESUME registers are used to temporarily stop the operation of the V1–V6 outputs. At the pixel location speciﬁ ed in the FREEZE register, the V1–V6 outputs will be held static at their current dc state, high or low. The V1–V6 outputs are held until the pixel location speciﬁ ed by RESUME register. Two sets of FREEZE/RESUME registers are provided, allowing the vertical outputs to be interrupted twice in the same line. The FREEZE and RESUME positions are programmed in the V-pattern group registers, but are separately enabled using the VMASK registers, which are described in the Vertical Sequence section.

Ta b le V. Ver tical Pattern Group Registers

Register Length Range Description

VPOL 1b High/Low Starting Polarity of Each V1–V6 Output VTOG1 12b 0–4096 Pixel Location First Toggle Position within Line for Each V1–V6 Output VTOG2 12b 0–4096 Pixel Location Second Toggle Position within Line for Each V1–V6 Output VTOG3 12b 0–4096 Pixel Location Third Toggle Position within Line for Each V1–V6 Output VTOG4 12b 0–4096 Pixel Location Fourth Toggle Position, only Available in V-Pattern Groups 8 and 9 VPATLEN 12b 0–4096 Pixels Total Length of Each V-Pattern Group FREEZE1 12b 0–4096 Pixel Location Holds the V1–V6 Outputs at Their Current Levels (Static DC) RESUME1 12b 0–4096 Pixel Location Resumes Operation of the V1–V6 Outputs to Finish Their Pattern FREEZE2 12b 0–4096 Pixel Location Holds the V1–V6 Outputs at Their Current Levels (Static DC) RESUME2 12b 0–4096 Pixel Location Resumes Operation of the V1–V6 Outputs to Finish Their Pattern

START POSITION OF V-PATTERN GROUP IS PROGRAMMABLE IN V-SEQUENCE REGISTERS

HD

4

V1

V2

V6

PROGRAMMABLE SETTINGS FOR EACH V-PATTERN:

1. START POLARITY

2. FIRST TOGGLE POSITION

3. SECOND TOGGLE POSITION (THIRD TOGGLE POSITION ALSO AVAILABLE, FOURTH TOGGLE POSITION AVAILABLE FOR V-PATTERN GROUPS 8 AND 9)

4. TOTAL PATTERN LENGTH FOR ALL V1–V6 OUTPUTS

1

2

3

1

2

3

1

2

3

Figure 16. Vertical Pattern Group Programmability

REV. 0

–17–

AD9991

Ve r tical Sequences (VSEQ)

The vertical sequences are created by selecting one of the 10 V-pattern groups and adding repeats, start position, and horizontal clamping, and blanking information. Up to 10 V-sequences can be programmed, each using the registers shown in Table VI. Figure 17 shows how the different registers are used to generate each V-sequence.

The VPATSEL register selects which V-pattern group will be used in a given V-sequence. The basic V-pattern group can have repetitions added, for high speed line shifts or line binning, by using the VPATREPO and VPATREPE registers. Generally, the same number of repetitions are programmed into both registers, but if a different number of repetitions is required on odd and

even lines, separate values may be used for each register (see the V-Sequence Line Alternation section). The VPATSTART register speciﬁ es where in the line the V-pattern group will start. The VMASK register is used in conjunction with the FREEZE/ RESUME registers to enable optional masking of the V-outputs. Either or both of the FREEZE1/RESUME1 and FREEZE2/ RESUME2 registers can be enabled.

The line length (in pixels) is programmable using the HDLEN registers. Each V-sequence can have a different line length to accommodate various image readout techniques. The maximum number of pixels per line is 4096. Note that the last line of the ﬁ eld is separately programmable using the HDLAST register located in the Field register section.

Ta b le VI. V-Sequence Registers (see Tables III and IV for HBLK, CLPOB, PBLK Registers)

Register Length Range Description

VPATSEL 4b 0–9 V-Pattern Group # Selected V-Pattern Group for Each V-Sequence. VMASK 2b 0–3 Mask Mode Enables the Masking of V1–V6 Outputs at the Locations Speciﬁ ed by the FREEZE/RESUME Registers. 0 = No Mask, 1 = Enable FREEZE1/RESUME1, 2 = Enable FREEZE2/RESUME2, 3 = Enable both 1 and 2. VPATREPO 12b 0–4095 # of Repeats Number of Repetitions for the V-Pattern Group for Odd Lines. If no odd/even alternation is required, set equal to VPATREPE. VPATREPE 12b 0–4095 # of Repeats Number of Repetitions for the V-Pattern Group for Even Lines. If no odd/even alternation is required, set equal to VPATREPO. VPATSTART 12b 0–4095 Pixel Location Start Position for the Selected V-Pattern Group. HDLEN 12b 0–4095 # of Pixels HD Line Length for Lines in Each V-Sequence.

1

HD

2

3

V1–V6

CLPOB

PBLK

HBLK

PROGRAMMABLE SETTINGS FOR EACH V-SEQUENCE:

1. START POSITION IN THE LINE OF SELECTED V-PATTERN GROUP

2. HD LINE LENGTH

3. V-PATTERN SELECT (VPATSEL) TO SELECT ANY V-PATTERN GROUP

4. NUMBER OF REPETITIONS OF THE V-PATTERN GROUP (IF NEEDED)

5. START POLARITY AND TOGGLE POSITIONS FOR CLPOB AND PBLK SIGNALS

6. MASKING POLARITY AND TOGGLE POSITIONS FOR HBLK SIGNAL

V-PATTERN GROUP

6

44

VPAT REP 2

5

Figure 17. V-Sequence Programmability

VPAT REP 3

–18–

REV. 0

Analog Devices AD9991 Datasheet

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

DIGITAL SPECIFICATIONS

ANALOG SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS*

ORDERING GUIDE

PIN CONFIGURATION

PIN FUNCTION DESCRIPTIONS

Peak Nonlinearity

EQUIVALENT CIRCUITS

Total Output Noise

Power Supply Rejection (PSR)

SYSTEM OVERVIEW

PRECISION TIMING HIGH SPEED TIMING GENERATION

Timing Resolution

High Speed Clock Programmability

H-Driver and RG Outputs

Digital Data Outputs

HORIZONTAL CLAMPING AND BLANKING

Individual CLPOB and PBLK Patterns

Individual HBLK Patterns

Generating Special HBLK Patterns

Generating HBLK Line Alternation

HORIZONTAL TIMING SEQUENCE EXAMPLE

VERTICAL TIMING GENERATION

Ve r tical Pattern Groups (VPAT)

Ve r tical Sequences (VSEQ)