ANALOG DEVICES AD9990 Service Manual

Dual Channel, 14-Bit CCD Signal Processor

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FEATURES

1.8 V AFETG core Internal LDO regulators 24 programmable vertical clock signals Correlated double sampler (CDS) with

−3 dB

, 0 dB, +3 dB, and +6 dB gain 6 dB to 42 dB, 10-bit variable gain amplifier (VGA) 14-bit, 32 Hz analog-to-digital converter (ADC) Black level clamp with variable level control Complete on-chip timing generator Precision Timing c On-chip 3 V horizontal and RG drivers General-purpose outputs (GPOs) for shutter and

stem support On-chip driver for external crystal On-chip sync generator with external sync input 112-ball CSP_BGA package, 8 mm × 8 mm, 0.65 mm pitch

APPLICATIONS

Digital still cameras

ore with ~488 ps resolution

with V-Driver and Precision Timing

AD9990

GENERAL DESCRIPTION

The AD9990 is a highly integrated CCD signal processor for digital still camera applications. It includes a complete analog front end with analog-to-digital conversion and a full-function programmable timing generator for a 2-channel output CCD. Each channel is specified up to 32 MHz. The timing generator is capable of supporting up to 24 vertical clock signals to control advanced CCDs. A Precision Timing™ core allows adjustment of high speed clocks with approximately 488 ps resolution at 32 MHz operation. The AD9990 also contains eight general-purpose outputs that can be used for shutter and system functions.

Each analog front end includes black level clamping, a CDS, a

GA, and a 14-bit ADC. The timing generator provides all the

V necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate pulses, substrate clock, and substrate bias control.

The AD9990 is specified over an operating temperature range o

f −25°C to +85°C.

For more information about the AD9990, contact Analog Devices vi

a email at afe.ccd@analog.com.

CCDIN_A

CCDIN_B

3V INPUT

1.8V OUTPUT 3V INPUT

1.8V OUTPUT

RG_A, RG_B

HL_A, HL_B

H1A TO H4A, H1B TO H4B

XV1 TO XV24

SUBCK

FUNCTIONAL BLOCK DIAGRAM

–3dB, 0dB, + 3dB, +6dB

CDS VGA

–3dB, 0dB, + 3dB, +6dB

CDS VGA

LDO

REG_A

LDO

REG_B 2 2

HORIZONTAL

DRIVERS

REFT_

6dB TO 42dB

VERTICAL CONTROL

VREF_A

TIMING

Figure 1.

REFB_

CLAMP

INTERNAL CLOCKS

HD VD SYNC

REFT_B REFB_B

VREF_B

14-BIT

ADC

14-BIT

ADC

PRECISION

TIMING

GENERATOR

SYNC

GENERATOR

AD9990

DATA

OUTPUT

MUX

INTERNAL

REGISTERS

CLI

CLOGPO1 TO GPO8

RSTB

DOUT

SL SCK SDATA

06894-001

Rev. Sp0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9990

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