ANALOG DEVICES AD9985A Service Manual

110 MSPS/140 MSPS Analog Interface for

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FEATURES

Automated clamping level adjustment
140 MSPS maximum conversion rate
300 MHz analog bandwidth

0.5 V to 1.0 V analog input range
500 ps p-p PLL clock jitter at 110 MSPS

3.3 V power supply
Full sync processing
Sync detect for hot plugging
Midscale clamping
Power-down mode
Low power: 500 mW typical
4:2:2 output format mode

APPLICATIONS

RGB graphics processing
LCD monitors and projectors
Plasma display panels
Scan converters
Microdisplays
Digital TV

Flat Panel Displays

AD9985

FUNCTIONAL BLOCK DIAGRAM

AUTO CLAMP

LEVEL ADJUST

R

AIN

G

AIN

B

AIN

HSYNC
COAS

LAMP

FILT

SOGIN

SCL

SDA

CLAMP

AUTO CLAMP

LEVEL ADJUST

CLAMP

AUTO CLAMP

LEVEL ADJUST

CLAMP

SYNC

PROCESSING

AND CLOCK

GENERATION

SERIAL REGISTER AND

A0

POWER MANAGEMENT

A/D

A/D

A/D

Figure 1.

8

8

8

REF

AD9985

R

OUTA

G

OUTA

B

OUTA

MIDSCV
DTACK

HSOUT
VSOUT
SOGOUT

REF
BYPASS

04799-0-001

GENERAL DESCRIPTION

The AD9985 is a complete 8-bit, 140 MSPS, monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode rate
capability and full power analog bandwidth of 300 MHz
support resolutions up to SXGA (1280 × 1024 at 75 Hz).

The AD9985 includes a 140 MHz triple ADC with internal

1.25 V reference, a PLL, and programmable gain, offset, and
clamp control. The user provides only a 3.3 V power supply,
analog input, and Hsync and COAST signals. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.

The AD9985’s on-chip PLL generates a pixel clock from the
Hsync input. Pixel clock output frequencies range from 12 MHz

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.
When the COAST signal is presented, the PLL maintains its
output frequency in the absence of Hsync. A sampling phase
adjustment is provided. Data, Hsync, and clock output phase
relationships are maintained. The AD9985 also offers full sync
processing for composite sync and sync-on-green applications.

A clamp signal is generated internally or may be provided by
the user through the CLAMP input pin. This interface is fully
programmable via a 2-wire serial interface.

Fabricated in an advanced CMOS process, the AD9985 is
provided in a space-saving 80-lead LQFP surface-mount
plastic package and is specified over the –40°C to +85°C
temperature range.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone]

www.analog.com

© 2004 Analog Devices, Inc. All rights reserved.

AD9985

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TABLE OF CONTENTS

Revision History ........................................................................... 2

2-Wire Serial Register Map....................................................... 16

Specifications..................................................................................... 3

Explanation of Test Levels........................................................... 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Design Guide................................................................................... 11

General Description................................................................... 11

Digital Inputs .............................................................................. 11

Input Signal Handling................................................................ 11

Hsync, Vsync Inputs................................................................... 11

Serial Control Port .....................................................................11

Output Signal Handling............................................................. 11

Clamping .....................................................................................11

RGB Clamping........................................................................ 11

YUV Clamping....................................................................... 12

2-Wire Serial Control Register Detail Chip Identification... 19

PLL Divider Control .................................................................. 19

Clock Generator Control .......................................................... 19

Clamp Timing............................................................................. 20

Hsync Pulsewidth....................................................................... 20

Input Gain................................................................................... 20

Input Offset................................................................................. 20

Mode Control 1 .......................................................................... 21

2-Wire Serial Control Port........................................................ 26

Data Transfer via Serial Interface............................................. 26

Sync Slicer.................................................................................... 28

Sync Separator ............................................................................ 28

PCB Layout Recommendations ............................................... 29

Analog Interface Inputs ............................................................. 29

Power Supply Bypassing............................................................ 29

Gain and Offset Control............................................................ 12

Auto Offset.............................................................................. 12

Sync-on-Green............................................................................ 13

Clock Generation ....................................................................... 13

Power Management.................................................................... 14

Timing.......................................................................................... 15

Hsync Timing .............................................................................15

Coast Timing............................................................................... 15

REVISION HISTORY

5/04—Revision 0: Initial Version

PLL ............................................................................................... 30

Outputs (Both Data and Clocks).............................................. 30

Digital Inputs.............................................................................. 30

Voltage Reference....................................................................... 30

Outline Dimensions....................................................................... 31

Ordering GuIde.......................................................................... 31

Rev. 0 | Page 2 of 32

AD9985

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SPECIFICATIONS

Analog Interface: VD = 3.3 V, VDD = 3.3 V, ADC clock = maximum conversion rate, unless otherwise noted.

Table 1.

AD9985KSTZ-110 AD9985KSTZ-140

Test

Parameter Temp

RESOLUTION 8 8 Bits

DC ACCURACY

Differential Nonlinearity 25°C I ±0.5 +1.25/–1.0 ±0.5 +1.35/−1.0 LSB
Full VI +1.35/–1.0 ±1.45/−1.0 LSB
Integral Nonlinearity 25°C I ±0.5 ±1.85 ±0.5 ±2.0 LSB
Full VI ±2.0 ±2.3 LSB
No Missing Codes Full VI Guaranteed Guaranteed

ANALOG INPUT

Input Voltage Range

Minimum Full VI 0.5 0.5 V p-p

Maximum Full VI 1.0 1.0 V p-p
Gain Tempco 25°C V 100 100 ppm/°C
Input Bias Current 25°C IV 1 1 µA
Full IV 1 1 µA
Input Offset Voltage Full V 7 7 mV
Input Full-Scale Matching Full VI 1.5 8.0 1.5 8.0 % FS
Offset Adjustment Range Full VI 46 49 52 46 49 52 % FS

REFERENCE OUTPUT

Output Voltage Full V 1.25 1.25 V
Temperature Coefficient Full V ±50 ±50 ppm/°C

SWITCHING PERFORMANCE

Maximum Conversion Rate Full VI 110 140 MSPS
Minimum Conversion Rate Full IV 10 10 MSPS
Data to Clock Skew Full IV −0.5 +2.0 −0.5 +2.0 ns
t

Full VI 4.7 4.7 µs

BUFF

t

Full VI 4.0 4.0 µs

STAH

t

Full VI 300 300 ns

DHO

t

Full VI 4.7 4.7 µs

DAL

t

Full VI 4.0 4.0 µs

DAH

t

Full VI 250 250 ns

DSU

t

Full VI 4.7 4.7 µs

STASU

t

Full VI 4.0 4.0 µs

STOTSU

HSYNC Input Frequency Full IV 15 110 15 110 kHz
Maximum PLL Clock Rate Full VI 110 140 MHz
Minimum PLL Clock Rate Full IV 12 12 MHz
PLL Jitter 25°C IV 400 700
Full IV 10001 400 7001 ps p-p
Sampling Phase Tempco Full IV 15 15 ps/°C

DIGITAL INPUTS

Input Voltage, High (VIH) Full VI 2.5 2.5 V
Input Voltage, Low (VIL) Full VI 0.8 0.8 V
Input Current, High (VIH) Full V −1.0 −1.0 µA
Input Current, Low (VIL) Full V +1.0 +1.0 µA
Input Capacitance 25°C V 3 3 pF

Level Min Typ Max Min Typ Max Unit

1

400 700

1

ps p-p

Rev. 0 | Page 3 of 32

AD9985

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AD9985KSTZ-110 AD9985KSTZ-140

Test

Parameter Temp

DIGITAL OUTPUTS

Output Voltage, High (VOH) Full VI VD −0.1 VD −0.1 V
Output Voltage, Low (VOL) Full VI 0.1 0.1 V
Duty Cycle DATACK Full IV 45 50 55 45 50 55 %
Output Coding Binary Binary

POWER SUPPLY

VD Supply Voltage Full IV 3.15 3.3 3.45 3.15 3.3 3.45 V
VDD Supply Voltage Full IV 2.2 3.3 3.45 2.2 3.3 3.45 V
PVD Supply Voltage Full IV 3.15 3.3 3.45 3.15 3.3 3.45 V
ID Supply Current (VD) 25°C V 132 180 mA
IDD Supply Current (VDD)2 25°C V 19 26 mA
IPVD Supply Current (PVD) 25°C V 8 11 mA
Total Power Dissipation Full VI 525 760 650 900 mW
Power-Down Supply Current Full VI 5 15 5 15 mA
Power-Down Dissipation Full VI 16.5 50 16.5 50 mW

DYNAMIC PERFORMANCE

Analog Bandwidth, Full Power 25°C V 300 300 MHz

Transient Response 25°C V 2 2 ns
Overvoltage Recovery Time 25°C V 1.5 1.5 ns

Signal-to-Noise Ratio (SNR) 25°C V 44 43 dB

(Without Harmonics) Full V 43 42 dB
fIN = 40.7 MHz
Crosstalk Full V 55 55 dBc

THERMAL CHARACTERISTICS

θJC Junction-to-Case

Thermal Resistance V 16 16 °C/W

θJA Junction-to-Ambient

Thermal Resistance V 35 35 °C/W

1

VCO range = 10, charge pump current = 110, PLL divider = 1693.

2

DATACK load = 15 pF, data load = 5 pF.

Level

Min Typ Max Min Typ Max Unit

Rev. 0 | Page 4 of 32

AD9985

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Table 2.

AD9985BSTZ-110

Test

Parameter Temp

RESOLUTION 8 Bits

DC ACCURACY LSB

Differential Nonlinearity 25°C I ±0.5 +1.25/−1.0 LSB
Full VI +1.5/−1.0 LSB

Integral Nonlinearity 25°C I ±0.5 ±1.85 LSB
Full VI ±3.2
ANALOG INPUT

Input Voltage Range

Minimum Full VI 0.5 V p-p

Maximum Full VI 1.0 V p-p
Gain Tempco 25°C V 100 ppm/°C
Input Bias Current 25°C IV 1 µA

Full IV 2 µA

Input Offset Voltage Full VI 7 mV
Input Full-Scale Matching Full VI 1.5 8.0 % FS
Offset Adjustment Range Full VI 46 49 52 % FS

REFERENCE OUTPUT

Output Voltage Full VI 1.25 V
Temperature Coefficient Full V ±100 ppm/°C

SWITCHING PERFORMANCE

Maximum Conversion Rate Full VI 110 MSPS
Minimum Conversion Rate Full IV 10 MSPS
Data to Clock Skew Full IV –0.5 +2.0 ns
t

Full VI 4.7 µs

BUFF

t

Full VI 4.0 µs

STAH

t

Full VI 300 ns

DHO

t

Full VI 4.7 µs

DAL

t

Full VI 4.0 µs

DAH

t

Full VI 250 ns

DSU

t

Full VI 4.7 µs

STASU

t

Full VI µs

STAH

HSYNC Input Frequency Full IV 15 110 kHz
Maximum PLL Clock Rate Full VI 110 MHz
Minimum PLL Clock Rate Full IV 12 MHz
PLL Jitter 25°C IV 400 7001 ps p-p

Full IV 10001 ps p-p
Sampling Phase Tempco Full IV 15 ps/°C
DIGITAL INPUTS

Input Voltage, High (VIH) Full VI 2.5 V
Input Voltage, Low (VIL) Full VI 0.8 V
Input Current, High (IIH) Full V −1.0 µA
Input Current, Low (IIL) Full V 1.0 µA
Input Capacitance 25°C V 3 pF

DIGITAL OUTPUTS

Output Voltage, High (VOH) Full VI VD −0.1 V
Output Voltage, Low (VOL) Full VI 0.1 V
Duty Cycle, DATACK Full IV 45 50 55 %
Output Coding Binary

Level Min Typ Max Unit

Rev. 0 | Page 5 of 32

AD9985

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AD9985BSTZ-110

Test

Parameter Temp

POWER SUPPLY

VD Supply Voltage Full IV 3.15 3.3 3.45 V
VDD Supply Voltage Full IV 2.2 3.3 3.45 V
PVD Supply Voltage Full IV 3.15 3.3 3.45 V
ID Supply Current (VD) 25°C V 132 mA
IDD Supply Current (VDD) 2 25°C V 19 mA
IPVD Supply Current (PVD) 25°C V 8 mA
Total Power Dissipation Full VI 525 760 mW
Power-Down Supply Current Full VI 5 15 mA
Power-Down Dissipation Full VI 16.5 50 mW

DYNAMIC PERFORMANCE

Analog Bandwidth, Full Power 25°C V 300 MHz

Transient Response 25°C V 2 ns
Overvoltage Recovery Time 25°C V 1.5 ns

Signal-to-Noise Ratio (SNR) 25°C V 44 dB

(Without Harmonics) Full V 43 dB
fIN = 40.7 MHz

Crosstalk Full V 55 dBc
THERMAL CHARACTERISTICS

θJC Junction-to-Case

Thermal Resistance V 16 °C/W

θJA Junction-to-Ambient

Thermal Resistance V 35 °C/W

1

VCO range = 10, charge pump current = 110, PLL divider = 1693.

2

DATACK load = 15 pF, data load = 5 pF.

Level

Min Typ Max Unit

.

EXPLANATION OF TEST LEVELS

Tes t Le v el

I. 100% production tested.
II. 100% production tested at 25°C and sample tested at specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization testing.
V. Parameter is a typical value only.

VI. 100% production tested at 25°C; guaranteed by design and characterization testing.

Rev. 0 | Page 6 of 32

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ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VD 3.6 V
VDD 3.6 V
Analog Inputs VD to 0.0 V
VREF IN VD to 0.0 V
Digital Inputs 5 V to 0.0 V
Digital Output Current 20 mA
Operating Temperature −40°C to +85°C
Storage Temperature −65°C to +150°C
Maximum Junction Temperature 150°C
Maximum Case Temperature 150°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions outside of those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.

Rev. 0 | Page 7 of 32

AD9985

G

G

G

G

G

G

G

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DDVDD

RED <0>

RED <1>

RED <2>

RED <3>

RED <4>

RED <5>

RED <6>

RED <7>

AD9985

TOP VIEW

COAST

HSYNC

VDDGND

34 35 36 37 38 39 40

FILT

GND

VSYNC

REEN <7>
REEN <6>
REEN <5>
REEN <4>
REEN <3>
REEN <2>
REEN <1>
REEN <0>

BLUE <7>
BLUE <6>
BLUE <5>
BLUE <4>
BLUE <3>
BLUE <2>
BLUE <1>
BLUE <0>

GND

V

80 79 78 77 76 71 70 69 6875 74 73 72

1

GND

GND

V

GND

DD

PIN 1

2

INDICATOR
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20

21 22 23 24 25 26 27 28 29 30 31 32 33

DDVDD

V

GND

GND

GND

DPVD

PV

(Not to Scale)

GND

Figure 2. Pin Configuration

Table 4. Complete Pinout List

Pin Type Mnemonic Function Value Pin No.

Inputs R
G
B

Analog Input for Converter R 0.0 V to 1.0V 54

AIN

Analog Input for Converter G 0.0 V to 1.0V 48

AIN

Analog Input for Converter B 0.0 V to 1.0V 43

AIN

HSYNC Horizontal SYNC Input 3.3 V CMOS 30
VSYNC Vertical SYNC Input 3.3 V CMOS 31
SOGIN Input for Sync-on-Green 0.0 V to 1.0 V 49
CLAMP Clamp Input (External CLAMP Signal) 3.3 V CMOS 38
COAST PLL COAST Signal Input 3.3 V CMOS 29
Outputs Red [7:0] Outputs of Converter Red, Bit 7 is the MSB 3.3 V CMOS 70–77
Green [7:0] Outputs of Converter Green, Bit 7 is the BSB 3.3 V CMOS 2–9
Blue [7:0] Outputs of Converter Blue, Bit 7 is the BSB 3.3 V CMOS 12–19
DATACK Data Output Clock 3.3 V CMOS 67
HSOUT HSYNC Output (Phase-Aligned with DATACK) 3.3 V CMOS 66
VSOUT VSYNC Output (Phase-Aligned with DATACK) 3.3 V CMOS 64
SOGOUT Sync-on-Green Slicer Output 3.3 V CMOS 65
References REF BYPASS Internal Reference Bypass 1.25 V 58
MIDSCV Internal Midscale Voltage Bypass 37

Connection for External Filter Components

FILT

for Internal PLL 33
Power Supply VD Analog Power Supply 3.3 V 39, 42, 45, 46, 51, 52, 59, 62
V

Output Power Supply 3.3 V 11, 22, 23, 69, 78, 79

DD

PVD PLL Power Supply 3.3 V 26, 27, 34, 35

GND Ground 0 V

Control SDA Serial Port Data I/O 3.3 V CMOS 57
SCL Serial Port Data Clock (100 kHz Maximum 3.3 V CMOS 56
A0 Serial Port Address Input 1 3.3 V CMOS 55

DATACK

HSOUT

D

PVDPV

VSOUT

SOGOU

64 63 62 6167 66 65

GND

MIDSCV

GND

VDGND

D

V

CLAMP

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

GND

GND
V

D

REF BYPASS
SDA
SCL
A0
R

AIN

GND
V

D

V

D

GND
SOGIN
G

AIN

GND
V

D

V

D

GND
B

AIN

V

D

GND

04799-0-002

1, 10, 20, 21, 24, 25, 28, 32, 36, 40, 41,
44, 47, 50, 53, 60, 61, 63, 68, 80

Rev. 0 | Page 8 of 32

AD9985

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Table 5. Pin Function Descriptions

Pin
Name

OUTPUTS
HSOUT Horizontal Sync Output

VSOUT Vertical Sync Output

SOGOUT

SERIAL PORT (2-Wire)
SDA Serial Port Data I/O
SCL Serial Port Data Clock
A0 Serial Port Address Input 1
For a full description of the 2-wire serial register and how it works, refer to the 2-wire serial control port section.
DATA OUTPUTS
RED Data Output, Red Channel
GREEN Data Output, Green Channel
BLUE Data Output, Blue Channel

DATA CLOCK OUTPUT
DATACK Data Output Clock

INPUTS
R

Analog Input for Red Channel

AIN

G

AIN

B

Analog Input for Blue Channel

AIN

HSYNC Horizontal Sync Input

VSYNC Vertical Sync Input
The input for vertical sync.

Function

A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be
programmed via serial bus registers. By maintaining alignment with DATACK and Data, data timing with respect to horizontal
sync can always be determined.

A reconstructed and phase-aligned version of the video Vsync. The polarity of this output can be controlled via a serial bus bit.
The placement and duration in all modes is set by the graphics transmitter.

Sync-On-Green Slicer Output

This pin outputs either the signal from the Sync-on-Green slicer comparator or an unprocessed but delayed version of the
Hsync input. See the Sync Processing Block Diagram (Figure 14) to view how this pin is connected. (Note: Besides slicing off
SOG, the output from this pin gets no other additional processing on the AD9985. Vsync separation is performed via the sync
separator.)

The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed. When the sampling time is
changed by adjusting the PHASE register, the output timing is shifted as well. The DATACK and HSOUT outputs are also
moved, so the timing relationship among the signals is maintained. For exact timing information, refer to Figure 9, Figure 10,
and Figure 11.

The main clock output signal used to strobe the output data and HSOUT into external logic. It is produced by the internal clock
generator and is synchronous with the internal pixel sampling clock. When the sampling time is changed by adjusting the
PHASE register, the output timing is shifted as well. The Data, DATACK, and HSOUT outputs are all moved, so the timing
relationship among the signals is maintained.

Analog Input for Green Channel

High impedance inputs that accept the Red, Green, and Blue channel graphics signals, respectively. (The three channels are
identical, and can be used for any colors, but colors are assigned for convenient reference.) They accommodate input signals
ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp operation.

This input receives a logic signal that establishes the horizontal timing reference and provides the frequency reference for pixel
clock generation. The logic sense of this pin is controlled by serial Register 0EH Bit 6 (Hsync Polarity). Only the leading edge of
Hsync is active; the trailing edge is ignored. When Hsync Polarity = 0, the falling edge of Hsync is used. When Hsync Polarity =
1, the rising edge is active. The input includes a Schmitt trigger for noise immunity, with a nominal input threshold of 1.5 V.

Rev. 0 | Page 9 of 32

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Pin
Name

SOGIN Sync-on-Green Input

CLAMP External Clamp Input

COAST Clock Generator Coast Input (Optional)

REF
BYPASS

MIDSCV Midscale Voltage Reference BYPASS

FILT External Filter Connection

POWER SUPPLY
VD Main Power Supply
These pins supply power to the main elements of the circuit. They should be filtered and as quiet as possible.
VDD Digital Output Power Supply

PVD Clock Generator Power Supply

GND Ground

Function

This input is provided to assist with processing signals with embedded sync, typically on the Green channel. The pin is
connected to a high speed comparator with an internally generated threshold. The threshold level can be programmed in
10 mV steps to any voltage between 10 mV and 330 mV above the negative peak of the input signal. The default voltage
threshold is 150 mV. When connected to an ac-coupled graphics signal with embedded sync, it will produce a noninverting
digital output on SOGOUT. (This is usually a composite sync signal, containing both vertical and horizontal sync information
that must be separated before passing the horizontal sync signal to Hsync.) When not used, this input should be left
unconnected. For more details on this function and how it should be configured, refer to the Sync-on-Green section.

This logic input may be used to define the time during which the input signal is clamped to ground. It should be exercised
when the reference dc level is known to be present on the analog input channels, typically during the back porch of the
graphics signal. The CLAMP pin is enabled by setting control bit Clamp Function to 1 (Register 0FH, Bit 7, default is 0). When
disabled, this pin is ignored and the clamp timing is determined internally by counting a delay and duration from the trailing
edge of the Hsync input. The logic sense of this pin is controlled by Clamp Polarity Register 0FH, Bit 6. When not used, this pin
must be grounded and Clamp Function programmed to 0.

This input may be used to cause the pixel clock generator to stop synchronizing with Hsync and continue producing a clock at
its current frequency and phase. This is useful when processing signals from sources that fail to produce horizontal sync pulses
during the vertical interval. The COAST signal is generally not required for PC-generated signals. The logic sense of this pin is
controlled by Coast Polarity (Register 0FH, Bit 3). When not used, this pin may be grounded and Coast Polarity programmed to
1, or tied HIGH (to V

Internal Reference BYPASS

Bypass for the internal 1.25 V band gap reference. It should be connected to ground through a 0.1 µF capacitor. The absolute
accuracy of this reference is ±4%, and the temperature coefficient is ±50 ppm, which is adequate for most AD9985 applica­tions. If higher accuracy is required, an external reference may be employed instead.

Bypass for the internal midscale voltage reference. It should be connected to ground through a 0.1 µF capacitor. The exact
voltage varies with the gain setting of the Blue channel.

For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 8 to this pin.
For optimal performance, minimize noise and parasitics on this node.

A large number of output pins (up to 25) switching at high speed (up to 110 MHz) generates a lot of power supply transients
(noise). These supply pins are identified separately from the V
transferred into the sensitive analog circuitry. If the AD9985 is interfacing with lower voltage logic, V
lower supply voltage (as low as 2.5 V) for compatibility.

The most sensitive portion of the AD9985 is the clock generation circuitry. These pins provide power to the clock PLL and help
the user design for optimal performance. The designer should provide quiet, noise-free power to these pins.

The ground return for all circuitry on-chip. It is recommended that the AD9985 be assembled on a single solid ground plane,
with careful attention given to ground current paths.

through a 10 kΩ resistor) and Coast Polarity programmed to 0. Coast Polarity defaults to 1 at power-up.

D

pins so special care can be taken to minimize output noise

D

may be connected to a

DD

Rev. 0 | Page 10 of 32