ANALOG DEVICES AD9984A Service Manual

High Performance

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FEATURES

10-bit, analog-to-digital converters
170 MSPS maximum conversion rate
Low PLL clock jitter at 170 MSPS
Automatic gain matching
Automated offset adjustment
2:1 input mux
Power-down via dedicated pin or serial register
4:4:4, 4:2:2, and DDR output format modes
Variable output drive strength
Odd/even field detection
External clock input
Regenerated Hsync output
Programmable output high impedance control
Hsyncs per Vsync counter
Sync-on-green (SOG) pulse filter
Pb-free package

APPLICATIONS

Advanced TVs
Plasma display panels
LCDT V
HDTV
RGB graphics processing
LCD monitors and projectors
Scan converters

Pr/RED

Pr/RED

Y/GREEN

Y/GREEN

Pb/BLUE

Pb/BLUE

HSYNC1

HSYNC0

VSYNC0

VSYNC1

SOGIN1

SOGIN0

EXTCK/COAST

CLAMP

FILT

SDA

SCL

10-Bit Display Interface

AD9984A

FUNCTIONAL BLOCK DIAGRAM

IN1

IN0

IN1

IN0

IN1

IN0

AD9984A

2:1

MUX

2:1

MUX

2:1

MUX

2:1

MUX

2:1

MUX

2:1

MUX

SERIAL REGISTER

CLAMP

CLAMP

CLAMP

10

PGA

10

PGA

10

PGA

SYNC

PROCESSING

PLL

POWER

MANAGEMENT

Figure 1.

AUTO OFFSET

AUTO GAIN

10-BIT

ADC

AUTO OFFSET

AUTO GAIN

10-BIT

ADC

AUTO OFFSET

AUTO GAIN

10-BIT

ADC

OUTPUT DATA FORMAT TER

VOLTAGE

REFS

10

10

10

Cb/Cr/RED

OUT

Y/GREEN

OUT

Cb/BLUE

OUT

DATACK

SOGOUT

ODD/EVEN FIELD

HSOUT

VSOUT/A0

REFHI

REFLO

06476-001

GENERAL DESCRIPTION

The AD9984A is a complete 10-bit, 170 MSPS, monolithic
analog interface optimized for capturing YPbPr video and RGB
graphics signals. Its 170 MSPS encode rate capability and full
power analog bandwidth of 300 MHz support all HDTV video
modes up to 1080p, as well as graphics resolutions up to UXGA
(1600 × 1200 at 60 Hz).

The AD9984A includes a 170 MHz triple ADC with an internal
r

eference, a PLL, and programmable gain, offset, and clamp
control. The user provides only a 1.8 V power supply and an
analog input. Three-state CMOS outputs can be powered from

1.8 V to 3.3 V.

The AD9984A on-chip PLL generates a sample clock from the

ri-level sync (for YPbPr video) or the horizontal sync (for RGB

t
graphics). Sample clock output frequencies range from 10 MHz
to 170 MHz. With internal coast generation, the PLL maintains
its output frequency in the absence of a sync input. A 32-step

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

sampling clock phase adjustment is provided. Output data,
sync, and clock phase relationships are maintained.

The auto-offset feature can be enabled to automatically restore

he signal reference levels and calibrate out any offset differences

t
between the three channels. The auto channel-to-channel gain­matching feature can be enabled to minimize any gain
mismatches between the three channels.

The AD9984A also offers full sync processing for composite sync

nd sync-on-green applications. A clamp signal is generated

a
internally or can be provided by the user through the CLAMP
input pin.

Fabricated in an advanced CMOS process, the AD9984A is
p

rovided in a space-saving, Pb-free, 80-lead low profile quad
flat package (LQFP) or 64-lead lead frame chip scale package
(LFCSP) and is specified over the 0°C to 70°C temperature range.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

AD9984A

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Analog Interface Characteristics................................................ 3

Absolute Maximum Ratings............................................................ 5

Explanation of Test Levels........................................................... 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Theory of Operation ...................................................................... 11

Digital Inputs ..............................................................................11

Analog Input Signal Handling.................................................. 11

Hsync and Vsync Inputs............................................................ 11

Serial Control Port ..................................................................... 11

Output Signal Handling............................................................. 11

Clamping .....................................................................................11

Gain and Offset Control............................................................ 12

Sync-on-Green ............................................................................ 13

Reference Bypassing................................................................... 13

Clock Generation .......................................................................14

Sync Processing........................................................................... 16

Power Management.................................................................... 19

Timing Diagrams........................................................................ 19

Hsync Timing ............................................................................. 20

Coast Timing...............................................................................21

Output Formatter ....................................................................... 21

2-Wire Serial Control Port ............................................................ 22

Data Transfer via Serial Interface............................................. 22

2-Wire Serial Register Map ........................................................... 24

2-Wire Serial Control Registers.................................................... 30

Chip Identification ..................................................................... 30

PLL Divider Control.................................................................. 30

Clock Generator Control .......................................................... 30

Phase Adjust................................................................................ 30

Input Gain ................................................................................... 30

Input Offset ................................................................................. 31

Hsync Control............................................................................. 31

Vsync Control............................................................................. 32

Coast and Clamp Controls........................................................ 33

SOG Control ............................................................................... 34

Input and Power Control........................................................... 35

Output Control........................................................................... 35

Sync Processing .......................................................................... 36

Detection Status.......................................................................... 37

Polarity Status ............................................................................. 37

Hsync Count ............................................................................... 38

Test Registers............................................................................... 38

PCB Layout Recommendations.................................................... 40

Analog Interface Inputs............................................................. 40

Outputs (Both Data and Clocks).............................................. 40

Digital Inputs .............................................................................. 41

Outline Dimensions ....................................................................... 42

Ordering Guide .......................................................................... 42

REVISION HISTORY

7/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 44

AD9984A

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SPECIFICATIONS

ANALOG INTERFACE CHARACTERISTICS

VD = 1.8 V, VDD = 3.3 V, PVD = 1.8 V, DAVDD = 1.8 V, ADC clock = maximum conversion rate, full temperature range = 0°C to 70°C.

Table 1. Electrical Characteristics

AD9984AKSTZ-140

Te st

1

Lev

Parameter Temp

RESOLUTION

Number of Bits 10 10 Bits
LSB Size 0.098 0.098 % of full scale (FS)

DC ACCURACY

Differential Nonlinearity 25°C I ±0.6 +1.8/−1.0 ±0.7 +1.9/−1.0 LSB
Full VI +1.9/−1.0 +2.0/−1.0 LSB
Integral Nonlinearity 25°C I ±2.35 ±7.0 ±2.35 ±8.5 LSB
Full VI ±9.0 ±9.0 LSB
No Missing Codes Full VI GNT2 GNT2

ANALOG INPUT

Input Voltage Range

Minimum Full VI 0.5 0.5 V p-p

Maximum Full VI 1.0 1.0 V p-p
Gain Tempco 25°C V 125 125 ppm/°C
Input Bias Current 25°C IV 1 1 μA
Full IV 1 1 μA
Input Full-Scale Matching Full VI 1 1 % FS
Offset Adjustment Range Full VI 50 50 % FS

SWITCHING PERFORMANCE

Maximum Conversion Rate Full VI 140 170 MSPS
Minimum Conversion Rate Full IV 10 10 MSPS
Clock to Data Skew (t
t

BUFF

t

STAH

t

DHO

t

DAL

t

DAH

t

DSU

t

STASU

t

STOSU

Maximum PLL Clock Rate Full VI 140 170 MHz
Minimum PLL Clock Rate Full IV 10 10 MHz
Sampling Phase Tempco Full IV 15 15 ps/°C

DIGITAL INPUTS

Input Voltage, High (VIH) Full VI 1.0 1.0 V
Input Voltage, Low (VIL) Full VI 0.8 0.8 V
Input Current, High (IIH) Full V −1.0 −1.0 μA
Input Current, Low (IIL) Full V 1.0 1.0 μA
Input Capacitance 25°C V 2 2 pF

DIGITAL OUTPUTS

Output Voltage, High (VOH) Full VI VDD − 0.1 VDD − 0.1 V
Output Voltage, Low (VOL) Full VI 0.1 0.1 V
Duty Cycle (DATACK) Full IV 45 50 55 45 50 55 %
Output Coding Binary Binary

) Full IV −0.5 +2.0 −0.5 +2.0 ns

SKEW

Full VI 4.7 4.7 μs
Full VI 4.0 4.0 μs
Full VI 0 0 μs
Full VI 4.7 4.7 μs
Full VI 4.0 4.0 μs
Full VI 250 250 ns
Full VI 4.7 4.7 μs
Full VI 4.0 4.0 μs

el

AD9984AKCPZ-140

Min Typ Max Min Typ Max Unit

AD9984AKSTZ-170
AD9984AKCPZ-170

Rev. 0 | Page 3 of 44

AD9984A

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AD9984AKSTZ-140

Te st

1

Parameter Temp

POWER SUPPLY

VD Supply Voltage Full IV 1.7 1.8 1.9 1.755 1.8 1.9 V
VDD Supply Voltage Full IV 1.7 3.3 3.47 1.7 3.3 3.47 V
PVD Supply Voltage Full IV 1.7 1.8 1.9 1.7 1.8 1.9 V
DAVDD Supply Voltage Full IV 1.7 1.8 1.9 1.7 1.8 1.9 V
VD Supply Current (ID)

VDD Supply Current (IDD)
PVD Supply Current (IPVD)
DAVDD Supply Current (IDA
Total Power Dissipation Full VI 710 740 mW

Power-Down Supply Current Full VI 10 10 mA
Power-Down Dissipation Full VI 18 18 mW

DYNAMIC PERFORMANCE

Analog Bandwidth, Full Power 25°C V 300 300 MHz
Crosstalk Full V 60 60 dBc

1

See the Explanation of Test Levels section.

2

Guaranteed by design, not production tested.

VDD

25°C
25°C
25°C

)

25°C

Level

V 250 255 mA
V 31 34 mA
V 9 9 mA
V 16 19 mA

AD9984AKCPZ-140

Min Typ Max Min Typ Max Unit

AD9984AKSTZ-170
AD9984AKCPZ-170

Rev. 0 | Page 4 of 44

AD9984A

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ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

V

D

V

DD

PV

D

DAV

DD

Analog Inputs VD to 0.0 V
REFHI VD to 0.0 V
REFLO VD to 0.0 V
Digital Inputs 5 V to 0.0 V
Digital Output Current 20 mA
Operating Temperature Range −25°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
Maximum Case Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings

y cause permanent damage to the device. This is a stress

ma
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

1.98 V

3.6 V

1.98 V

1.98 V

EXPLANATION OF TEST LEVELS

I. 100% production tested.

II. 100% production tested at 25°C and sample tested at

sp

ecified temperatures.

III. Sample tested only.

IV. Parameter is guaranteed by design and characterization

sting.

te

V. Parameter is a typical value only.

VI. 100% production tested at 25°C; guaranteed by design

aracterization testing.

and ch

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θ

80-Lead LQFP 35 16
64-Lead LFCSP 35 16

JA

θ

JC

Unit

°C/W
°C/W

ESD CAUTION

Rev. 0 | Page 5 of 44

AD9984A

V

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

(1.8V)

D

B

AIN0

GND

B

AIN1

VD(1.8V)

G

AIN0

GND

SOGIN0

VD(1.8V)

G

AIN1

GND

SOGIN1

VD(1.8V)

R

AIN0

GND

R

AIN1

PWRDN

REFLO

NC

REFHI

(1.8V)

D

GND79PV

80

78

1

PIN 1

2

INDICATO R

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

O/E FIELD

VSOUT/A0

NC = NO CONNECT

(1.8V)

(1.8V)

D

FILT77GND76PV

24

HSOUT

SOGOUT

D

GND74PV

CLAMP72EXTCK/COAST71VSYNC070HSYNC069VSYNC168HSYNC167SCL66SDA65GND64V

75

73

AD9984A

TOP VIEW

(Not to Scale)

25

26

27

28

GND

(3.3V)

RED 929RED 830RED 731RED 632RED 533RED 434RED 335RED 236RED 137RED 0

DD

DATACK

V

Figure 2. 80-Lead LQFP Pin

Configuration

(3.3V)

DD

63

38

BLUE 062BLUE 161BLUE 2

39

GND40GND

(3.3V)

DD

V

60

BLUE 3

59

BLUE 4

58

BLUE 5

57

BLUE 6

56

BLUE 7

55

BLUE 8

54

BLUE 9

53

GND

52

VDD(3.3V)

51

GREEN 0

50

GREEN 1

49

GREEN 2

48

GREEN 3

47

GREEN 4

46

GREEN 5

45

GREEN 6

44

GREEN 7

43

GREEN 8

42

GREEN 9

41

DAVDD(1.8V)

06476-002

Rev. 0 | Page 6 of 44

AD9984A

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GREEN 9

GREEN 8

GREEN 7

GREEN 6

GREEN 5

GREEN 4

GREEN 3

GREEN 2

GREEN 1

GREEN 0

BLUE 9

BLUE 8

BLUE 7

BLUE 6

BLUE 5

BLUE 4

DD

DAV

64

1

PIN 1
INDICATO R

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

BLUE 3

RED 2

RED 1

RED 0

63 62 61 60 595857 56 55 54 535251 50

BLUE 2

RED 3

RED 4

RED 5

RED 6

RED 7

AD9984A

TOP VIEW

(Not to Scale)

DD

V

SCL

BLUE 1

SDA

BLUE 0

VSYNC1

HSYNC1

DD

RED 8

RED 9

V

DATACK

29

CLAMP

VSYNC0

HSYNC0

SOGOUT

PV

VSOUT/A0

HSOUT

49

48

O/E FIELD

REFHI

47

46

REFLO

45

PWRDN

44

R

AIN1

43

R

AIN0

42

V

D

41

SOGIN1

40

G

AIN1

39

V

D

38

SOGIN0

37

G

AIN0

V

36

D

35

B

AIN1

34

B

AIN0

33

V

D

3217 18 19 20 21 22 23 24 25 26 27 282930 31

D

D

PV

FILT

EXTCK/COAST

6476-020

Figure 3. 64-Lead LFCSP Pin Configuration

Table 4. Complete Pin Configuration List

Pin Number
Pin Type 80-Lead LQFP 64-Lead LFCSP Mnemonic Function Value

Inputs 14 43 R
16 44 R
6 37 G
10 40 G
2 34 BB
4 35 BB

AIN0

AIN1

AIN0

AIN1

AIN0

AIN1

Channel 0 Analog Input for Converter R 0.0 V to 1.0 V
Channel 1 Analog Input for Converter R 0.0 V to 1.0 V
Channel 0 Analog Input for Converter G 0.0 V to 1.0 V
Channel 1 Analog Input for Converter G 0.0 V to 1.0 V
Channel 0 Analog Input for Converter B 0.0 V to 1.0 V

Channel 1 Analog Input for Converter B 0.0 V to 1.0 V
70 26 HSYNC0 Horizontal Sync Input for Channel 0 3.3 V CMOS
68 24 HSYNC1 Horizontal Sync Input for Channel 1 3.3 V CMOS
71 27 VSYNC0 Vertical Sync Input for Channel 0 3.3 V CMOS
69 25 VSYNC1 Vertical Sync Input for Channel 1 3.3 V CMOS
8 38 SOGIN0 Input for Sync-on-Green Channel 0 0.0 V to 1.0 V
12 41 SOGIN1 Input for Sync-on-Green Channel 1 0.0 V to 1.0 V
72 28 EXTCK

1

External Clock Input 3.3 V CMOS
73 29 CLAMP External Clamp Input Signal 3.3 V CMOS
72 28 COAST

1

External PLL Coast Signal Input 3.3 V CMOS
17 45 PWRDN Power-Down Control 3.3 V CMOS

Rev. 0 | Page 7 of 44

AD9984A

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Pin Number
Pin Type 80-Lead LQFP 64-Lead LFCSP Mnemonic Function Value

Outputs 28 to 37 54 to 63 RED[9:0] Outputs of Converter R; Bit 9 is the MSB 3.3 V CMOS
42 to 51 1 to 10 GREEN[9:0] Outputs of Converter G; Bit 9 is the MSB 3.3 V CMOS
54 to 63 11 to 20 BLUE[9:0] Outputs of Converter B; Bit 9 is the MSB 3.3 V CMOS
25 52 DATACK Data Output Clock 3.3 V CMOS
23 50 HSOUT Hsync Output Clock (Phase-aligned with DATACK) 3.3 V CMOS
22 49 VSOUT
24 51 SOGOUT Sync-on-Green Slicer Output 3.3 V CMOS
21 48 O/E FIELD Odd/Even Field Output 3.3 V CMOS
References 78 31 FILT Connection for External Filter Components for Internal PLL
18 46 REFLO Connection for External Capacitor for Input Amplifier
20 47 REFHI Connection for External Capacitor for Input Amplifier
Power Supply 1, 5, 9, 13 33, 36, 39, 42 V
26, 38, 52, 64 21, 53 V
74, 76, 79 30, 32 PV
41 64 DAV

Control 66 22 SDA Serial Port Data I/O 3.3 V CMOS
67 23 SCL Serial Port Data Clock (100 kHz maximum) 3.3 V CMOS
22 49 A0

1

EXTCK and COAST share the same pin.

2

VSOUT and A0 share the same pin.

3, 7, 11, 15, 27,
39, 40, 53, 65,
75, 77, 80

N/A GND Ground 0 V

2

Vsync Output Clock 3.3 V CMOS

D

DD

D

DD

2

Analog Power Supply 1.8 V
Output Power Supply 1.8 V to 3.3 V
PLL Power Supply 1.8 V
Digital Logic Power Supply 1.8 V

Serial Port Address Input 3.3 V CMOS

Rev. 0 | Page 8 of 44

AD9984A

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Table 5. Pin Function Descriptions

Mnemonic Function Description

R

AIN0

G

AIN0

BB

AIN0

R

AIN1

G

AIN1

BB

AIN1

HSYNC0

HSYNC1

VSYNC0 Vertical Sync Input Channel 0
VSYNC1 Vertical Sync Input Channel 1

SOGIN0

SOGIN1

CLAMP

EXTCK/COAST External Clock (EXTCK)

PWRDN

REFLO, REFHI Input Amplifier Reference

Analog Input for the Red
Channel 0

Analog Input for the Green
Channel 0

Analog Input for the Blue
Channel 0

Analog Input for the Red
Channel 1

Analog Input for the Green
Channel 1

Analog Input for the Blue
Channel 1

Horizontal Sync Input

l 0

Channe
Horizontal Sync Input

l 1

Channe

Sync-on-Green Input

l 0

Channe
Sync-on-Green Input

l 1

Channe

External Clamp Input

ptional)

(O

Optional Coast Input to

enerator (COAST)

Clock G

Power-Down Control
(PWRDN

)

These high impedance inputs accept the red, green, and blue channel graphics signals,
r

espectively. The three channels are identical and can be used for any colors, but colors

are assigned for convenient reference. They accommodate input signals ranging from

0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp
operation. Refer to

These inputs receive a logic signal that establish
provides the frequency reference for pixel clock generation. The logic sense of these pins
can be automatically determined by the chip or manually controlled by Serial Register 0x12,
Bits[5:4] (Hsync polarity). Only the leading edge of Hsync is used by the PLL; the trailing
edge is used in clamp timing. When Hsync polarity = 0, the falling edge of Hsync is used.
When Hsync polarity = 1, the rising edge is active. These inputs include a Schmitt trigger
for noise immunity.

These inputs for vertical sync provide timing inf
(odd/even) and internal coast generation. The logic sense of this pin can be
automatically determined by the chip or manually controlled by Serial Register 0x14,
Bits[5:4] (Vsync polarity).

These inputs help process signals with embedded sync, typically on the green channel.
These pins conn
The threshold level can be programmed in 8 mV steps to any voltage between 8 mV and
256 mV above the negative peak of the input signal. The default voltage threshold is
128 mV. When connected to an ac-coupled graphics signal with embedded sync, a
noninverting digital output is produced on SOGOUT. This output is usually a composite
sync signal, containing both vertical and horizontal sync information that must be
separated before passing the horizontal sync signal for Hsync processing. When not
used, these inputs should be left unconnected. For more details about this function and
how it should be configured, refer to the Sync-on-Green section.

This logic input can be used to define the time during which the input signal is clamped
to ground or midscale. It should be exercised when the reference dc level is known to be
present on the analog input channels, typically during the back porch of the graphics
signal. The CLAMP pin is enabled by setting the control bit clamp function to 1, (Register 0x18,
Bit 4; default is 0). When disabled, this pin is ignored and the clamp timing is determined
internally by counting a delay and duration from the trailing edge of the Hsync input.
The logic sense of this pin can be automatically determined by the chip or controlled by
clamp polarity (Register 0x1B, Bits[7:6]). When not used, this pin can be left unconnected
(there is an internal pull-down resistor) and the clamp function programmed to 0.

This pin has dual functionality.

TCK allows the insertion of an external clock source rather than the internally

EX
generated, PLL locked clock. EXTCK is enabled by programming Register 0x03, Bit 2 to 1.
This EXTCK function does not affect the COAST function.

COAST can be used to cause the pixel clock generator to stop synchronizing with Hsync
and continue to produce a clock at its current frequency and phase. This is useful when
processing signals from sources that fail to produce Hsync pulses during the vertical
interval. The coast signal is generally not required for PC-generated signals. The logic
sense of this pin can be determined automatically or controlled by coast polarity
(Register 0x18, Bits[7:6]). When this function and the EXTCK function are not used, this
pin can be grounded and coast polarity programmed to 1. Input coast polarity defaults
to 1 at power-up. This COAST function does not affect the EXTCK function.

PWRDN allows for manual power-down control. If manual power-down control is selected
(Register 0x1E, Bit 4),and this pin is not used, it is recommended to set the pin polarity
(Register 0x1E, Bit 2) to active high and hardwire this pin to ground with a 10 kΩ resistor.

REFLO and REFHI are connected together through a 10 μF capacitor. These are used for

y in the input ADC circuitry. See Figure 6.

stabilit

Figure 4 and Figure 5.

es the horizontal timing reference and

ormation for generation of the field

ect to a high speed comparator with an internally generated threshold.

Rev. 0 | Page 9 of 44

AD9984A

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Mnemonic Function Description

FILT External Filter Connection

HSOUT Horizontal Sync Output

VSOUT/A0

SOGOUT Sync-On-Green Slicer Output

O/E FIELD

SDA Serial Port Data I/O Data I/O for the I2C® serial port.
SCL Serial Port Data Clock Clock for the I2C serial port.
RED[9:0] Data Output, Red Channel
GREEN[9:0] Data Output, Green Channel
BLUE[9:0] Data Output, Blue Channel

DATACK Data Clock Output

VD (1.8 V) Main Power Supply

VDD (1.8 V to 3.3 V) Digital Output Power Supply

PVD (1.8 V)

DAVDD (1.8 V) Digital Input Power Supply

GND Ground

Vertical Sync Output

SOUT)

(V

Serial Port Address Input 0

0)

(A

Odd/Even Field Bit for

terlaced Video

In

Clock Generator Power
Supply

For proper operation, the pixel clock generator PLL requires an external filter. Connect the
filter shown
on this node

This pin is a reconstructed and phase-aligned v
polarity and duration of this output can be programmed via serial bus registers. By
maintaining alignment with DATACK and the main data outputs (RED[9:0], GREEN[9:0],
BLUE[9:0]), data timing with respect to Hsync can always be determined.

This pin has dual functionality.
VSOUT can either be a separated Vsync from a composite signal or a direct pass through
of the Vsync signal. The polarity of this output can be controlled via a serial bus bit. The
placement and duration in all modes can be set by the graphics transmitter or the
duration can be set by Register 0x14, Bit 1 and Register 0x15, Bits[7:0]. This VSOUT function
does not affect the A0 function.

A0 selects the LSB of the serial port device address, allowing two parts from Analog
Devices, Inc., to be on the same serial bus. A high impedance (10 kΩ), external pull-up
resistor enables this pin to be read at power-up as 1. This A0 function does not interfere
with the VSOUT function. For more details on A0, see the description in the 2-Wire Serial
Co

ntrol Port section.

This pin outputs one of four possible signals (cont
SOGINx, raw HSYNCx, regenerated Hsync from the filter, or the filtered Hsync. See Figure 9

o view how this pin is connected. Other than slicing off SOG, the output from this pin

t
receives no additional processing on the AD9984A. Vsync separation is performed via the
sync separator.

This output identifies whether the current field (in an in

The main data outputs. Bit 9 is the MSB. The delay from pixel sampling time to output is
fixed. When the sampling time is changed by adjusting the phase register, the output
timing is shifted as well. The DATACK and HSOUT outputs are also moved to maintain the
timing relationship among the signals.

This is the main clock output signal used t
external logic. Four possible output clocks can be selected with Register 0x20, Bits[7:6].
Three of these are related to the pixel clock (pixel clock, 90° phase-shifted pixel clock,
and 2× frequency pixel clock). They are produced by the internal PLL clock generator or
by EXTCK, and are synchronous with the pixel sampling clock. The fourth option for the
data clock output is an internally generated 0.5× pixel clock. The sampling time of the
internal pixel clock can be changed by adjusting the phase register (Register 0x04).
When this is changed, the pixel-related DATACK timing is also shifted. The data (RED[9:0],
GREEN[9:0], BLUE[9:0]), DATACK, and HSOUT outputs are moved to maintain the timing
relationship among the signals.

These pins supply power to the main elements of the circuit. They should be as quiet
and as filt

A large number of output pins (up to 35) switchin
large amounts of power supply transients (noise). These supply pins are identified separately
from the V
into the sensitive analog circuitry. If the AD9984A is interfacing with lower voltage logic,
V

can be connected to a lower supply voltage (as low as 1.8 V) for compatibility.

DD

The most sensitive portion of the AD9984A is th
provide power to the clock PLL and help the user design for optimal performance. The
designer should provide quiet, noise-free power to these pins.

This supplies power to the digital logic. It is r
the V

The ground return for all on-chip circuitry. It is recommended that the AD9984A be
assembled on a

in Figure 8 to this pin. For optimal performance, minimize noise and parasitics

. For more information, see the PCB Layout Recommendations section.

ersion of the Hsync input. Both the

rolled by Register 0x1D, Bits[1:0]): raw

terlaced signal) is odd or even.

o strobe the output data and HSOUT into

ered as possible.

g at high speed (up to 170 MHz) generates

pins. As a result, special care must be taken to minimize output noise transferred

D

e clock generation circuitry. These pins

ecommended to connect this pin to

supply.

D

single solid ground plane with careful attention to ground current paths.

Rev. 0 | Page 10 of 44

AD9984A

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THEORY OF OPERATION

The AD9984A is a fully integrated solution for capturing and
digitizing analog RGB or YPbPr signals for display on advanced
TVs, flat panel monitors, projectors, and other types of digital
displays. Implemented in a high performance CMOS process,
the interface can capture signals with pixel rates up to 170 MHz.

The AD9984A includes all necessary input buffering, signal dc

estoration (clamping), offset and gain (brightness and contrast)

r
adjustment, pixel clock generation, sampling phase control, and
output data formatting. All controls are programmable via a
2-wire serial interface (I
analog functions makes system design straightforward and less
sensitive to the physical and electrical environment.

With a typical power dissipation of less than 900 mW and an

perating temperature range of 0°C to 70°C, the device requires

o
no special environmental considerations.

DIGITAL INPUTS

All digital inputs on the AD9984A operate to 3.3 V CMOS levels.
The following digital inputs are 5 V tolerant (that is, applying
5 V to them does not cause any damage): HSYNC0, HSYNC1,
VSYNC0, VSYNC1, SOGIN0, SOGIN1, SDA, SCL, and CLAMP.

ANALOG INPUT SIGNAL HANDLING

The AD9984A has six, high impedance, analog input pins for
the red, green, and blue channels. They accommodate signals
ranging from 0.5 V to 1.0 V p-p.

Signals are typically brought onto the interface board with a

VI-I connector, a 15-pin D connector, or RCA connectors.

D
The AD9984A should be located as close as possible to the
input connector. Signals should be routed using matched­impedance traces (normally 75 Ω) to the IC input pins.

At the input pins, the signal should be resistively terminated
(75 Ω

to the signal ground return) and capacitively coupled to
the AD9984A inputs through 47 nF capacitors. These capacitors
form part of the dc restoration circuit.

In an ideal world of perfectly matched impedances, the best
pe

rformance can be obtained with the widest possible signal
bandwidth. The wide bandwidth inputs of the AD9984A
(300 MHz) can track the input signal continuously as it moves
from one pixel level to the next and can digitize the pixel during
a long, flat pixel time. In many systems, however, there are
mismatches, reflections, and noise, which can result in excessive
ringing and distortion of the input waveform. This makes it
more difficult to establish a sampling phase that provides good
image quality. A small inductor in series with the input is shown
to be effective in rolling off the input bandwidth slightly and
providing a high quality signal over a wider range of conditions.
Using a high speed, signal chip, bead inductor (such as the
Fair-Rite 2508051217Z0) in the circuit shown in

rovides good results in most applications.

p

2

C). Full integration of these sensitive

Figure 4

RGB

INPUT

Figure 4. Analog Input Interface Circuit

47n

75Ω

R

AIN

G

AIN

B

AIN

06476-003

HSYNC AND VSYNC INPUTS

The interface also accepts Hsync and Vsync signals, which are
used to generate the pixel clock, clamp timing, and coast and
field information. These can be either a sync signal directly
from the graphics source, or a preprocessed TTL- or CMOS­level signal.

The Hsync input includes a Schmitt trigger buffer for immunity
t

o noise and signals with long rise times. In typical PC-based
graphic systems, the sync signals are simply TTL-level drivers
feeding unshielded wires into the monitor cable. As such, no
termination is required.

SERIAL CONTROL PORT

The serial control port is designed for 3.3 V logic; however, it is
tolerant of 5 V logic signals. Refer to the 2-Wire Serial Control

rt section for more information.

Po

OUTPUT SIGNAL HANDLING

The digital outputs operate from 1.8 V to 3.3 V (VDD).

CLAMPING

RGB Clamping

To properly digitize the incoming signal, the dc offset of the
input must be adjusted to fit the range of the on-board ADCs.

Most graphics systems produce RGB signals with black at
g

round and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
ground, black is at 300 mV, and white is at approximately 1.0 V.
Some common RGB line amplifier boxes use emitter-follower
buffers to split signals and increase drive capability. This
introduces a 700 mV dc offset to the signal, which must be
removed for proper capture by the AD9984A.

The key to clamping is to identify a portion (time) of the signal
w

hen the graphic system is known to be producing black. An
offset is then introduced that results in the ADC producing a
black output (Code 0x00) when the known black input is present.
The offset then remains in place when other signal levels are
processed, and the entire signal is shifted to eliminate offset errors.

In most PC graphics systems, black is transmitted between
a

ctive video lines. With CRT displays, when the electron beam
has completed writing a horizontal line on the screen (at the
right side), the beam is deflected quickly to the left side of the
screen (called horizontal retrace) and a black signal is provided
to prevent the beam from disturbing the image.

Rev. 0 | Page 11 of 44

AD9984A

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In systems with embedded sync, a blacker-than-black signal
(Hsync) is briefly produced to signal the CRT that it is time to
begin a retrace. Because the input is not at black level at this
time, it is important to avoid clamping during Hsync. Fortunately,
there is usually a period following Hsync (called the back porch)
where a good black reference is provided. This is the time when
clamping should be done.

The clamp timing can be established by simply exercising

he CLAMP pin at the appropriate time with clamp source

t
(Register 0x18, Bit 4) = 1. The polarity of this signal is set by
the clamp polarity bits (Register 0x1B, Bits[7:6]).

A simpler method of clamp timing employs the AD9984A
in

ternal clamp timing generator. The clamp placement register
(Register 0x19) is programmed with the number of pixel periods
that should pass after the trailing edge of Hsync before clamping
starts. A second register, clamp duration (Register 0x1A), sets
the duration of the clamp. These are both 8-bit values, providing
considerable flexibility in clamp generation. Although Hsync
duration can widely vary, the clamp timing is referenced to the
trailing edge of Hsync because the back porch (black reference)
always follows Hsync. An effective starting point for establishing
clamping is to set the clamp placement to 0x04 (providing 4 pixel
periods for the graphics signal to stabilize after sync) and set the
clamp duration to 0x28 (giving the clamp 40 pixel periods to
reestablish the black reference).

Clamping is accomplished by placing an appropriate charge on
t

he external input coupling capacitor. The value of this capacitor
affects the performance of the clamp. If it is too small, there is a
significant amplitude change during a horizontal line time
(between clamping intervals). If the capacitor is too large, it
takes a long time for the clamp to recover from a large change
in incoming signal offset. The recommended value (100 nF)
results in recovering from a step error of 100 mV to within 1 LSB
in 60 lines with a clamp duration of 20 pixel periods on a 85 Hz
XGA signal.

YPbPr Clamping

YPbPr graphic signals are slightly different from RGB signals in
that the dc reference level (black level in RGB signals) of color
difference signals is at the midpoint of the video signal rather than
at the bottom. The three inputs are composed of luminance (Y)
and color difference (Pb and Pr) signals. For color difference
signals, it is necessary to clamp to the midscale range of the
ADC range (512) rather than to the bottom of the ADC range (0),
while the Y channel is clamped to ground.

Clamping to midscale rather than ground can be accomplished

y setting the clamp select bits in the serial bus register. Each of

b
the three converters has its own selection bit to enable them to
be independently clamped to midscale or ground. These bits are
located in Register 0x18, Bits[3:1]. The midscale reference
voltage is internally generated for each converter.

GAIN AND OFFSET CONTROL

The AD9984A contains three programmable gain amplifiers
(PGAs), one for each of the three analog inputs. The range of
the PGA is sufficient to accommodate input signals with inputs
ranging from 0.5 V to 1.0 V full scale. The gain is set in three
9-bit registers, red gain (Register 0x05, Register 0x06), green
gain (Register 0x07, Register 0x08), and blue gain (Register 0x09,
Register 0x0A). For each register, a gain setting of 0d corresponds
to the highest gain, while a gain setting of 511d corresponds to
the lowest gain. Note that increasing the gain setting results in
an image with less contrast.

The offset control shifts the analog input, resulting in a change

brightness. Three 11-bit registers, red offset (Register 0x0B,

in
Register 0x0C), green offset (Register 0x0D, Register 0x0E),
and blue offset (Register 0x0F, Register 0x10) provide inde­pendent settings for each channel. Note that the function of
the offset register depends on whether auto-offset is enabled
(Register 0x1B, Bit 5).

If manual offset is used, nine bits of the offset registers (for the

ed channel, Register 0x0B, Bits[6:0] plus Register 0x0C, Bits[7:6])

r
control the absolute offset added to the channel. The offset control
provides ±255 LSBs of adjustment range, with 1 LSB of offset
corresponding to 1 LSB of output code.

Automatic Offset

In addition to the manual offset adjustment mode, the AD9984A
also includes circuitry to automatically calibrate the offset for
each channel. By monitoring the output of each ADC during
the back porch of the input signals, the AD9984A can self-adjust
to eliminate any offset errors in its own ADC channels and any
offset errors present on the incoming graphics or video signals.

To activate the auto-offset mode, set Register 0x1B, Bit 5 to 1. Next,
t

he target code registers (Register 0x0B through Register 0x10)
must be programmed. The values programmed into the target
code registers should be the output code desired from the
AD9984A during the back porch reference time.

For example, for RGB signals, all three registers are normally

rogrammed to Code 2, while for YPbPr signals, the green

p
(Y) channel is normally programmed to Code 2, and the blue
and red channels (Pb and Pr) are normally set to 512. The
target code registers have 11 bits per channel and are in twos
complement format. This allows any value between −1024 and
+1023 to be programmed. Although any value in this range can
be programmed, the AD9984A offset range may not be able to
reach every value. Intended target code values range from (but
are not limited to) −160 to −1 and +1 to +160 when ground
clamping, and 350 to 670 when midscale clamping. Note that a
target code of 0 is not valid.

Rev. 0 | Page 12 of 44

AD9984A

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Negative target codes are included to duplicate a feature that is
present with manual offset adjustment. The benefit that is
mimicked is the ability to easily adjust brightness on a display. By
setting the target code to a value that does not correspond to the
ideal ADC range, the end result is an image that is brighter or
darker. A target code higher than ideal results in a brighter image,
whereas a target code lower than ideal results in a darker image.

The ability to program a target code offers a large degree of

reedom and flexibility. Although all channels are set to either 1

f
or 512 in most cases, the flexibility to select other values makes
it possible to insert intentional skews between channels. It also
allows the ADC range to be skewed so that voltages outside of
the normal range can be digitized. For example, setting the
target code to 40 allows the sync tip, which is normally below
black level, to be digitized and evaluated.

The internal logic for the auto-offset circuit requires 16 data
cl

ock cycles to perform its function. This operation is executed
immediately after the clamping pulse. Therefore, it is important
to end the clamping pulse signal at least 16 data clock cycles
before active video. This is true whether using the AD9984A
internal clamp circuit or an external CLAMP signal. The auto­offset function can be programmed to run continuously or on a
one-time basis (see the
s

ection). In continuous mode, the update frequency can be

0x2C—Bit[4] Auto-Offset Hold

programmed (Register 0x1B, Bits[4:3]). Continuous operation
with updates every 192 Hsyncs is recommended.

Guidelines for basic auto-offset operation are shown in Tabl e 6
a

nd Tabl e 7.

Table 6. RGB Auto-Offset Register Settings

Register Value Comments

0x0B 0x00 Sets red target to 4.
0x0C 0x80 Must be written.
0x0D 0x00 Sets green target to 4.
0x0E 0x80 Must be written.
0x0F 0x00 Sets blue target to 4.
0x10 0x80 Must be written.
0x18, Bits[3:1] 000

0x1B, Bits[5:3] 110

Sets red, green, and blue channels to

ound clamp.

gr
Selects update rate to every 192

s and enables auto-offset.

clamp

Table 7. YPbPr Auto-Offset Register Settings

Register Value Comments

0x0B 0x40 Sets Pr (red) target to 512.
0x0C 0x00 Must be written.
0x0D 0x00 Sets Y (green) target to 4.
0x0E 0x80 Must be written.
0x0F 0x40 Sets Pb (blue) target to 512.
0x10 0x00 Must be written.
0x18, Bits[3:1] 101

0x1B, Bits[5:3] 110

Sets Pb, Pr to midscale clamp and Y to

ound clamp.

gr
Selects update rate to every 192

s and enables auto-offset.

clamp

Automatic Gain Matching

The AD9984A includes circuitry to match the gains between
the three channels to within 1% of each other. Matching the
gains of each channel is necessary to achieve good color balance
on a display. On products without this feature, gain matching is
achieved by writing software that evaluates the output of each
channel, calculates gain mismatches, and then writes values to
the gain registers of each channel to compensate. With the auto
gain matching function, this software routine is no longer needed.
To activate auto gain matching, set Register 0x3C, Bits[2:0] to 110.

Auto gain matching has similar timing requirements to auto
o

ffset. It requires 16 data clock cycles to perform its function,
starting immediately after the end of the clamp pulse. Unlike
auto offset, auto gain matching does not require that these
16 clock cycles occur during the back porch reference time,
although it is recommended. During auto gain matching
operation, the data outputs of the AD9984A are frozen (held at
the value they had just prior to operation). The auto gain
matching function can be programmed to run continuously or
on a one-time basis (see the

ld section). In continuous mode, the update frequency can

Ho

rogrammed (Register 0x1B, Bits[4:3]). Continuous

be p

0x3C—Bit[3] Auto Gain Matching

operation with updates every 192 Hsyncs is recommended.

SYNC-ON-GREEN

The sync-on-green inputs (SOGIN0, SOGIN1) operate in two
steps. First, they set a baseline clamp level off the incoming
video signal with a negative peak detector. Second, they set the
voltage level of the SOG slicer’s comparator (Register 0x1D,
Bits[7:3]) with a variable trigger level to a programmable level
(typically 128 mV) above the negative peak. Each sync-on­green input must be ac-coupled to the green analog input
through its own capacitor. The value of the capacitor must be
1 nF ± 20%. If sync-on-green is not used, this connection is not
required. The sync-on-green signal always has negative polarity.

47nF

R

47nF

47nF

1nF

Figure 5. Typical Input Configu

AIN

B

AIN

G

AIN

SOGIN

6476-004

ration

REFERENCE BYPASSING

REFLO and REFHI are connected to each other by a 10 μF
capacitor (see Figure 6). These references are used by the input

C circuitry.

AD

10µF

Figure 6. Input Amplifier Reference Capacitors

REFHI

REFLO

6476-005

Rev. 0 | Page 13 of 44

AD9984A

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CLOCK GENERATION

A PLL is used to generate the pixel clock. The Hsync input
provides a reference frequency to the PLL. A voltage controlled
oscillator (VCO) generates a much higher pixel clock frequency.
The pixel clock is divided by the PLL divide value (Register 0x01
and Register 0x02) and phase-compared with the Hsync input.
Any error is used to shift the VCO frequency and maintain lock
between the two signals.

The stability of this clock is a very important element in provid­i

ng the clearest and most stable image. During each pixel time,
the signal slews from the old pixel amplitude and settles at its
new value; this is called the slewing time. Then, the input voltage
stabilizes before the signal must slew to a new value; this is called
the stable time. The ratio of the slewing time to the stable time is
a function of the graphics DAC bandwidth and the bandwidth
of the transmission system (cable and termination). This ratio is
also a function of the overall pixel rate. If the dynamic charac­teristics of the system remain fixed, the slewing and settling
time is likewise fixed. This time must be subtracted from the
total pixel period, leaving the stable period. At higher pixel
frequencies, the total cycle time is shorter and the stable pixel
time becomes shorter as well.

PIXEL CLOC

INVALID SAMPLE TIMES

Four programmable registers are provided to optimize the
performance of the PLL. These registers are the 12-bit divisor
register, the 2-bit VCO range register, the 3-bit charge pump
current register, and the 5-bit phase adjust register.

The 12-Bit Divisor Register

The input Hsync frequencies can accommodate any Hsync as
long as the product of the Hsync and the PLL divisor falls
within the operating range of the VCO. The PLL multiplies the
frequency of the Hsync signal, producing pixel clock frequencies
in the range of 10 MHz to 170 MHz. The divisor register controls
the exact multiplication factor. This register can be set to any
value between 2 and 4095 as long as the output frequency is
within range.

The 2-Bit VCO Range Register

To improve the noise performance of the AD9984A, the VCO
operating frequency range is divided into four overlapping
regions. The VCO range register sets this operating range. The
frequency ranges for the four regions are shown in Tab le 8 .

Table 8. VCO Frequency Ranges

PV1 PV0 Pixel Clock Range (MHz) KVCO Gain (MHz/V)

0 0 10 to 31
0 1 31 to 62 150
1 0 62 to 124 150
1 1 124 to 170 150

1

For frequencies of 18 MHz or lower, enable the VCO low range bit (Reg. 0x36[0]).

1

150

The 3-Bit Charge Pump Current Register

This register varies the current that drives the low-pass loop
filter. The possible current values are listed in Table 9 .

6476-006

Figure 7. Pixel Sampling Times

Any jitter in the clock reduces the precision of the sampling
time and it must also be subtracted from the stable pixel time.
Considerable care has been taken in the design of the AD9984A
clock generation circuit to minimize jitter. The clock jitter of the
AD9984A is low in all operating modes, making the reduction
in the valid sampling time due to jitter negligible.

The PLL characteristics are determined by the loop filter design,
t

he PLL charge pump current, and the VCO range setting. The
loop filter design is illustrated in

f the VCO range and charge pump current for VESA standard

o

Figure 8. Recommended settings

display modes are listed in Tabl e 10.

PV

C

P

8.2n

FILT

Figure 8. PLL Loop Filter Design

1.5kΩ

C
82nF

R

Z

Z

D

06476-007

Rev. 0 | Page 14 of 44

Table 9. Charge Pump Current/Control Bits

Ip2 Ip1 Ip0 Current (μA)

0 0 0 50
0 0 1 100
0 1 0 150
0 1 1 250
1 0 0 350
1 0 1 500
1 1 0 750
1 1 1 1500

The 5-Bit Phase Adjust Register

The phase of the generated sampling clock can be shifted to
locate an optimum sampling point within a clock cycle. The
phase adjust register provides 32 phase-shift steps of 11.25°
each. The Hsync signal with an identical phase shift is available
through the HSOUT pin. Phase adjust is still available if an
external pixel clock is used. The COAST pin or the internal
coast is used to allow the PLL to continue to run at the same
frequency in the absence of the incoming Hsync signal or
during disturbances in Hsync (such as from equalization
pulses). This can be used during the vertical sync period or at
any other time that the Hsync signal is unavailable.