ANALOG DEVICES AD9983A Service Manual
High Performance
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FEATURES
8-bit analog-to-digital converters
140 MSPS maximum conversion rate
Low PLL clock jitter at 140 MSPS
Automatic gain matching
Automated offset adjustment
2:1 input mux
Power-down via dedicated pin or serial register
4:4:4, 4:2:2, and DDR output format modes
Variable output drive strength
Odd/even field detection
External clock input
Regenerated Hsync output
Programmable output high impedance control
Hsyncs per Vsync counter
Pb-free package
APPLICATIONS
Advanced TVs
Plasma display panels
LCDT V
HDTV
RGB graphics processing
LCD monitors and projectors
Scan converters
Pr/RED
Pr/RED
Y/GREEN
Y/GREEN
Pb/BLUE
Pb/BLUE
HSYNC1
HSYNC0
VSYNC0
VSYNC1
SOGIN1
SOGIN0
EXTCK/COAST
CLAMP
FILT
SDA
SCL
8-Bit Display Interface
FUNCTIONAL BLOCK DIAGRAM
IN1
IN0
IN1
IN0
IN1
IN0
AD9983A
2:1
MUX
2:1
MUX
2:1
MUX
2:1
MUX
2:1
MUX
2:1
MUX
SERIAL REGI STER
CLAMP
CLAMP
CLAMP
8
PGA
8
PGA
8
PGA
SYNC
PROCESSING
PLL
POWER
MANAGEMENT
Figure 1.
AUTO OFFS ET
AUTO GAIN
8-BIT
ADC
AUTO OFFS ET
AUTO GAIN
8-BIT
ADC
AUTO OFFS ET
AUTO GAIN
8-BIT
ADC
AD9983A
8
Cb/Cr/RED
8
Y/GREEN
OUTPUT DATA F ORMATTER
8
Cb/BLUE
DATACK
SOGOUT
O/E FIELD
HSOUT
VSOUT/A0
VOLTAGE
REFS
REFHI
REFLO
OUT
OUT
OUT
06475-001
GENERAL DESCRIPTION
The AD9983A is a complete 8-bit, 140 MSPS, monolithic
analog interface optimized for capturing YPbPr video and RGB
graphics signals. Its 140 MSPS encode rate capability and full
power analog bandwidth of 300 MHz support all HDTV video
modes up to 1080i and 720p as well as graphics resolutions up
to SXGA (1280 x 1024 at 75 Hz).
The AD9983A includes a 140 MHz triple ADC with an internal
r
eference, a PLL, and programmable gain, offset, and clamp
control. The user provides only a 1.8 V power supply and an
analog input. Three-state CMOS outputs can be powered from
1.8 V to 3.3 V.
The AD9983A on-chip PLL generates a sample clock from the
ri-level sync (for YPbPr video) or the horizontal sync (for RGB
t
graphics). Sample clock output frequencies range from 10 MHz
to 140 MHz. With internal coast generation, the PLL maintains
its output frequency in the absence of sync input. A 32-step
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
sampling clock phase adjustment is provided. Output data,
sync, and clock phase relationships are maintained.
The auto-offset feature can be enabled to automatically restore
e signal reference levels and to automatically calibrate out any
th
offset differences between the three channels. The auto channelto-channel gain matching feature can be enabled to minimize
any gain mismatches between the three channels.
The AD9983A also offers full sync processing for composite
nc and sync-on-green applications. A clamp signal is
sy
generated internally or may be provided by the user through the
CLAMP input pin.
Fabricated in an advanced CMOS process, the AD9983A is
p
rovided in a space-saving 80-lead, Pb-free, LQFP surfacemount plastic package, and is specified over the 0°C to 70°C
temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
AD9983A
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TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Analog Interface Characteristics................................................ 3
Absolute Maximum Ratings............................................................ 5
Explanation of Test Levels ........................................................... 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Theory of Operation ...................................................................... 10
Digital Inputs ..............................................................................10
Analog Input Signal Handling.................................................. 10
Hsync and Vsync Inputs............................................................ 10
Serial Control Port .....................................................................10
Output Signal Handling............................................................. 10
Clamping .....................................................................................10
Gain and Offset Control............................................................ 11
Sync-on-Green............................................................................ 12
Reference Bypassing................................................................... 12
Clock Generation ....................................................................... 13
Sync Processing........................................................................... 15
Power Management.................................................................... 18
Timing Diagrams........................................................................ 18
Hsync Timing .............................................................................19
Coast Timing............................................................................... 20
Output Formatter ....................................................................... 20
2-Wire Serial Control Port............................................................ 21
Data Transfer via Serial Interface............................................. 21
2-Wire Serial Register Map........................................................... 23
2-Wire Serial Control Registers.................................................... 29
Chip Identification..................................................................... 29
PLL Divider Control.................................................................. 29
Clock Generator Control .......................................................... 29
Phase Adjust................................................................................ 29
Input Gain................................................................................... 30
Input Offset................................................................................. 30
Hsync Controls........................................................................... 30
Vsync Controls........................................................................... 31
Coast and Clamp Controls........................................................ 32
SOG Control ............................................................................... 33
Input and Power Control........................................................... 34
Output Control........................................................................... 35
Sync Processing .......................................................................... 36
Detection Status.......................................................................... 36
Polarity Status ............................................................................. 37
Hsync Count............................................................................... 37
Test Registers............................................................................... 37
PCB Layout Recommendations.................................................... 39
Analog Interface Inputs............................................................. 39
Outputs (Both Data and Clocks).............................................. 40
Digital Inputs .............................................................................. 40
Outline Dimensions....................................................................... 41
Ordering Guide .......................................................................... 41
REVISION HISTORY
5/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 44
AD9983A
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SPECIFICATIONS
ANALOG INTERFACE CHARACTERISTICS
VD = 1.8 V, VDD = 3.3 V, PVD = 1.8 V, DAVDD = 1.8 V, ADC clock = maximum conversion rate, full temperature range = 0°C to 70°C.
Table 1.
Parameter Temperature Test Level1Min Typ Max Unit
RESOLUTION
Number of bits 8 Bits
LSB Size 0.391 % of Full Scale
DC ACCURACY
Differential Nonlinearity 25°C I ±0.25 ±0.85 LSB
Full VI ±0.3 LSB
Integral Nonlinearity 25°C I ±0.75 1.45/−2.60 LSB
Full VI ±1.0 LSB
No Missing Codes Full VI GNT
ANALOG INPUT
Input Voltage Range
Minimum Full VI 0.5 V p–p
Maximum Full VI 1.0 V p–p
Gain Tempco 25°C V 125 ppm/°C
Input Bias Current 25°C
Full
Input Full-Scale Matching Full VI 1 5 % FS
Offset Adjustment Range Full VI 50 % FS
SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 140 MSPS
Minimum Conversion Rate Full IV 10 MSPS
Clock to Data Skew t
t
Full VI 4.7 μs
BUFF
t
Full VI 4.0 μs
STAH
t
Full VI 0 μs
DHO
t
Full VI 4.7 μs
DAL
t
Full VI 4.0 μs
DAH
t
Full VI 250 ns
DSU
t
Full VI 4.7 μs
STASU
t
Full VI 4.0 μs
STOSU
Maximum PLL Clock Rate Full VI 140 MHz
Minimum PLL Clock Rate Full IV 10 MHz
2
Jitter
Full IV pS p-p
Sampling Phase Tempco Full IV 15 pS/°C
DIGITAL INPUTS
Input Voltage, High (VIH) Full VI 1.0 V
Input Voltage, Low (VIL) Full VI 0.8 V
Input Current, High (IIH) Full V −1.0 μA
Input Current, Low (IIL) Full V 1.0 μA
Input Capacitance
DIGITAL OUTPUTS
Output Voltage, High (VOH) Full VI VDD − 0.1 V
Output Voltage, Low (VOL) Full VI 0.1 V
Duty Cycle, DATACK Full IV 45 50 55 %
Output Coding Binary
Full IV −0.5 2.0 ns
SKEW
25°C
25°C
IV
IV
IV pS p
V 2 pF
1
μA
1
μA
-p
Rev. 0 | Page 3 of 44
AD9983A
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Parameter Temperature Test Level1Min Typ Max Unit
POWER SUPPLY
VD Supply Voltage Full IV 1.7 1.8 1.9 V
VDD Supply Voltage Full IV 1.7 3.3 3.47 V
PVD Supply Voltage Full IV 1.7 1.8 1.9 V
DA
Supply Voltage Full IV 1.7 1.8 1.9 V
VDD
VD Supply Current (ID)
VDD Supply Current (IDD)
PVD Supply Current (IPVD)
DAVDD Supply Current (IDAVDD)
Total Power Dissipation Full VI 800 mW
Power-Down Supply Current Full VI 10 mA
Power-Down Dissipation Full VI 18 mW
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power 25°C V 300 MHz
Crosstalk Full V 60 dBc
1
See the Explanation of Test Levels section.
2
Jitter measurements taken at SXGA with recommended PLL settings.
25°C
25°C
25°C
25°C
V 250 mA
V 31 mA
V 9 mA
V 16 mA
Rev. 0 | Page 4 of 44
AD9983A
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ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VD 1.98 V
VDD 3.6 V
PVD 1.98 V
DAVDD 1.98 V
Analog Inputs VD to 0.0 V
REFHI VD to 0.0 V
REFLO VD to 0.0 V
Digital Inputs 5 V to 0.0 V
Digital Output Current 20 mA
Operating Temperature −25°C to + 85°C
Storage Temperature −65°C to + 150°C
Maximum Junction Temperature 150°C
Maximum Case Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
y cause permanent damage to the device. This is a stress
ma
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
I. 100% production tested.
II. 100% p
III. Sample tested only.
IV. P
V. Parameter is a typical value only.
VI. 100% p
roduction tested at 25°C and sample tested at
specified temperatures.
arameter is guaranteed by design and characterization
testing.
roduction tested at 25°C; guaranteed by design and
characterization testing.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA θ
80-lead LQFP 35 16 °C/W
Unit
JC
ESD CAUTION
Rev. 0 | Page 5 of 44
AD9983A
V
V
V
V
T
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
(1.8V)
D
B
AIN0
GND
B
AIN1
(1.8V)
D
G
AIN0
GND
SOGIN0
(1.8V)
D
G
AIN1
GND
SOGIN1
(1.8V)
D
R
AIN0
GND
R
AIN1
PWRDN
REFLO
NC
REFHI
(1.8V)
GND79PV
80
1
PIN 1
2
INDICATO R
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
O/E FIELD
VSOUT/A0
(1.8V)
D
FILT77GND76PV
78
23
24
HSOUT
NC = NO CONNECT
(1.8V)
D
D
GND74PV
75
25
26
27
GND
(3.3V)
DATACK
DD
SOGOUT
V
Figure 2. 80-Lead LQFP Pin
CLAMP72EXTCK/COAS
VSYNC070HSYNC069VSYNC168HSYNC167SCL66SDA65GND64V
73
71
AD9983A
TOP VIEW
(Not to Scale)
28
RED 729RED 630RED 531RED 432RED 333RED 234RED 135RED 0
Configuration
(3.3V)
DD
36NC37NC38
63NC62NC61
39
GND40GND
(3.3V)
DD
V
BLUE 0
60
BLUE 1
59
BLUE 2
58
BLUE 3
57
BLUE 4
56
BLUE 5
55
BLUE 6
54
BLUE 7
53
GND
52
VDD (3.3V)
51
NC
50
NC
49
GREEN 0
48
GREEN 1
47
GREEN 2
46
GREEN 3
45
GREEN 4
44
GREEN 5
43
GREEN 6
42
GREEN 7
41
DAVDD (1.8V)
06475-002
Table 4. Complete Pinout List
Pin Type Pin Number Mnemonic Function Value
Inputs 14 R
16 R
6 G
10 G
2 B
4 B
Channel 0 Analog Input for Converter R 0.0 V to 1.0 V
AIN0
Channel 1 Analog Input for Converter R 0.0 V to 1.0 V
AIN1
Channel 0 Analog Input for Converter G 0.0 V to 1.0 V
AIN0
Channel 1 Analog Input for Converter G 0.0 V to 1.0 V
AIN1
Channel 0 Analog Input for Converter B 0.0 V to 1.0 V
AIN0
Channel 1 Analog Input for Converter B 0.0 V to 1.0 V
AIN1
70 HSYNC0 Horizontal Sync Input for Channel 0 3.3 V CMOS
68 HSYNC1 Horizontal Sync Input for Channel 1 3.3 V CMOS
71 VSYNC0 Vertical Sync Input for Channel 0 3.3 V CMOS
69 VSYNC1 Vertical Sync Input for Channel 1 3.3 V CMOS
8 SOGIN0 Input for Sync-on-Green Channel 0 0.0 V to 1.0 V
12 SOGIN1 Input for Sync-on-Green Channel 1 0.0 V to 1.0 V
72
1
EXTCK External Clock Input 3.3 V CMOS
73 CLAMP External Clamp Input Signal 3.3 V CMOS
72
1
COAST External PLL Coast Signal Input 3.3 V CMOS
17 PWRDN Power-Down Control 3.3 V CMOS
Rev. 0 | Page 6 of 44
AD9983A
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Pin Type Pin Number Mnemonic Function Value
Outputs 28 to 35 RED [7:0] Outputs of Converter R, Bit 9 is the MSB 3.3 V CMOS
42 to 49 GREEN [7:0] Outputs of Converter G, Bit 9 is the MSB 3.3 V CMOS
54 to 61 BLUE [7:0] Outputs of Converter B, Bit 9 is the MSB 3.3 V CMOS
25 DATACK Data Output Clock 3.3 V CMOS
23 HSOUT Hsync Output Clock (Phase-Aligned with DATACK) 3.3 V CMOS
22
24 SOGOUT Sync-on-Green Slicer Output 3.3 V CMOS
21 O/E FIELD Odd/Even Field Output 3.3 V CMOS
References 78 FILT
18 REFLO Connection for External Capacitor for Input Amplifier
20 REFHI Connection for External Capacitor for Input Amplifier
Power Supply 1, 5, 9, 13 VD Analog Power Supply 1.8 V
26, 38, 52, 64 VDD Output Power Supply 1.8 V or 3.3 V
74, 76, 79 PVD PLL Power Supply 1.8 V
41 DAVDD Digital Logic Power Supply 1.8 V
Control 66 SDA Serial Port Data I/O 3.3 V CMOS
67 SCL Serial Port Data Clock (100 kHz maximum) 3.3 V CMOS
22
1
EXTCK and COAST share the same pin.
2
VSOUT and A0 share the same pin.
2
3, 7, 11, 15, 39, 40, 53,
75, 77, 80
65,
2
VSOUT Vsync Output Clock 3.3 V CMOS
Connection for External Filter Components for Internal
PLL
GND Ground 0 V
A0 Serial Port Address Input 3.3 V CMOS
Rev. 0 | Page 7 of 44
AD9983A
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Table 5. Pin Function Descriptions
Mnemonic Function Description
R
AIN0
G
AIN0
B
AIN0
R
AIN1
G
AIN1
B
AIN1
HSYNC0
HSYNC1
VSYNC0 Vertical Sync Input Channel 0
VSYNC1 Vertical Sync Input Channel 1
SOGIN0
SOGIN1
CLAMP
EXTCK/COAST External Clock
PWRDN
Analog Input for the Red
l 0
Channe
Analog Input for the Green
l 0
Channe
Analog Input for the Blue
l 0
Channe
Analog Input for the Red
l 1
Channe
Analog Input for the Green
l 1
Channe
Analog Input for the Blue
l 1
Channe
Horizontal Sync Input
l 0
Channe
Horizontal Sync Input
l 1
Channe
Sync-on-Green Input
l 0
Channe
Sync-on-Green Input
l 1
Channe
External Clamp Input
ptional)
(O
Coast Input to Clock
enerator (Optional)
G
Power-Down Control
These are high impedance inputs that accept the red, green, and blue channel graphics
, respectively. The three channels are identical and can be used for any colors,
signals
but colors are assigned for convenient reference. They accommodate input signals
ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to
support clamp operation. See Figure 4 and Figure 5.
These inputs receive a logic signal that establish
provides the frequency reference for pixel clock generation. The logic sense of this pin
can be automatically determined by the chip or manually controlled by Serial Register
0x12, Bits[5:4] (Hsync polarity). Only the leading edge of Hsync is used by the PLL; the
trailing edge is used in clamp timing. When Hsync polarity = 0, the falling edge of
Hsync is used. When Hsync polarity = 1, the rising edge is active. The input includes a
Schmitt trigger for noise immunity.
These are the inputs for vertical sync and provide timing information for generation of
the fiel
d (odd/even) and internal Coast generation. The logic sense of this pin can be
automatically determined by the chip or manually controlled by Serial Register 0x14,
Bits[5:4] (Vsync polarity).
These inputs process signals with embedded sync, typically on the green channel. The
pin is c
onnected to a high speed comparator with an internally generated threshold.
The threshold level can be programmed in 8 mV steps to any voltage between 8 mV
and 256 mV above the negative peak of the input signal. The default voltage threshold
is 128 mV. When connected to an ac-coupled graphics signal with embedded sync, it
produces a noninverting digital output on SOGOUT. This is usually a composite sync
signal, containing both vertical and horizontal sync information that must be separated
before passing the horizontal sync signal for Hsync processing. When not used, this
input should be left unconnected. For more details on this function and how it should
be configured, refer to the Sync-on-Green section.
This logic input can be used to define the time during which the input signal is
clamped to ground or midscale. It should be exercised when the reference dc level is
known to be present on the analog input channels, typically during the back porch of
the graphics signal. The CLAMP pin is enabled by setting the control bit clamp function
to 1, (Register 0x18, Bit 4; default is 0). When disabled, this pin is ignored and the clamp
timing is determined internally by counting a delay and duration from the trailing edge
of the Hsync input. The logic sense of this pin can be automatically determined by the
chip or controlled by clamp polarity Register 0x1B, Bits[7:6]. When not used, this pin
may be left unconnected (there is an internal pull-down resistor) and the clamp
function programmed to 0.
EXTCK allows the insertion of an external clock sour
generated, PLL locked clock. EXTCK is enabled by programming Register 0x03, Bit 2 to 1.
This pin is shared with the Coast function, which does not affect EXTCK functionality.
COAST can be used to cause the pixel clock generator to stop synchronizing with Hsync
and continue producing a clock at its current frequency and phase. This is useful when
processing signals from sources that fail to produce Hsync pulses during the vertical
interval. The coast signal is generally not required for PC-generated signals. The logic
sense of this pin can be determined automatically or controlled by Coast polarity
(Register 0x18, Bits[7:6]). When not used and EXTCK not used, this pin may be grounded
and Coast polarity programmed to 1. Input Coast polarity defaults to1 at power-up. This
pin is shared with the EXTCK function, which does not affect coast functionality. For
more details on EXTCK, see the description in this section.
This pin can be used along with Register 0x1E, Bit 3 for manual power-down control.
If manual power-down control is selected (Register 0x1E, Bit 4) and this pin is not used,
it is recommended to set the pin polarity (Register 0x1E, Bit 2) to active high and
hardwire this pin to ground with a 10 kΩ resistor.
Rev. 0 | Page 8 of 44
es the horizontal timing reference and
ce rather than the internally
AD9983A
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Mnemonic Function Description
REFLO, REFHI Input Amplifier Reference
FILT External Filter Connection
HSOUT Horizontal Sync Output
VSOUT/A0 Vertical Sync Output
Serial Port Address Input 0
SOGOUT
O/E FIELD
SDA Serial Port Data I/O Data I/O for the I2C® serial port.
SCL Serial Port Data Clock Clock for the I2C serial port.
RED [7:0] Data Output, Red Channel
GREEN [7:0] Data Output, Green Channel
BLUE [7:0] Data Output, Blue Channel
DATACK Data Clock Output
VD (1.8 V) Main Power Supply
VDD (1.8 V to 3.3 V) Digital Output Power Supply
PVD (1.8 V)
DAVDD (1.8 V) Digital Input Power Supply This supplies power to the digital logic.
GND Ground
Sync-On-Green Slicer
utput
O
Odd/Even Field Bit for
terlaced Video
In
Clock Generator Power
Supply
REFLO and REFHI are connected together through a 10 μF capacitor. These are used for
y in the input ADC circuitry. See Figure 6.
stabilit
For proper operation, the pixel clock generator PLL requires an external filter. Connect the
filter sho
on th
A reconstructed and phase-aligned version of the Hsync input. Both the polarit
duration of this output can be programmed via serial bus registers. By maintaining
alignment with DATACK and Data, data timing with respect to Hsync can always be
determined.
Pin shared with A0, serial port address. This can be either a separated Vsync from a
c
be controlled via a serial bus bit. The placement and duration in all modes can be set by the
graphics transmitter or the duration can be set by Register 0x14 and Register 0x15. This pin
is shared with the A0 function, which does not affect Vsync Output functionality. For more
details on A0, see the description in the Serial Control Port section.
Pin shared with VSOUT. This pin selects the LSB of the serial port device address,
allowing t
external pull-up resistor enables this pin to be read at power-up as 1, or a high
impedance, external pull-down resistor enables this pin to be read at power-up as a 0
and not interfere with the VSOUT functionality.
This pin outputs one of four possible signals (controlled by Register 0x1D, Bits[1:0]): raw
SOG, raw Hsync, regenerated Hsync from the filter, or the filtered Hsync. See Figure 8 to
view how this pi
gets no additional processing on the AD9983A. Vsync separation is performed via the
sync separator.
This output will identify whether the current field (in an interlaced signal) is odd or even.
The main data outputs. Bit 9 is the MSB. The delay from pixel sampling time to output is
fixed. When the sampling time is changed by adjusting the phase register, the output
timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing
relationship among the signals is maintained.
This is the main clock output signal used t
external logic. Four possible output clocks can be selected with Register 0x20, Bits[7:6].
Three of these are related to the pixel clock (pixel clock, 90° phase-shifted pixel clock
and 2× frequency pixel clock). They are produced either by the internal PLL clock
generator or EXTCK and are synchronous with the pixel sampling clock. The fourth
option for the data clock output is an internally generated 1⁄2x pixel clock.
The sampling time of the internal pixel clock can be changed by adjusting the phase
register (Register 0x04). When this is changed, the pixel related DATACK timing is also
shifted. The data, DATACK, and HSOUT outputs are all moved so that the timing
relationship among the signals is maintained.
These pins supply power to the main elements of the circuit. They should be as quiet
and
A large number of output pins (up to 29) switching at high speed (up to 140 MHz)
genera
separately from the V
transferred into the sensitive analog circuitry. If the AD9983A is interfacing with lower
voltage logic, V
compatibility.
The most sensitive portion of the AD9983A is th
provide power to the clock PLL and help the user design for optimal performance. The
designer should provide quiet, noise-free power to these pins.
The ground return for all circuitry on-chip. I
assembled on a single solid ground plane, with careful attention to ground current paths.
wn in Figure 6 to this pin. For optimal performance, minimize noise and parasitics
is node. For more information, see the PCB Layout Recommendations section.
y and
omposite signal or a direct pass through of the Vsync signal. The polarity of this output can
wo Analog Devices parts to be on the same serial bus. A high impedance
n is connected. Other than slicing off SOG, the output from this pin
o strobe the output data and HSOUT into
filtered as possible.
tes a lot of power supply transients (noise). These supply pins are identified
pins, so special care can be taken to minimize output noise
D
can be connected to a lower supply voltage (as low as 1.8 V) for
DD
e clock generation circuitry. These pins
t is recommended that the AD9983A be
Rev. 0 | Page 9 of 44
AD9983A
F
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THEORY OF OPERATION
The AD9983A is a fully integrated solution for capturing analog
RGB or YPbPr signals and digitizing them for display on
advanced TVs, flat panel monitors, projectors, and other types
of digital displays. Implemented in a high performance CMOS
process, the interface can capture signals with pixel rates of up
to 140 MHz.
The AD9983A includes all necessary input buffering, signal dc
r
estoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control, and
output data formatting. All controls are programmable via a
2-wire serial interface (I
analog functions makes system design straightforward and less
sensitive to the physical and electrical environment.
With a typical power dissipation of less than 800 mW and an
perating temperature range of 0°C to 70°C, the device requires
o
no special environmental considerations.
DIGITAL INPUTS
All digital inputs on the AD9983A operate to 3.3 V CMOS
levels. The following digital inputs are 5 V tolerant (that is, applying
5 V to them does not cause any damage.): HSYNC0, HSYNC1,
VSYNC0, VSYNC1, SOGIN0, SOGIN1, SDA, SCL and CLAMP.
ANALOG INPUT SIGNAL HANDLING
The AD9983A has six high impedance analog input pins for the
red, green, and blue channels. They accommodate signals
ranging from 0.5 V to 1.0 V p-p.
Signals are typically brought onto the interface board with a
VI-I connector, a 15-pin D connector, or RCA connectors.
D
The AD9983A should be located as close as possible to the
input connector. Signals should be routed using matchedimpedance traces (normally 75 Ω) to the IC input pins.
At the input pins the signal should be resistively terminated
to the signal ground return) and capacitively coupled to
(75 Ω
the AD9983A inputs through 47 nF capacitors. These capacitors
form part of the dc restoration circuit.
In an ideal world of perfectly matched impedances, the best
pe
rformance can be obtained with the widest possible signal
bandwidth. The wide bandwidth inputs of the AD9983A
(300 MHz) can track the input signal continuously as it moves
from one pixel level to the next and can digitize the pixel during
a long, flat pixel time. In many systems, however, there are
mismatches, reflections, and noise, which can result in excessive
ringing and distortion of the input waveform. This makes it
more difficult to establish a sampling phase that provides good
image quality. A small inductor in series with the input is
effective in rolling off the input bandwidth slightly and
providing a high quality signal over a wider range of conditions.
Using a Fair-Rite #2508051217Z0-High Speed, Signal Chip
Bead Inductor in the circuit shown in
esults in most applications.
r
2
C). Full integration of these sensitive
Figure 3 provides good
RGB
INPUT
Figure 3. Analog Input Interface Circuit
47n
75Ω
R
AIN
G
AIN
B
AIN
06475-003
HSYNC AND VSYNC INPUTS
The interface also accepts Hsync and Vsync signals, which are
used to generate the pixel clock, clamp timing, coast and field
information. These can be either a sync signal directly from the
graphics source, or a preprocessed TTL- or CMOS-level signal.
The Hsync input includes a Schmitt trigger buffer for immunity
o noise and signals with long rise times. In typical PC-based
t
graphic systems, the sync signals are simply TTL-level drivers
feeding unshielded wires in the monitor cable. As such, no
termination is required.
SERIAL CONTROL PORT
The serial control port is designed for 3.3 V logic; however, it is
tolerant of 5 V logic signals. Refer to the 2-Wire Serial Control
rt section.
Po
OUTPUT SIGNAL HANDLING
The digital outputs operate from 1.8 V to 3.3 V (VDD).
CLAMPING
RGB Clamping
To properly digitize the incoming signal, the dc offset of the
input must be adjusted to fit the range of the on-board ADCs.
Most graphics systems produce RGB signals with black at
g
round and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
ground, black is at 300 mV, and white is at approximately 1.0 V.
Some common RGB line amplifier boxes use emitter-follower
buffers to split signals and increase drive capability. This
introduces a 700 mV dc offset to the signal, which must be
removed for proper capture by the AD9983A.
The key to clamping is to identify a portion (time) of the signal
w
hen the graphic system is known to be producing black. An
offset is then introduced that results in the ADC producing a
black output (Code 0x00) when the known black input is
present. The offset then remains in place when other signal
levels are processed, and the entire signal is shifted to eliminate
offset errors.
Rev. 0 | Page 10 of 44
AD9983A
www.BDTIC.com/IC
In most PC graphics systems, black is transmitted between
active video lines. With CRT displays, when the electron beam
has completed writing a horizontal line on the screen (at the
right side), the beam is deflected quickly to the left side of the
screen (called horizontal retrace) and a black signal is provided
to prevent the beam from disturbing the image.
In systems with embedded sync, a blacker-than-black signal
(H
sync) is produced briefly to signal the CRT that it is time to
begin a retrace. Because the input is not at black level at this
time, it is important to avoid clamping during Hsync. Fortunately, there is usually a period following Hsync, called the back
porch, where a good black reference is provided. This is the
time when clamping should be done.
The clamp timing can be established by simply exercising the
LAMP pin at the appropriate time with clamp source
C
(Register 0x18, Bit 4) = 1. The polarity of this signal is set by
the clamp polarity bit, (Register 0x1B, Bits[7:6]).
A simpler method of clamp timing employs the AD9983A
ternal clamp timing generator. The clamp placement register
in
(Register 0x19) is programmed with the number of pixel
periods that should pass after the trailing edge of Hsync
before clamping starts. A second register, clamp duration,
(Register 0x1A) sets the duration of the clamp. These are both
8-bit values, providing considerable flexibility in clamp
generation. The clamp timing is referenced to the trailing edge
of Hsync because, though Hsync duration can vary widely, the
back porch (black reference) always follows Hsync. A good
starting point for establishing clamping is to set the clamp
placement to 0x04 (providing 4 pixel periods for the graphics
signal to stabilize after sync) and set the clamp duration to
0x28 (giving the clamp 40 pixel periods to reestablish the
black reference).
Clamping is accomplished by placing an appropriate charge on
he external input coupling capacitor. The value of this
t
capacitor affects the performance of the clamp. If it is too small,
there will be a significant amplitude change during a horizontal
line time (between clamping intervals). If the capacitor is too
large, it will take too long for the clamp to recover from a large
change in incoming signal offset. The recommended value
(47 nF) results in recovering from a step error of 100 mV to
within 1 LSB in 30 lines with a clamp duration of 20 pixel
periods on a 85 Hz XGA signal.
YPbPr Clamping
YPbPr graphic signals are slightly different from RGB signals in
that the dc reference level (black level in RGB signals) of color
difference signals is at the midpoint of the video signal rather
than at the bottom. The three inputs are composed of
luminance (Y) and color difference (Pb and Pr) signals. For
color difference signals, it is necessary to clamp to the midscale
range of the ADC range (512) rather than to the bottom of the
ADC range (0), while the Y channel is clamped to ground.
Clamping to midscale rather than ground can be accomplished
b
y setting the clamp select bits in the serial bus register. Each of
the three converters has its own selection bit so that they can be
clamped to either midscale or ground independently. These bits
are located in Register 0x18, Bits[3:1]. The midscale reference
voltage is internally generated for each converter.
GAIN AND OFFSET CONTROL
The AD9983A contains three PGAs, one for each of the three
analog inputs. The range of the PGA is sufficient to accommodate input signals with inputs ranging from 0.5 V to 1.0 V
full scale. The gain is set in three 7-bit registers (red gain [0x05],
green gain [0x07], blue gain [0x09]). For each register, a gain
setting of 0 corresponds to the highest gain, while a gain setting
of 127 corresponds to the lowest gain. Note that increasing the
gain setting results in an image with less contrast.
The offset control shifts the analog input, resulting in a change
brightness. Three 9-bit registers red offset [Register 0x0B and
in
Register 0x0C], green offset [Register 0x0D and Register 0x0E],
and blue offset [Register 0x0F and Register 0x10] provide
independent settings for each channel. Note that the function of
the offset register depends on whether auto-offset is enabled
(Register 0x1B, Bit 5).
If manual offset is used, seven bits of the offset registers (for the
ed channel Register 0x0B, Bits[6:0]) control the absolute offset
r
added to the channel. The offset control provides ±63 LSBs of
adjustment range, with 1 LSB of offset corresponding to 1 LSB
of output code.
Automatic Offset
In addition to the manual offset adjustment mode, the
AD9983A also includes circuitry to automatically calibrate the
offset for each channel. By monitoring the output of each ADC
during the back porch of the input signals, the AD9983A can
self-adjust to eliminate any offset errors in its own ADC
channels and any offset errors present on the incoming graphics
or video signals.
To activate the auto-offset mode, set Register 0x1B, Bit 5 to 1.
N
ext, the target code registers (Register 0x0B through
Register 0x10) must be programmed. The values programmed
into the target code registers should be the output code desired
from the AD9983A ADCs, which are generated during the back
porch reference time. For example, for RGB signals, all three
registers are normally programmed to Code 2, while for YPbPr
signals the green (Y) channel is normally programmed to Code 2
and the blue and red channels (Pb and Pr) are normally set to
128. The target code registers have nine bits per channel and are
in twos complement format. This allows any value between –256
and +255 to be programmed. Although any value in this range
can be programmed, the AD9983A offset range may not be able
to reach every value. Intended target code values range from
(but are not limited to) –40 to –1 and 1 to 40 when ground
clamping and 88 to 168 when midscale clamping. Note that a
target code of 0 is not valid.
Rev. 0 | Page 11 of 44
AD9983A
www.BDTIC.com/IC
Negative target codes are included in order to duplicate a feature that is present with manual offset adjustment. The benefit
that is being mimicked is the ability to easily adjust brightness
on a display. By setting the target code to a value that does not
correspond to the ideal ADC range, the end result is an image
that is either brighter or darker. A target code higher than ideal
results in a brighter image. A target code lower than ideal
results in a darker image.
The ability to program a target code gives a large degree of
f
reedom and flexibility. In most cases all channels are set to
either 1 or 128, but the flexibility to select other values allows
for the possibility of inserting intentional skews between
channels. It also allows the ADC range to be skewed so that
voltages outside of the normal range can be digitized. For
example, setting the target code to 40 allows the sync tip, which
is normally below black level, to be digitized and evaluated.
The internal logic for the auto-offset circuit requires 16 data
cl
ock cycles to perform its function. This operation is executed
immediately after the clamping pulse. Therefore, it is important
to end the clamping pulse signal at least 16 data clock cycles
before active video. This is true whether using the AD9983A
internal clamp circuit or an external clamp signal. The autooffset function can be programmed to run continuously or on a
one-time basis (see auto-offset hold, Register 0x2C, Bit 4). In
continuous mode, the update frequency can be programmed
(Register 0x1B, Bits[4:3]). Continuous operation with updates
every 64 Hsyncs is recommended.
A guideline for basic auto-offset operation is shown in
a
nd Tabl e 7 .
Tabl e 6
Table 6. RGB Auto-Offset Register Settings
Register Value Comments
0x0B 0x02 Sets red target to 4
0x0C 0x00 Must be written
0x0D 0x02 Sets green target to 4
0x0E 0x00 Must be written
0x0F 0x02 Sets blue target to 4
0x10 0x00 Must be written
0x18, Bits[3:1] 000
0x1B, Bits[5:3] 110
Sets red, green, and blue
ls to ground clamp
channe
Selects update rate and
es auto-offset.
enabl
Table 7. PbPr Auto-Offset Register Settings
Register Value Comments
0x0B 0x40 Sets Pr (red) target to 128
0x0C 0x00 Must be written
0x0D 0x02 Sets Y (green) target to 4
0x0E 0x00 Must be written
0x0F 0x40 Sets Pb (blue) target to 128
0x10 0x00 Must be written
0x18 Bits[3:1] 101
0x1B, Bits[5:3] 110
Sets Pb, Pr to midscale clamp
Y to ground clamp
and
Selects update rate and
es auto-offset
enabl
Rev. 0 | Page 12 of 44
Automatic Gain Matching
The AD9983A includes circuitry to match the gains between
the three channels to within 1% of each other. Matching the
gains of each channel is necessary in order to achieve good
color balance on a display. On products without this feature,
gain matching is achieved by writing software that evaluates the
output of each channel, calculates gain mismatches, then writes
values to the gain registers of each channel to compensate. With
the auto gain matching function, this software routine is no
longer needed. To activate auto gain matching, set Register 0x3C,
Bit 2 to Bit 1.
Auto gain matching has similar timing requirements to auto
ffset. It requires 16 data clock cycles to perform its function,
o
starting immediately after the end of the clamp pulse. Unlike
auto offset it does not require that these 16 clock cycles occur
during the back porch reference time, although that is what is
recommended. During auto gain matching operation, the data
outputs of the AD9983A are frozen (held at the value they had
just prior to operation). The auto gain matching function can be
programmed to run continuously or on a one-time basis (see
the
0x3C—Bit[3] Auto Gain Matching Hold section).
SYNC-ON-GREEN
The sync-on-green inputs (SOGIN0, SOGIN1) operate in two
steps. First, they set a baseline clamp level off of the incoming
video signal with a negative peak detector. Second, they set the
sync trigger level to a programmable (Register 0x1D, Bits[7:3])
level (typically 128 mV) above the negative peak. The sync-ongreen inputs must be ac-coupled to the green analog input
through their own capacitors. The value of the capacitors must
be 1 nF ±20%. If sync-on-green is not used, this connection is
not required. The sync-on-green signal always has negative
polarity.
47nF
R
1nF
AIN
B
AIN
G
AIN
SOGIN
06475-004
ration
47nF
47nF
Figure 4. Typical Input Configu
REFERENCE BYPASSING
REFLO and REFHI are connected to each other by a 10 μF
capacitor. These references are used by the input ADC circuitry.
10µF
Figure 5. Input Amplifier Reference Capacitors
REFHI
REFLO
06475-014
AD9983A
K
8
F
www.BDTIC.com/IC
CLOCK GENERATION
A PLL is used to generate the pixel clock. The Hsync input provides a reference frequency to the PLL. A voltage controlled
oscillator (VCO) generates a much higher pixel clock frequency.
The pixel clock is divided by the PLL divide value (Register 0x01
and Register 0x02) and phase-compared with the Hsync input.
Any error is used to shift the VCO frequency and maintain lock
between the two signals.
The stability of this clock is a very important element in
p
roviding the clearest and most stable image. During each pixel
time, there is a period during which the signal slews from the
old pixel amplitude and settles at its new value. Then there is a
time when the input voltage is stable, before the signal must
slew to a new value (see
o the stable time is a function of the bandwidth of the graphics
t
DAC and the bandwidth of the transmission system (cable and
termination). It is also a function of the overall pixel rate.
Clearly, if the dynamic characteristics of the system remain
fixed, then the slewing and settling time is likewise fixed. This
time must be subtracted from the total pixel period, leaving the
stable period. At higher pixel frequencies, the total cycle time is
shorter and the stable pixel time also becomes shorter.
PIXEL CLOC
Figure 6). The ratio of the slewing time
INVALID SAMPLE TIMES
Four programmable registers are provided to optimize the
performance of the PLL. These registers are the 12-Bit Divisor
Register, the 2-Bit VCO Range Register, the 3-Bit Charge Pump
Current Register, and the 5-Bit Phase Adjust Register.
The 12-Bit Divisor Register
The input Hsync frequencies can accommodate any Hsync as
lo
ng as the product of the Hsync and the PLL divisor falls
within the operating range of the VCO. The PLL multiplies the
frequency of the Hsync signal, producing pixel clock
frequencies in the range of 10 MHz to 140 MHz. The divisor
register controls the exact multiplication factor. This register
may be set to any value between 2 and 4095 as long as the
output frequency is within range.
The 2-Bit VCO Range Register
To improve the noise performance of the AD9983A, the VCO
perating frequency range is divided into four overlapping
o
regions. The VCO range register sets this operating range. The
frequency ranges for the four regions are shown in Tab le 8 .
Table 8. VCO Frequency Ranges
Pixel Clock
R
PV1 PV0
0 0 10 to 21 150
0 1 21 to 42 150
1 0 42 to 84 150
1 1 84 to 140 150
ange (MHz)
KVCO
Gain (MHz/V)
The 3-Bit Charge Pump Current Register
This register varies the current that drives the low pass loop
f
ilter. The possible current values are listed in Tab le 9 .
6475-005
Figure 6. Pixel Sampling Times
Any jitter in the clock reduces the precision with which the
sampling time can be determined and must also be subtracted
from the stable pixel time. Considerable care has been taken in
the design of the AD9983A clock generation circuit to
minimize jitter. The clock jitter of the AD9983A is low in all
operating modes, making the reduction in the valid sampling
time due to jitter negligible.
The PLL characteristics are determined by the loop filter design,
he PLL charge pump current, and the VCO range setting. The
t
loop filter design is shown in Figure 7. Recommended settings
o
f the VCO range and charge pump current for VESA standard
display modes are listed in
C
P
.2n
Tabl e 10.
C
Z
82nF
R
Z
1.5kΩ
FILT
Figure 7. PLL Loop Filter Detail
PV
D
06475-006
Table 9. Charge Pump Current/Control Bits
Ip2 Ip1 Ip0 Current (μA)
0 0 0 50
0 0 1 100
0 1 0 150
0 1 1 250
1 0 0 350
1 0 1 500
1 1 0 750
1 1 1 1500
The 5-Bit Phase Adjust Register
The phase of the generated sampling clock can be shifted to
lo
cate an optimum sampling point within a clock cycle. The
phase adjust register provides 32 phase-shift steps of 11.25°
each. The Hsync signal with an identical phase shift is available
through the HSOUT pin. Phase adjust is still available if an
external pixel clock is used. The COAST pin or the internal
coast is used to allow the PLL to continue to run at the same
frequency in the absence of the incoming Hsync signal or
during disturbances in Hsync (such as from equalization
pulses). This can be used during the vertical sync period or at
any other time that the Hsync signal is unavailable.
Rev. 0 | Page 13 of 44
AD9983A
www.BDTIC.com/IC
The polarity of the coast signal may be set through the coast
polarity register (Register 0x18, Bits[6:5]). Also, the polarity of
the Hsync signal can be set through the Hsync polarity register
(Register 0x12, Bits[5:4]). For both Hsync and coast, a value of 1
Table 10. Recommended VCO Range and Charge Pump and Current Settings for Standard Display Formats
Refresh Rate
Standard Resolution
VGA 640 × 480 60 31.500 25.175 800 00 101 0
72 37.700 31.500 832 01 100 0
75 37.500 31.500 840 01 100 0
85 43.300 36.000 832 01 100 0
SVGA 800 × 600 56 35.100 36.000 1024 01 100 0
60 37.900 40.000 1056 01 101 0
72 48.100 50.000 1040 01 101 0
75 46.900 49.500 1056 01 101 0
85 53.700 56.250 1048 01 110 0
XGA 1024 × 768 60 48.400 65.000 1344 10 100 0
70 56.500 75.000 1328 10 101 0
75 60.000 78.750 1312 10 101 0
80 64.000 85.500 1336 10 101 0
85 68.300 94.500 1376 10 110 0
SXGA 1280 × 1024 60 64.000 108.000 1688 10 110 0
75 80.000 135.000 1688 11 110 0
TV 480i 30 15.750 13.510 858 00 101 1
480p 60 31.470 27.000 858 00 101 0
576i 30 15.625 13.500 864 00 101 1
576p 60 31.250 27.000 864 00 101 0
720p 60 45.000 74.250 1650 10 101 0
1035i 30 33.750 74.250 2200 10 101 0
1080i 60 33.750 74.250 2200 10 101 0
(Hz)
Horizontal
F
requency (kHz) Pixel Rate (MHz) PLL Divider
is active high. The internal coast function is driven off the
Vsync signal, which is typically a time when Hsync signals may
be disrupted with extra equalization pulses.
VCO
Range Current
VCO Gear
(R0x36[0])
Rev. 0 | Page 14 of 44
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