ANALOG DEVICES AD9974 Service Manual

Dual-Channel, 14-Bit, CCD Signal

A

A

Processor with Precision Timing Core

FEATURES

1.8 V analog and digital core supply voltage
Correlated double sampler (CDS) with

−3 dB, 0 dB, +3 dB, and +6 dB gain
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)
14-bit, 65 MHz analog-to-digital converter (ADC)
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with 240 ps resolution @ 65 MHz
On-chip 3 V horizontal and RG drivers
100-lead, 9 mm × 9 mm, 0.8 mm pitch, CSP_BGA package
Internal low dropout (LDO) regulator circuitry

APPLICATIONS

Professional HDTV camcorders
Professional/high end digital cameras
Broadcast cameras
Industrial high speed cameras

AD9974

GENERAL DESCRIPTION

The AD9974 is a highly integrated, dual-channel, charge­coupled device (CCD) signal processor for high speed digital
video camera applications. Each channel is specified at pixel
rates of up to 65 MHz. The AD9974 consists of a complete
analog front end (AFE) with analog-to-digital conversion,
combined with a programmable timing driver. The Precision
Timi ng™ core allows adjustment of high speed clocks with
approximately 240 ps resolution at 65 MHz operation.

Each AFE includes black level clamping, CDS, VGA, and
a 65 MSPS, 14-bit ADC. The timing driver provides the high
speed CCD clock drivers for the RG_A, RG_B, H1_A to H4_A,
and H1_B to H4_B outputs. A 3-wire serial interface is used to
program each channel of the AD9974.

Available in a space-saving, 9 mm × 9 mm, CSP_BGA package,
the AD9974 is specified over an operating temperature range of

−25°C to +85°C.

AD9974

CCDINP_A

CCDINM_A

CCDINP_B

CCDINM_B

1.8V OUTP UT LDO A

1.8V OUTP UT LDO B

RG_A
RG_B

H1_A TO H4_

H1_B TO H4_B

4

4

CDS

CDS

HORIZONTAL

FUNCTIONAL BLOCK DIAGRAM

REFT_AREFB_

–3, 0, +3, +6dB

–3, 0, +3, +6dB

DRIVERS

VREF_A

VGA

VGA

INTERNAL CL OCKS

PRECISION

TIMING

CORE

SYNC

GENERATOR

HD_A VD_A HD_B VD_B

REFT_B REFB_B

6dB TO 42d B

6dB TO 42d B

Figure 1.

VREF_B

SL_A

CLAMP

CLAMP

INTERNAL

REGISTERS

SDATA_A

ADC

ADC

SL_B

14

14

SDATA_B

DOUT_A

DOUT_B

CLI_A
CLI_B

SCK_A
SCK_B

5955-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

AD9974

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Channel-to-Channel Specifications ........................................... 3

Timing Specifications .................................................................. 4

Digital Specifications ................................................................... 5

Analog Specifications ................................................................... 6

Absolute Maximum Ratings ............................................................ 8

Thermal Characteristics .............................................................. 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 11

Equivalent Input/Output Circuits ................................................ 12

Terminolog y .................................................................................... 13

Theory of Operation ...................................................................... 14

Programmable Timing Generation .............................................. 15

Precision Timing High Speed Timing Core ............................. 15

Horizontal Clamping and Blanking ......................................... 18

Complete Field—Combining H-Patterns ............................... 25

Mode Registers ........................................................................... 26

Horizontal Timing Sequence Example .................................... 28

Analog Front End Description and Operation ...................... 29

Applications Information .............................................................. 33

Recommended Power-Up Sequence ....................................... 33

Standby Mode Operation .......................................................... 36

CLI Frequency Change .............................................................. 36

Circuit Configuration ................................................................ 37

Grounding and Decoupling Recommendations .................... 37

3-Wire Serial Interface Timing ..................................................... 39

Layout of Internal Registers ...................................................... 40

Updating of Register Values ...................................................... 41

Complete Register Listing ............................................................. 42

Outline Dimensions ....................................................................... 50

Ordering Guide .......................................................................... 50

REVISION HISTORY

10/09—Revision A: Initial Version

Changes to Table 1 ............................................................................ 3

Changes to Table 3 ............................................................................ 4

Changes to Pin Function Descriptions Table ............................... 9

Changes to Figure 11 ...................................................................... 12

Changes to Individual HBLK Pattern Section ............................ 20

Changes to Table 14 ........................................................................ 25

Added Example Register Setting for Power-Up Section ........... 34

Added Additional Restrictions Section ....................................... 35

Changes to Table 2 .......................................................................... 36

Changes to 3 V System Compatibility Section ........................... 37

Changes to Grounding and Decoupling

Recommendations Section ............................................................ 37

Changes to Table 30 ........................................................................ 48

Changes to Table 31 ........................................................................ 49

Changes to Ordering Guide .......................................................... 50

Rev. A | Page 2 of 52

AD9974

SPECIFICATIONS

X = A = B, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit

TEMPERATURE RANGE

Operating −25 +85 °C
Storage −65 +150 °C

POWER SUPPLY VOLTAGE

AVDD_X (AFE, Timing Core) 1.6 1.8 2.0 V
RGVDD_X (RG_X Driver) 2.7 3.3 3.6 V
HVDD_X (H1_X to H4_X Drivers) 2.7 3.3 3.6 V
DVDD_X (All Other Digital) 1.6 1.8 2.0 V
DRVDD_X (Parallel Data Output Drivers) 1.6 3.0 3.6 V
IOVDD_X (I/O Supply Without the Use of LDO) 1.6 1.8 3.6 V

POWER SUPPLY CURRENTS—65 MHz OPERATION

AVDD_X (1.8 V) 55 mA
RGVDD_X (3.3 V, 20 pF RG Load) 5 mA
HVDD_X1 (3.3 V, 200 pF Total Load on H1 to H4) 40 mA
DVDD_X (1.8 V) 15 mA
DRVDD_X (3.0 V) 3 mA
IOVDD_X (1.8 V) 2 mA

POWER SUPPLY CURRENTS—STANDBY MODE OPERATION

Reference Standby 10 mA
Total Shutdown 0.5 mA

2

LDO

IOVDD_X (I/O Supply When Using LDO) 3.0 V
Output Voltage 1.85 V
Output Current 60 100 mA

CLOCK RATE (CLI) 8 65 MHz

1

The total power dissipated by the HVDD (or RGVDD) supply can be approximated as follows: Total HVDD Power = [C

Reducing the capacitive load and/or reducing the HVDD supply reduces the power dissipation. C

2

LDO should be used to supply only AVDD and DVDD.

is the total capacitance seen by all H-outputs.

LOAD

× HVDD × Pixel Frequency] × HVDD.

LOAD

CHANNEL-TO-CHANNEL SPECIFICATIONS

X = A = B, T

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

LINEARITY MISMATCH
CROSSTALK ERROR CDS = 0 dB

Channel A to Channel B −82 dB Full-scale step applied to Channel A while measuring response on Channel B
Channel B to Channel A −82 dB Full-scale step applied to Channel B while measuring response on Channel A

1

See the section for further measurement explanation. Terminology

MIN

to T

, AVDD_X = DVDD_X = 1.8 V, f

MAX

1

<0.5 % Absolute value above 1⁄16 of maximum output code

= 65 MHz, typical timing specifications, unless otherwise noted.

CLI

Rev. A | Page 3 of 52

AD9974

TIMING SPECIFICATIONS

X = A = B, CL = 20 pF, AVDD_X = DVDD_X = 1.8 V, f

Table 3.

Parameter Min Typ Max Unit Comments

MASTER CLOCK (CLI) See Figure 17

CLI Clock Period (t
CLI High/Low Pulse Width (t

) 15.38 ns

CONV

) 6.9 7.7 8.9 ns

ADC

Delay from CLI Rising Edge to Internal Pixel Position 0 (t

AFE

SHP Rising Edge to SHD Rising Edge (tS1) 6.9 7.7 8.5 ns See Figure 21
AFE Pipeline Delay 16 Cycles See Figure 22
CLPOB Pulse Width (Programmable) (t

1

)

2 20 Pixels

COB

HD Pulse Width t
VD Pulse Width 1 HD period ns

SERIAL INTERFACE See Figure 52

Maximum SCK Frequency (f

) 40 MHz

SCLK

SL to SCK Setup Time (tLS) 10 ns
SCK to SL Hold Time (tLH) 10 ns
SDATA Valid to SCK Rising Edge Setup (tDS) 10 ns
SCK Rising Edge to SDATA Valid Hold (tDH) 10 ns

H-COUNTER RESET SPECIFICATIONS See Figure 49

HD Pulse Width t
VD Pulse Width 1 HD period ns
VD Falling Edge to HD Falling Edge(t
HD Falling Edge to CLI Rising Edge(t

) 0 VD period − t

VDHD

) 3 t

HDCLI

CLI Rising Edge to SHPLOC (Internal Sample Edge) (t

TIMING CORE SETTING RESTRICTIONS

Inhibited Region for SHP Edge Location (t
Inhibited Region for SHP or SHD with Respect to H-Clocks

(See Figure 21)

RETIME = 0, MASK = 0 (t
RETIME = 0, MASK = 1 (t
RETIME = 1, MASK = 0 (t
RETIME = 1, MASK = 1 (t

3, 4, 5, 6

) H × NEGLOC − 15 H × NEGLOC − 0 Edge location

SHDINH

) H × POSLOC − 15 H × POSLOC − 0 Edge location

SHDINH

) H × NEGLOC − 15 H × NEGLOC − 0 Edge location

SHPINH

) H × POSLOC − 15 H × POSLOC − 0 Edge location

SHPINH

) (See Figure 21)250 64/0 Edge location

SHPINH

Inhibited Region for DOUTPHASE Edge Location (t

(See Figure 21)

1

Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.

2

Only applies to slave mode operation. The inhibited area for SHP is needed to meet the timing requirements for t

3

When 0x34[2:0] HxBLKRETIME bits are enabled, the inhibit region for SHD location changes to inhibit region for SHP location.

4

When sequence register 0x09[23:21] HBLK masking registers are set to 0, the H-edge reference becomes H × NEGLOC.

5

The H-clock signals that have SHP/SHD inhibit regions depend on the HCLK mode: Mode 1 = H1, Mode 2 = H1, H2, and Mode 3 = H1, H3.

6

These specifications apply when H1POL, H2POL, RGPOL, and HLPOL are all set to 1 (default setting).

= 65 MHz, unless otherwise noted.

CLI

) 5 ns

CLIDLY

ns

CONV

ns

CONV

) 3 t

CLISHP

DOUTINH

)

SHDLOC + 0 SHDLOC + 15 Edge location

ns

CONV

− 2 ns

CONV

− 2 ns

CONV

for proper H-counter reset operation.

CLISHP

Rev. A | Page 4 of 52

AD9974

DIGITAL SPECIFICATIONS

X = A = B, IOVDD_X = 1.6 V to 3.6 V, RGVDD_X = HVDD_X = 2.7 V to 3.6 V, CL = 20 pF, T

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS

High Level Input Voltage (VIH) IOVDD − 0.6 V
Low Level Input Voltage (VIL) 0.6 V
High Level Input Current (IIH) 10 μA
Low Level Input Current (IIL) 10 μA
Input Capacitance (CIN) 10 pF

LOGIC OUTPUTS

High Level Output Voltage (VOH) IOVDD − 0.5 V IOH = 2 mA
Low Level Output Voltage (VOL) 0.5 V IOL = 2 mA

CLI INPUT (CLI_BIAS = 0)

High Level Input Voltage (V
Low Level Input Voltage (V

) IOVDD/2 + 0.5 V

IHCLI

) IOVDD/2 − 0.5 V

ILCLI

H-DRIVER OUTPUTS

High Level Output Voltage at Maximum Current (VOH) HVDD − 0.5 V
Low Level Output Voltage at Maximum Current 0.5 V
Maximum Output Current (Programmable) (VOL) 30 mA
Maximum Load Capacitance 100 pF

MIN

to T

, unless otherwise noted.

MAX

Rev. A | Page 5 of 52

AD9974

ANALOG SPECIFICATIONS

X = A = B, AVDD_X = 1.8 V, f

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

CDS1

Allowable CCD Reset Transient 0.5 0.8 V
CDS Gain Accuracy

−3 dB CDS Gain −3.3 −2.8 −2.3
0 dB CDS Gain (Default) −0.7 −0.2 +0.3
3 dB CDS Gain 2.3 2.8 3.3
6 dB CDS Gain 4.9 5.4 5.9

Maximum Input Voltage VGA gain = 5.6 dB (Code 15, default value)

−3 dB CDS Gain 1.4 V p-p
0 dB CDS Gain (Default) 1.0 V p-p
3 dB CDS Gain 0.7 V p-p
6 dB CDS Gain 0.5 V p-p

Allowable OB Pixel Amplitude

0 dB CDS Gain (Default) −100 +200 mV
6 dB CDS Gain −50 +100 mV

VARIABLE GAIN AMPLIFIER (VGA_X)

Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Low Gain Setting (VGA Code 15, Default) 6 dB
Maximum Gain Setting (VGA Code 1023) 42 dB

BLACK LEVEL CLAMP

Clamp Level Resolution 1024 Steps
Minimum Clamp Level (Code 0) 0 LSB Measured at ADC output
Maximum Clamp Level (Code 1023) 1023 LSB Measured at ADC output

ADC (CHN_A and CHN_B)

Resolution 14 Bits
Differential Nonlinearity (DNL) −1.0 ±0.5 +1.2 LSB
No Missing Codes Guaranteed
Integral Nonlinearity (INL) 5 15 LSB
Full-Scale Input Voltage 2.0 V

VOLTAGE REFERENCE

Reference Top Voltage (REFT_X) 1.4 V
Reference Bottom Voltage (REFB_X) 0.4 V

SYSTEM PERFORMANCE Specifications include entire signal chain

VGA Gain Accuracy 0 dB CDS gain (default)

Low Gain (Code 15) 5.1 5.6 6.1 dB Gain = (0.0359 × code) + 5.1 dB

Maximum Gain (Code 1023) 41.3 41.8 42.3 dB
Peak Nonlinearity, 500 mV Input Signal 0.1 0.4 % 12 dB total gain applied
Total Output Noise 2 LSB rms AC-grounded input, 6 dB gain applied
Power Supply Rejection (PSR) 48 dB Measured with step change on supply

1

Input signal characteristics are defined as shown in . Figure 2

= 65 MHz, typical timing specifications, T

CLI

MIN

to T

, unless otherwise noted.

MAX

Rev. A | Page 6 of 52

AD9974

800mV
MAXIMUM

500mV TYP

RESET TRANSIENT

200mV MAX

OPTICAL BLACK PIXEL

MAXIMUM INPUT LIMIT =
LESSER OF 2.2V
OR (AVDD + 0.3V )

+1.8V TYP (AVDD)

+1.3V TYP (AVDD – 0.5V)
DC RESTORE VO LTAGE

1V MAXIMUM INPUT
SIGNAL RANGE
(0dB CDS GAIN)

0V (AVSS)

MINIMUM INPUT LIMIT
(AVSS – 0.3V)

05957-002

Figure 2. Input Signal Characteristics

Rev. A | Page 7 of 52

AD9974

ABSOLUTE MAXIMUM RATINGS

Ratings apply to both Channel A and Channel B, unless
otherwise noted.

Table 6.

Parameter Rating

AVDD to AVSS −0.3 V to +2.2 V
DVDD to DVSS −0.3 V to +2.2 V
DRVDD to DRVSS −0.3 V to +3.9 V
IOVDD to DVSS −0.3 V to +3.9 V
HVDD to HVSS −0.3 V to +3.9 V
RGVDD to RGVSS −0.3 V to +3.9 V
Any VSS −0.3 V to +0.3 V
RG Output to RGVSS −0.3 V to RGVDD + 0.3 V
H1 to H4, HL Output to HVSS −0.3 V to HVDD + 0.3 V
SCK, SL, SDI to DVSS −0.3 V to IOVDD + 0.3 V
REFT, REFB, CCDINM, CCDINP to AVSS −0.2 V to AVDD + 0.2 V
Junction Temperature 150°C
Lead Temperature (10 sec) 350°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS

θJA is measured using a 4-layer PCB with the exposed paddle
soldered to the board.

Table 7. Thermal Resistance

Package Type θJA Unit

100-Lead, 9 mm × 9 mm, CSP_BGA 38.3 °C/W

ESD CAUTION

Rev. A | Page 8 of 52

AD9974

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD9974

TOP VIEW

A1 CORNER

INDEX AREA

A
B
C
D
E
F
G
H

J

K

Figure 3. Pin Configuration

(Not to S cale)

2345678910

1

05955-003

Table 8. Pin Function Descriptions

Ball Location Mnemonic Type

1

Description

B2 SL_A DI 3-Wire Serial Load for Channel A.

C2 SDATA_A DI 3-Wire Serial Data for Channel A.

D2 SCK_A DI 3-Wire Serial Clock for Channel A.

C1 REFT_A AO Reference with Top Decoupling for Channel A. Decouple with 0.1 μF to AVSS_A.

D1 REFB_A AO Reference with Bottom Decoupling for Channel A. Decouple with 0.1 μF to AVSS_A.

A1 CCDINM_A AI Analog Input for Channel A Image Sensor Signal.

F4 H1_A DO CCD Horizontal Clock 1 for Channel A.

F3 H2_A DO CCD Horizontal Clock 2 for Channel A.

D4 H3_A DO CCD Horizontal Clock 3 for Channel A.

D3 H4_A DO CCD Horizontal Clock 4 for Channel A.

B4 RG_A DO CCD Reset Gate Clock for Channel A.

J2 DRVSS_A P Digital Driver Ground for Channel A.

K3 DRVDD_A P Digital Driver Supply for Channel A: 1.8 V or 3.0 V.

E3 HVSS_A P H1_A to H4_A Driver Ground for Channel A.

E4 HVDD_A P H1_A to H4_A Driver Supply for Channel A: 3.0 V.

C3 RGVSS_A P RG_A Driver Ground for Channel A.

C4 RGVDD_A P RG_A Driver Supply for Channel A: 3.0 V.

B3 IOVDD_A P

Digital I/O Supply: 1.8 V or 3.0 V (HD, VD, SL, SCK, SDATA) and LDO Input (3.0 V Only)

When LDO Is Used.
A4 CLI_A DI Master Clock Input for Channel A.
B1 AVSS_A P Analog Ground for Channel A.
A2 CCDINP_A AI Analog Input for Channel A Image Sensor Signal.
F2 DVSS_A P Digital Ground for Channel A.
F1 DVDD_A P Digital Supply for Channel A: 1.8 V.
E2 VD_A DI Vertical Sync Pulse for Channel A.
E1 HD_A DI Horizontal Sync Pulse for Channel A.
B8 SL_B DI 3-Wire Serial Load for Channel B.
C8 SDATA_B DI 3-Wire Serial Data for Channel B.
A5 LDO_OUT_A P 1.8 V LDO Output from Channel A.
A6 CCDINM_B AI Analog Input for Channel B Image Sensor Signal.
D8 SCK_B DI 3-Wire Serial Clock for Channel B.
C7 REFT_B AO Reference with Top Decoupling for Channel B. Decouple with 0.1 μF to AVSS_B.
D7 REFB_B AO Reference with Bottom Decoupling for Channel B. Decouple with 0.1 μF to AVSS_B.
A7 CCDINP_B AI Analog Input for Channel B Image Sensor Signal.
F10 H1_B DO CCD Horizontal Clock 1 for Channel B.
F9 H2_B DO CCD Horizontal Clock 2 for Channel B.

Rev. A | Page 9 of 52

AD9974

Ball Location Mnemonic Type

1

Description

D10 H3_B DO CCD Horizontal Clock 3 for Channel B.
D9 H4_B DO CCD Horizontal Clock 4 for Channel B.
B10 RG_B DO CCD Reset Gate Clock for Channel B.
J8 DRVSS_B P Digital Driver Ground for Channel B.
K9 DRVDD_B P Digital Driver Supply for Channel B: 1.8 V or 3.0 V.
E9 HVSS_B P H1_B to H4_B Driver Ground for Channel B.
E10 HVDD_B P H1_B to H4_B Driver Supply for Channel B: 3.0 V.
C9 RGVSS_B P RG_B Driver Ground for Channel B.
C10 RGVDD_B P RG_B Driver Supply for Channel B: 3.0 V.
B9 IOVDD_B P

Digital I/O Supply: 1.8 V or 3.0 V (HD, VD, SL, SCK, SDATA) and LDO Input (3.0 V Only)

When LDO Is Used.
A10 LDO_OUT_B P 1.8 V LDO Output from Channel B.
B7 AVSS_B P Analog Ground for Channel B.
A8 AVDD_B P Analog Supply for Channel B: 1.8 V.
F8 DVSS_B P Digital Ground for Channel B.
F7 DVDD_B P Digital Supply for Channel B: 1.8 V.
E8 VD_B DI Vertical Sync Pulse for Channel B.
E7 HD_B DI Horizontal Sync Pulse for Channel B.
A3 AVDD_A P Analog Supply for Channel A: 1.8 V.
G1 D0_A DO Data Outputs Channel A.
H1 D1_A DO Data Outputs Channel A.
J1 D2_A DO Data Outputs Channel A.
K1 D3_A DO Data Outputs Channel A.
G2 D4_A DO Data Outputs Channel A.
H2 D5_A DO Data Outputs Channel A.
K2 D6_A DO Data Outputs Channel A.
G3 D7_A DO Data Outputs Channel A.
H3 D8_A DO Data Outputs Channel A.
J3 D9_A DO Data Outputs Channel A.
K4 D10_A DO Data Outputs Channel A.
J4 D11_A DO Data Outputs Channel A.
H4 D12_A DO Data Outputs Channel A.
G4 D13_A DO Data Outputs Channel A.
B5, C5, D5, E5, F5, G5, H5,

GND P Ground Connection.
J5, K5, B6, C6, D6, E6, F6,
G6, H6, J6, K6

A9 CLI_B DI Master Clock Input for Channel B.
G7 D0_B DO Data Outputs Channel B.
H7 D1_B DO Data Outputs Channel B.
J7 D2_B DO Data Outputs Channel B.
K7 D3_B DO Data Outputs Channel B.
G8 D4_B DO Data Outputs Channel B.
H8 D5_B DO Data Outputs Channel B.
K8 D6_B DO Data Outputs Channel B.
G9 D7_B DO Data Outputs Channel B.
H9 D8_B DO Data Outputs Channel B.
J9 D9_B DO Data Outputs Channel B.
K10 D10_B DO Data Outputs Channel B.
J10 D11_B DO Data Outputs Channel B.
H10 D12_B DO Data Outputs Channel B.
G10 D13_B DO Data Outputs Channel B.

1

AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power.

Rev. A | Page 10 of 52

AD9974

TYPICAL PERFORMANCE CHARACTERISTICS

250

200

150

100

POWER (mW)

50

0

20 25 30 35 40 45 50 55 60 65

TOTAL POWER

3.3V SUPPLIES

1.8V SUPPLIES

SAMPLE RATE (MHz)

Figure 4. Power vs. Sample Rate

05955-005

10

8

6

4

2

LSB

0

–2

–4

–6

–8

0

2k 4k 6k 8k 10k 12k 14k 16k

ADC OUTPUT CODE

05955-008

Figure 7. Integral Nonlinearity

180

160

140

120

100

80

60

RMS OUTPUT NOISE (LSB)

40

20

0

0 5 10 15 20 25 30 35 40 45

VGA GAIN (dB)

Figure 5. RMS Output Noise vs. VGA Gain

1.0

0.8

0.6

0.4

0.2

0

LSB

–0.2

–0.4

–0.6

–0.8
–1.0

0

2k 4k 6k 8k 10k 12k 14k 16k

ADC OUTPUT CODE

Figure 6. Differential Nonlinearity

1.0

0.8

0.6

0.4

0.2

0

–0.2

INL MISMATCH (%)

–0.4

–0.6

–0.8

–1.0

1k

3k 5k 7k 9k 11k 13k 15k

05955-006

ADC OUTPUT CODE

05955-009

Figure 8. Linearity Mismatch vs. ADC Output Code

05955-007

Rev. A | Page 11 of 52

AD9974

A

V

EQUIVALENT INPUT/OUTPUT CIRCUITS

DD

R

AVSS AVSS

Figure 9. CCDIN Input

IOVDD

330Ω

IOVDD

CLI

05955-010

330Ω

AVSS

100kΩ

+

05955-011

Figure 11. CLI Input, Register 0x15[0] = 1 Enables the Bias Circuit

HVDD OR RGVDD

DATA

ENABLE

OUTPUT

DVSS

Figure 10. Digital Inputs

05955-012

HVSS OR RGVSS

5955-013

Figure 12. H1 to H4 and RG Outputs

Rev. A | Page 12 of 52

AD9974

TERMINOLOGY

Differential Nonlinearity (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Therefore,
every code must have a finite width. No missing codes guaranteed
to 14-bit resolution indicates that all 16,384 codes, each for its
respective input, must be present over all operating conditions.

Peak Nonlinearity

Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9974 from a true straight
line. The point used as zero scale occurs 0.5 LSB before the first
code transition. Positive full scale is defined as a level 1 LSB
and 0.5 LSB beyond the last code transition. The deviation is
measured from the middle of each particular output code to the
true straight line. The error is then expressed as a percentage
of the 2 V ADC full-scale signal. The input signal is always
appropriately gained up to fill the ADC full-scale range.

Tot a l O ut p ut Noi se

The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage using the relationship

1 LSB = (ADC Full Scale/2

where n is the bit resolution of the ADC. For the AD9974,
1 LSB is approximately 122.0 μV.

Linearity Mismatch

The linearity mismatch is calculated by taking the difference in
INL of the two channels at Input X, and then expressing the
difference as a percentage of the output code at X. The values
given in Tab le 2 are obtained over the range of 1⁄16 and
maximum of the output code. The general trend is for the
linearity mismatch to decrease as the output approaches the
maximum code, as shown in Figure 8.

n

Codes)

MAX

OUTPUT CODE (LSB)

OUTPUT (X)

MAX/16

INL A(X)

INL B(X)

0

0

XFS

INPUT VOLTAGE

Figure 13. Linearity Mismatch Definition

CHANNEL B

IDEAL

CHANNEL A

Power Supply Rejection (PSR)

The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.

Crosstalk

The crosstalk is measured while applying a full-scale step to
one channel and measuring the interference on the opposite
channel.

)(

LSBceInterferen

⎛
⎜

×=

Crosstalk

log20)dB(

⎜
⎝

384,16

⎞
⎟

⎟
⎠

5955-004

MismatchLinearity

=

(%)

−

XBINLXAINL

)()(

XCodeOutput

)(

Rev. A | Page 13 of 52

AD9974

THEORY OF OPERATION

V DRIVER

H1_A TO H4_A, RG_A
H1_B TO H4_B, RG_B

CCDINP_A
CCDINM_A

CCD

CCDINP_B
CCDINM_B

V1 > Vx, VSG 1 > VS Gx, SUBCK

AD9974

INTEGRATED

AFE + TD

SERIAL

INTERFACE

DOUT_A
DOUT_B

HD_A, VD_A,
HD_B, VD_B

CLI_A, CLI _B

DIGITAL IMAGE

PROCESSING

ASIC

05955-014

Figure 14. Typical Application

Figure 14 shows the typical system block diagram for the AD9974.
The charge-coupled device (CCD) output is processed by the
analog front-end (AFE) circuitry of the AD9974, consisting of a
CDS, VGA, black level clamp, and ADC. The digitized pixel
information is sent to the digital image processor chip, which
performs the postprocessing and compression. To operate the
CCD, all CCD timing parameters are programmed into the
AD9974 from the system ASIC through the 3-wire serial
interface. From the system master clock, CLI_X, which is provided
by the image processor or external crystal, the AD9974 generates
the horizontal clocks of the CCD and all internal AFE clocks.

MAX VD LENG TH IS 8192 LINES

All AD9974 clocks are synchronized with VD and HD inputs.
All of the AD9974 horizontal pulses (CLPOB, PBLK, and
HBLK) are programmed and generated internally.

The H-drivers for H1 to H4 and RG are included in the
AD9974, allowing these clocks to be directly connected to the
CCD. An H-driver voltage of 3 V is supported in the AD9974.

Figure 15 and Figure 16 show the maximum horizontal and
vertical counter dimensions for the AD9974. All internal horizontal
and vertical clocking is controlled by these counters, which specify
line and pixel locations. Maximum HD length is 8191 pixels per
line, and maximum VD length is 8191 lines per field.

MAXIMUM COUNTE R DIM ENS I O NS

13-BIT HORIZONTAL = 8192 PIXELS MAX

13-BIT VERTICAL = 8192 L INES MAX

5955-015

Figure 15. Vertical and Horizontal Counters

CLI

VD

HD

MAX HD LENGTH IS 8192 PIXELS

Figure 16. Maximum VD/HD Dimensions

Rev. A | Page 14 of 52

05955-016

AD9974

S

PROGRAMMABLE TIMING GENERATION

PRECISION TIMING HIGH SPEED TIMING CORE

The AD9974 generates flexible high speed timing signals using
the Precision Timing core. This core, composed of the Reset
Gate RG, Horizontal Driver H1 to Horizontal Driver H4, and
SHP/SHD sample clocks, is the foundation for generating the
timing for both the CCD and the AFE. A unique architecture
makes it routine for the system designer to optimize image
quality by providing precise control over the horizontal CCD
readout and the AFE correlated double sampling.

Timing Resolution

The Precision Timing core uses a master clock input (CLI_X)
as a reference. This clock input should be the same as the CCD
pixel clock frequency. Figure 17 illustrates how the internal timing
core divides the master clock period into 64 steps or edge positions;
therefore, the edge resolution of the Precision Timing core is
(t

/64). For more information on using the CLI input, refer to

CLI

the Applications Information section.

POSITION

P[0] P[64] = P[0]P[16] P[32] P[48]

Using a 65 MHz CLI frequency, the edge resolution of the
Precision Timing core is approximately 240 ps. If a 1× system
clock is not available, it is possible to use a 2× reference clock
by programming the CLIDIVIDE register (Address 0x0D). The
AD9974 then internally divides the CLI frequency by 2.

High Speed Clock Programmability

Figure 18 shows when the high speed clocks, RG, H1 to H4,
SHP, and SHD, are generated. The RG pulse has programmable
rising and falling edges and can be inverted using the polarity
control. The H1 and H2 horizontal clocks have separate program­mable rising and falling edges, as well as separate polarity control.
The AD9974 provides additional HCLK-mode programmability,
as described in Ta bl e 9 .

The edge location registers are each six bits wide, allowing the
selection of all 64 edge locations. Figure 21 shows the default
timing locations for all of the high speed clock signals.

CLI

t

CLIDLY

1 PIXEL

PERIOD

NOTES

1. THE PIXEL CLOCK PERIOD IS DIVIDED INTO 64 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.

2. THERE IS A F I XED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITION (

t

CLIDLY

).

5955-017

Figure 17. High Speed Clock Resolution from CLI Master Clock Input

1

CCD

IGNAL

34

RG

56

H1, H3

H2, H4

PROGRAMMABLE CLOCK POSI T IONS:

1

SHP SAMPLE LOCATION.

2

SHD SAMPLE LO CAT I O N.

3

RG RISING EDGE.

4

RG FALLING EDGE.

5

H1 RISING EDGE.

6

H1 FALLING EDGE.

Figure 18. High Speed Clock Programmable Locations (HCLK Mode 1)

2

05955-018

Rev. A | Page 15 of 52

AD9974

12

H1, H3

43

H2, H4

H1 TO H4 P R OGRAMM A B LE LO CATI ONS:

1

H1 RISING EDGE.

2

H1 FALLING EDGE.

3

H2 RISING EDGE.

4

H2 FALLING EDGE.

5955-019

Figure 19. HCLK Mode 2 Operation

12

H1

H2

3

H3

H4

H1 TO H4 PROGRAMMABLE LOCATIONS:

1

H1 RISIN G EDGE .

2

H1 FALLING EDGE.

3

H3 RISIN G EDGE .

4

H3 FALLING EDGE.

4

05955-020

Figure 20. HCLK Mode 3 Operation

P[0]

P[32]P[16] P[48]POSITION

P[64] = P[0]

CLI

RGr[0] RGf[16]

RG

H1r[0] H1f[32]

H1

H2

t

CCD

SIGNAL

SHPLOC[32]

SHP

SHDLOC[0]

SHD

t

DOUTPHASEP

NOTES

1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.
TYPICAL P OSITI ONS FOR EACH SIGNAL ARE SHO WN. HCLK MODE 1 IS SHOWN.

2. CERTAIN POSITIONS SHOULD BE AVOIDED FO R EACH SIGNAL, S HOWN ABOVE AS INHIBIT REGIONS.

3. IF A SETTING I N THE INHIBIT REGION IS USED, AN UNSTABLE PIXEL S HIFT CAN OCCUR IN THE HBLK LOCATION OR AF E P IPELINE.

DOUTINH

DATAPHASEP[32]

S1

t

SHPINH

t

SHDINH

05955-021

Figure 21. High Speed Timing Default Locations

Rev. A | Page 16 of 52