ANALOG DEVICES AD9972 Service Manual

Dual-Channel, 14-Bit, CCD Signal

Processor with Precision Timing™ Core

FEATURES OF EACH CHANNEL

1.8 V analog and digital core supply voltage Correlated double sampler (CDS) with

−3 dB, 0 dB, +3 dB, and +6 dB gain 6 dB to 42 dB, 10-bit variable gain amplifier (VGA) 14-bit, 40 MHz analog-to-digital converter (ADC) Black level clamp with variable level control Complete on-chip timing generator Precision Timing core with 400 ps resolution @ 40 MHz On-chip 3 V horizontal and RG drivers 100-lead, 9 mm × 9 mm, 0.8 mm pitch, CSP_BGA package Internal LDO regulator circuitry

APPLICATIONS

Professional HDTV camcorders Professional/high end digital cameras Broadcast cameras Industrial high speed cameras

FUNCTIONAL BLOCK DIAGRAM

REFT_AREFB_

AD9972

GENERAL DESCRIPTION

The AD9972 is a highly integrated, dual-channel CCD signal processor for high speed digital video camera applications. Each channel is specified at pixel rates of up to 40 MHz. The AD9972 consists of a complete analog front end with analog-to-digital conversion combined with a programmable timing driver. The Precision Timing core allows adjustment of high speed clocks with approximately 400 ps resolution at 40 MHz operation.

Each analog front end includes black level clamping, CDS, VGA, and a 40 MSPS, 14-bit ADC. The timing driver provides the high speed CCD clock drivers for the RG_A, RG_B, H1_A to H4_A, and H1_B to H4_B outputs. A 3-wire serial interface is used to program each channel of the AD9972.

Available in a space-saving, 9 mm × 9 mm, CSP_BGA package, the AD9972 is specified over an operating temperature range of

−25°C to +85°C.

REFT_B REFB_B

AD9972

CDS

HORIZONTAL

CCDIN_A

CCDIN_B

1.8V OUTP UT LDO A

1.8V OUTP UT LDO B

RG_A RG_B

H1_A TO H4_A

H1_B TO H4_B

–3, 0, +3, +6dB

DRIVERS

VREF_A

VGA

INTERNAL CLOCKS

PRECISION

TIMING

CORE

SYNC

GENERATOR

HD_A VD_A HD_B VD_B

6dB

42dB

VREF_B

SL_A

CLAMP

INTERNAL

REGISTERS

SDATA_A

ADC

Figure 1.

For more information on the AD9772, contact Analog Devices, Inc. at: afe.ccd@analog.com.

SL_B

SDATA_B

DOUT_A

DOUT_B

CLI_A CLI_B

SCK_A SCK_B

5866-001

Rev. SpA

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9972

NOTES

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