ANALOG DEVICES AD9959 Service Manual

4-Channel, 500 MSPS DDS

S

FEATURES

4 synchronized DDS channels @ 500 MSPS Independent frequency/phase/amplitude control between

channels Matched latencies for frequency/phase/amplitude changes Excellent channel-to-channel isolation (>65 dB) Linear frequency/phase/amplitude sweeping capability Up to 16 levels of frequency/phase/amplitude modulation

(pin-selectable) 4 integrated 10-bit digital-to-analog converters (DACs) Individually programmable DAC full-scale currents

0.12 Hz or better frequency tuning resolution 14-bit phase offset resolution 10-bit output amplitude scaling resolution Serial I/O port interface (SPI) with enhanced data throughput

FUNCTIONAL BLOCK DIAGRAM

with 10-Bit DACs

AD9959

Software-/hardware-controlled power-down Dual supply operation (1.8 V DDS core/3.3 V serial I/O) Multiple device synchronization Selectable 4× to 20× REFCLK multiplier (PLL) Selectable REFCLK crystal oscillator 56-lead LFCSP package

APPLICATIONS

Agile local oscillators Phased array radars/sonars Instrumentation Synchronized clocking RF source for AOTF

10-BIT DAC

RECONSTRUCTED

SINE WAVE

SYSTEM

CLOCK OURCE

MODULATIO N

REF CLOCK

INPUT CIRCUIT RY

DDS CORES

CONTRO L

(4)

500MSPS

TIMING AND

CONTROL

USER INTERFACE

Figure 1.

10-BIT DAC

RECONSTRUCTED

SINE WAVE

RECONSTRUCTED

SINE WAVE

RECONSTRUCTED

SINE WAVE

05246-101

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9959

GENERAL DESCRIPTION

The AD9959 consists of four direct digital synthesizer (DDS) cores that provide independent frequency, phase, and amplitude control on each channel. This flexibility can be used to correct imbalances between signals due to analog processing, such as filtering, amplification, or PCB layout-related mismatches. Because all channels share a common system clock, they are inherently synchronized. Synchronization of multiple devices is supported.

The AD9959 can perform up to a 16-level modulation of frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is performed by applying data to the profile pins. In addition, the AD9959 also supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentation.

The AD9959 serial I/O port offers multiple configurations to provide significant flexibility. The serial I/O port offers an SPIcompatible mode of operation that is virtually identical to the SPI operation found in earlier Analog Devices, Inc., DDS products. Flexibility is provided by four data pins (SDIO_0/SDIO_1/ SDIO_2/SDIO_3) that allow four programmable modes of serial I/O operation.

The AD9959 uses advanced DDS technology that provides low power dissipation with high performance. The device incorporates four integrated, high speed 10-bit DACs with excellent wideband and narrow-band SFDR. Each channel has a dedicated 32-bit

frequency tuning word, 14 bits of phase offset, and a 10-bit output scale multiplier.

The DAC outputs are supply referenced and must be terminated into AVDD by a resistor or an AVDD center-tapped transformer. Each DAC has its own programmable reference to enable different full-scale currents for each channel.

The DDS acts as a high resolution frequency divider with the REFCLK as the input and the DAC providing the output. The REFCLK input source is common to all channels and can be driven directly or used in combination with an integrated REFCLK multiplier (PLL) up to a maximum of 500 MSPS. The PLL multiplication factor is programmable from 4 to 20, in integer steps. The REFCLK input also features an oscillator circuit to support an external crystal as the REFCLK source. The crystal must be between 20 MHz and 30 MHz. The crystal can be used in combination with the REFCLK multiplier.

The AD9959 comes in a space-saving 56-lead LFCSP package. The DDS core (AVDD and DVDD pins) is powered by a 1.8 V supply. The digital I/O interface (SPI) operates at 3.3 V and requires DVDD_I/O (Pin 49) be connected to 3.3 V.

The AD9959 operates over the industrial temperature range of

−40°C to +85°C.

SYNC_IN

SYNC_OUT

I/O_UPDATE

SYNC_CLK

REF_CLK

AD9959

DFTW

BUFFER/

XTAL

OSCILLATOR

CLK_MODE_SE L

Σ

32

32 32 1015

32

FTW

÷4

REF CLOCK MULTIPLIER

32 1015

Σ

ΣΣΣ

32

32 PHASE/

4× TO 20×

Σ

ΔPHASE

TIMING AND CONTRO L LOGIC

SYSTEM

CLK

MUX

D

S

C

D

cos(x)

S

C

cos(x)

S

C

cos(x)

S

C

cos(x)

1.8V

Σ

1.8V

AVDD DVDD

O

R

E

O

E

R

E

R

O

E

R

O

1015

AMP/ ΔAMP

CONTROL

REGISTERS

C

H

A

N

R

E

I

G

S

T

PROFILE

REGIS TERS

P0 P1 P2 P3 DVDD_I/O

DAC

10

DAC

10

DAC

10

DAC

10

SCALABLE

DAC REF

1014

CURRENT

E

SERIAL

L

R

S

I/O

PORT

BUFFER

CH0_IOUT

CH1_IOUT

CH2_IOUT

CH3_IOUT

DAC_RSET

PWR_DWN_CT L

MASTER_RESET

SCLK CS

SDIO_0 SDIO_1 SDIO_2 SDIO_3

05246-001

Figure 2. Detailed Block Diagram

Rev. B | Page 3 of 44

AD9959

SPECIFICATIONS

AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; T = 25°C; R (REFCLK multiplier bypassed), unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE CLOCK INPUT CHARACTERISTICS See Figure 34 and Figure 35

Frequency Range

REFCLK Multiplier Bypassed 1 500 MHz REFCLK Multiplier Enabled 10 125 MHz Internal VCO Output Frequency Range

VCO Gain Control Bit Set High1 255 500 MHz

VCO Gain Control Bit Set Low1

Crystal REFCLK Source Range 20 30 MHz Input Level 200 1000 mV Measured at each pin (single-ended) Input Voltage Bias Level 1.15 V Input Capacitance 2 pF Input Impedance 1500 Ω Duty Cycle with REFCLK Multiplier Bypassed 45 55 % Duty Cycle with REFCLK Multiplier Enabled 35 65 % CLK Mode Select (Pin 24) Logic 1 Voltage 1.25 1.8 V 1.8 V digital input logic CLK Mode Select (Pin 24) Logic 0 Voltage 0.5 V 1.8 V digital input logic

DAC OUTPUT CHARACTERISTICS Must be referenced to AVDD

Resolution 10 Bits Full-Scale Output Current 1.25 10 mA Gain Error Channel-to-Channel Output Amplitude Matching Error −2.5 +2.5 % Output Current Offset 1 25 μA Differential Nonlinearity ±0.5 LSB Integral Nonlinearity ±1.0 LSB Output Capacitance 3 pF Voltage Compliance Range AVDD − 0.50 AVDD + 0.50 V Channel-to-Channel Isolation 65 dB DAC supplies tied together

WIDEBAND SFDR The frequency range for wideband

1 MHz to 20 MHz Analog Output 20 MHz to 60 MHz Analog Output 60 MHz to 100 MHz Analog Output 100 MHz to 150 MHz Analog Output 150 MHz to 200 MHz Analog Output

NARROW-BAND SFDR

1.1 MHz Analog Output (±10 kHz)

1.1 MHz Analog Output (±50 kHz)

1.1 MHz Analog Output (±250 kHz)

1.1 MHz Analog Output (±1 MHz)

15.1 MHz Analog Output (±10 kHz)

15.1 MHz Analog Output (±50 kHz)

15.1 MHz Analog Output (±250 kHz)

15.1 MHz Analog Output (±1 MHz)

40.1 MHz Analog Output (±10 kHz)

40.1 MHz Analog Output (±50 kHz)

40.1 MHz Analog Output (±250 kHz)

40.1 MHz Analog Output (±1 MHz) −82 dBc

75.1 MHz Analog Output (±10 kHz) −87 dBc

100 160 MHz

−10

= 1.91 kΩ; external reference clock frequency = 500 MSPS

SET

+10 %FS

(see Figure 19)

SFDR is defined as dc to Nyquist

dBc

−65

dBc

−62

dBc

−59

dBc

−56

dBc

−53

dBc

−90

dBc

−88

dBc

−86

dBc

−85

dBc

−90

dBc

−87

dBc

−85

dBc

−83

dBc

−90

dBc

−87

dBc

−84

Rev. B | Page 4 of 44

AD9959

Parameter Min Typ Max Unit Test Conditions/Comments

75.1 MHz Analog Output (±50 kHz) −85 dBc

75.1 MHz Analog Output (±250 kHz) −83 dBc

75.1 MHz Analog Output (±1 MHz) −82 dBc

100.3 MHz Analog Output (±10 kHz) −87 dBc

100.3 MHz Analog Output (±50 kHz) −85 dBc

100.3 MHz Analog Output (±250 kHz) −83 dBc

100.3 MHz Analog Output (±1 MHz) −81 dBc

200.3 MHz Analog Output (±10 kHz) −87 dBc

200.3 MHz Analog Output (±50 kHz) −85 dBc

200.3 MHz Analog Output (±250 kHz) −83 dBc

200.3 MHz Analog Output (±1 MHz) −81 dBc

PHASE NOISE CHARACTERISTICS

Residual Phase Noise @ 15.1 MHz (f

@ 1 kHz Offset −150 dBc/Hz @ 10 kHz Offset −159 dBc/Hz @ 100 kHz Offset −165 dBc/Hz @ 1 MHz Offset −165 dBc/Hz

Residual Phase Noise @ 40.1 MHz (f

@ 1 kHz Offset −142 dBc/Hz @ 10 kHz Offset −151 dBc/Hz @ 100 kHz Offset −160 dBc/Hz @ 1 MHz Offset −162 dBc/Hz

Residual Phase Noise @ 75.1 MHz (f

@ 1 kHz Offset −135 dBc/Hz @ 10 kHz Offset −146 dBc/Hz @ 100 kHz Offset −154 dBc/Hz @ 1 MHz Offset −157 dBc/Hz

Residual Phase Noise @ 100.3 MHz (f

@ 1 kHz Offset −134 dBc/Hz @ 10 kHz Offset −144 dBc/Hz @ 100 kHz Offset −152 dBc/Hz @ 1 MHz Offset −154 dBc/Hz

Residual Phase Noise @ 15.1 MHz (f

with REFCLK Multiplier Enabled 5× @ 1 kHz Offset −139 dBc/Hz @ 10 kHz Offset −149 dBc/Hz @ 100 kHz Offset −153 dBc/Hz @ 1 MHz Offset −148 dBc/Hz

Residual Phase Noise @ 40.1 MHz (f

with REFCLK Multiplier Enabled 5× @ 1 kHz Offset −130 dBc/Hz @ 10 kHz Offset −140 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −139 dBc/Hz

Residual Phase Noise @ 75.1 MHz (f

with REFCLK Multiplier Enabled 5×

@ 1 kHz Offset −123 dBc/Hz @ 10 kHz Offset −134 dBc/Hz @ 100 kHz Offset −138 dBc/Hz @ 1 MHz Offset −132 dBc/Hz

)

OUT

)

OUT

)

OUT

)

OUT

)

Rev. B | Page 5 of 44

AD9959

Parameter Min Typ Max Unit Test Conditions/Comments

Residual Phase Noise @ 100.3 MHz (f

with REFCLK Multiplier Enabled 5×

@ 1 kHz Offset −120 dBc/Hz @ 10 kHz Offset −130 dBc/Hz @ 100 kHz Offset −135 dBc/Hz @ 1 MHz Offset −129 dBc/Hz

Residual Phase Noise @ 15.1 MHz (f

with REFCLK Multiplier Enabled 20×

@ 1 kHz Offset −127 dBc/Hz @ 10 kHz Offset −136 dBc/Hz @ 100 kHz Offset −139 dBc/Hz @ 1 MHz Offset −138 dBc/Hz

Residual Phase Noise @ 40.1 MHz (f

with REFCLK Multiplier Enabled 20× @ 1 kHz Offset −117 dBc/Hz @ 10 kHz Offset −128 dBc/Hz @ 100 kHz Offset −132 dBc/Hz @ 1 MHz Offset −130 dBc/Hz

Residual Phase Noise @ 75.1 MHz (f

with REFCLK Multiplier Enabled 20×

@ 1 kHz Offset −110 dBc/Hz @ 10 kHz Offset −121 dBc/Hz @ 100 kHz Offset −125 dBc/Hz @ 1 MHz Offset −123 dBc/Hz

Residual Phase Noise @ 100.3 MHz (f

with REFCLK Multiplier Enabled 20×

@ 1 kHz Offset −107 dBc/Hz @ 10 kHz Offset −119 dBc/Hz @ 100 kHz Offset −121 dBc/Hz @ 1 MHz Offset −119 dBc/Hz

SERIAL PORT TIMING CHARACTERISTICS

Maximum Frequency Serial Clock (SCLK) 200 MHz Minimum SCLK Pulse Width Low (t Minimum SCLK Pulse Width High (t Minimum Data Setup Time (tDS) 2.2 ns Minimum Data Hold Time 0 ns Minimum

CS

Setup Time (t

)

PRE

Minimum Data Valid Time for Read Operation 12 ns

MISCELLANEOUS TIMING CHARACTERISTICS

MASTER_RESET Minimum Pulse Width 1 Min pulse width = 1 sync clock period I/O_UPDATE Minimum Pulse Width 1 Min pulse width = 1 sync clock period Minimum Setup Time (I/O_UPDATE to SYNC_CLK) 4.8 ns Rising edge to rising edge Minimum Hold Time (I/O_UPDATE to SYNC_CLK) 0 ns Rising edge to rising edge Minimum Setup Time (Profile Inputs to SYNC_CLK) 5.4 ns Minimum Hold Time (Profile Inputs to SYNC_CLK) 0 ns Minimum Setup Time (SDIO Inputs to SYNC_CLK) 2.5 ns Minimum Hold Time (SDIO Inputs to SYNC_CLK) 0 ns Propagation Time Between REF_CLK and SYNC_CLK 2.25 3.5 5.5 ns Profile Pin Toggle Rate 2 Sync

CMOS LOGIC INPUTS

VIH 2.0 V VIL 0.8 V Logic 1 Current 3 12 μA Logic 0 Current −12 μA Input Capacitance 2 pF

)

OUT

)

OUT

)

OUT

)

OUT

)

OUT

) 1.6 ns

PWL

) 2.2 ns

PWH

1.0 ns

clocks

Rev. B | Page 6 of 44

AD9959

Parameter Min Typ Max Unit Test Conditions/Comments

CMOS LOGIC OUTPUTS 1 mA load

VOH 2.7 V

VOL 0.4 V

POWER SUPPLY

Total Power Dissipation—All Channels On,

Single-Tone Mode

Total Power Dissipation—All Channels On,

with Sweep Accumulator Total Power Dissipation—Full Power-Down 13 mW I

—All Channels On, Single-Tone Mode 155 180 mA

AVDD

I

—All Channels On, Sweep Accumulator, REFCLK

AVDD

Multiplier and 10-Bit Output Scalar Enabled I

—All Channels On, Single-Tone Mode 105 125 mA

DVDD

I

—All Channels On, Sweep Accumulator, REFCLK

DVDD

Multiplier and 10-Bit Output Scalar Enabled I

40 mA I

DVDD_I/O

30 mA I I

Power-Down Mode 0.7 mA

AVDD

I

Power-Down Mode 1.1 mA

DVDD

DATA LATENCY (PIPELINE DELAY) SINGLE-TONE MODE

Frequency, Phase, and Amplitude Words to DAC

Output with Matched Latency Enabled Frequency Word to DAC Output with Matched

Latency Disabled Phase Offset Word to DAC Output with Matched

Latency Disabled Amplitude Word to DAC Output with Matched

Latency Disabled

DATA LATENCY (PIPELINE DELAY) MODULATION MODE

Frequency Word to DAC Output 34 SYSCLKs

540 635 mW Dominated by supply variation

580 680 mW Dominated by supply variation

160 185 mA

125 145 mA

= read

DVDD

= write

DVDD

2, 3

29 SYSCLKs

25 SYSCLKs

17 SYSCLKs

3, 4

Phase Offset Word to DAC Output 29 SYSCLKs

Amplitude Word to DAC Output 21 SYSCLKs

3, 4

DATA LATENCY (PIPELINE DELAY) LINEAR SWEEP MODE

Frequency Rising/Falling Delta Tuning Word to DAC

41 SYSCLKs

Output Phase Offset Rising/Falling Delta Tuning Word to

37 SYSCLKs

DAC Output Amplitude Rising/Falling Delta Tuning Word to DAC

29 SYSCLKs

Output

1

For the VCO frequency range of 160 MHz to 255 MHz, there is no guarantee of operation.

2

Data latency is referenced to I/O_UPDATE.

3

Data latency is fixed.

4

Data latency is referenced to a profile change.

Rev. B | Page 7 of 44

AD9959

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Maximum Junction Temperature 150°C DVDD_I/O (Pin 49) 4 V AVDD, DVDD 2 V Digital Input Voltage (DVDD_I/O = 3.3 V) −0.7 V to +4 V Digital Output Current 5 mA Storage Temperature Range –65°C to +150°C Operating Temperature Range –40°C to +85°C Lead Temperature (10 sec Soldering) 300°C

θJA 21°C/W θJC 2°C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. B | Page 8 of 44

AD9959

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

3

DVDD46I/O_UPDATE47CS48SCLK49DVDD_I/O50SDIO_051SDIO_152SDIO_253SDIO_354SYNC_CLK

45

P

DGND

44

43

42 P2 41 P1 40 P0 39 AVDD 38 AGND 37 AVDD 36 CH1_IOUT 35 CH1_IOUT 34 AGND 33 AVDD 32 AGND 31 AVDD 30 CH0_IOUT 29 CH0_IOUT

CH3_IOUT

DVDD56DGND

55

PIN 1

1SYNC_IN

INDICATO R

2SYNC_OUT 3MASTER_RESET 4PW R_DWN_CTL 5AVDD 6AGND 7AVDD 8CH2_IOUT

9CH2_IOUT 10AGND 11AVDD 12AGND 13CH3_IOUT 14

AD9959

TOP VIEW

(Not to Scale)

16

15

D

AVD

AGND

NOTES

1. THE EXPO SED EPAD ON BOT TOM SI DE OF PACKAGE I S AN ELECTRICAL CONNECTION AND MUST BE SOLDERED TO GROUND.

2. PIN 49 IS DVDD_I/O AND I S TIED T O 3.3V.

21

17

19

20

22

18

AGND

DAC_RSET

NC = NO CONNECT

24

VDD A

AVDD

AGND

REF_CLK23REF_CLK

CLK_MODE_SEL

25

26

27

28

D

AVDD

AGND

AGN

LOOP_FILTER

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic I/O1 Description

1 SYNC_IN I

Used to Synchronize Multiple AD9959 Devices. Connects to the SYNC_OUT pin of the master AD9959 device.

2 SYNC_OUT O

Used to Synchronize Multiple AD9959 Devices. Connects to the SYNC_IN pin of the slave AD9959 devices.

3 MASTER_RESET I

Active High Reset Pin. Asserting the MASTER_RESET pin forces the AD9959 internal registers to their default state, as described in the Register Maps and Bit Descriptions

section. 4 PWR_DWN_CTL I External Power-Down Control. 5, 7, 11, 15, 19, 21,

AVDD I Analog Power Supply Pins (1.8 V).

26, 31, 33, 37, 39 6, 10, 12, 16, 18, 20,

AGND I Analog Ground Pins.

25, 28, 32, 34, 38 45, 55 DVDD I Digital Power Supply Pins (1.8 V). 44, 56 DGND I Digital Power Ground Pins. 8 CH2_IOUT O True DAC Output. Terminates into AVDD. 9

CH2_IOUT

O Complementary DAC Output. Terminates into AVDD. 13 CH3_IOUT O True DAC Output. Terminates into AVDD. 14

CH3_IOUT

17 DAC_RSET I

O Complementary DAC Output. Terminates into AVDD.

Establishes the Reference Current for All DACs. A 1.91 kΩ resistor (nominal) is connected from Pin 17 to AGND.

22

REF_CLK

I

Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended mode, this pin should be decoupled to AVDD or AGND with a

0.1 μF capacitor.

23 REF_CLK I

Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended mode, this is the input. See the Modes of Operation section for the reference clock configuration.

05246-003

Rev. B | Page 9 of 44

AD9959

Pin No. Mnemonic I/O1 Description

24 CLK_MODE_SEL I

27 LOOP_FILTER I

29

CH0_IOUT

O Complementary DAC Output. Terminates into AVDD.

30 CH0_IOUT O True DAC Output. Terminates into AVDD. 35

CH1_IOUT

O Complementary DAC Output. Terminates into AVDD.

36 CH1_IOUT O True DAC Output. Terminates into AVDD. 40 to 43 P0 to P3 I

46 I/O_UPDATE I

47

CS

I Active Low Chip Select. Allows multiple devices to share a common I/O bus (SPI).

48 SCLK I

49 DVDD_I/O I 3.3 V Digital Power Supply for SPI Port and Digital I/O. 50 SDIO_0 I/O Data Pin SDIO_0 is dedicated to the serial port I/O only. 51, 52 SDIO_1, SDIO_2 I/O

53 SDIO_3 I/O

54 SYNC_CLK O

1

I = input, O = output.

Control Pin for the Oscillator Section. Caution: Do not drive this pin beyond 1.8 V. When high (1.8 V), the oscillator section is enabled to accept a crystal as the REF_CLK source. When low, the oscillator section is bypassed.

Connects to the external zero compensation network of the PLL loop filter. Typically, the network consists of a 0 Ω resistor in series with a 680 pF capacitor tied to AVDD.

Data pins used for modulation (FSK, PSK, ASK), to start/stop the sweep accumulators or used to ramp up/ramp down the output amplitude. The data is synchronous to the SYNC_CLK (Pin 54). The data inputs must meet the setup and hold time requirements of the SYNC_CLK. The functionality of these pins is controlled by the profile pin configuration (PPC) bits (FR1[14:12]).

A rising edge transfers data from the serial I/O port buffer to active registers. I/O_UPDATE is synchronous to the SYNC_CLK (Pin 54). I/O_UPDATE must meet the setup and hold time requirements of the SYNC_CLK to guarantee a fixed pipeline delay of data to the DAC output; otherwise, a ±1 SYNC_CLK period of pipeline uncertainty exists. The minimum pulse width is one SYNC_CLK period.

Serial Data Clock for I/O Operations. Data bits are written on the rising edge of SCLK and read on the falling edge of SCLK.

Data Pin SDIO_1 and Data Pin SDIO_2 can be used for the serial I/O port or used to initiate a ramp-up/ramp-down (RU/RD) of the DAC output amplitude.

Data Pin SDIO_3 can be used for the serial I/O port or to initiate a ramp-up/ramp-down (RU/RD) of the DAC output amplitude. In single-bit or 2-bit modes, SDIO_3 is used for SYNC_I/O. If the SYNC_I/O function is not used, tie to ground or Logic 0. Do not let SDIO_3 float in single-bit or 2-bit modes.

The SYNC_CLK runs at one-fourth the system clock rate; it can be disabled. I/O_UPDATE or data (Pin 40 to Pin 43) is synchronous to the SYNC_CLK. To guarantee a fixed pipeline delay of data to DAC output, I/O_UPDATE or data (Pin 40 to Pin 43) must meet the setup and hold time requirements to the rising edge of SYNC_CLK; otherwise, a ±1 SYNC_CLK period of uncertainty occurs.

Rev. B | Page 10 of 44

AD9959

B

A

B

A

V

A

B

A

B

V

TYPICAL PERFORMANCE CHARACTERISTICS

DELTA 1 (T1) REF LVL 0dBm

0

1

–71.73dB

4.50901804MHz

–10

–20

–30

–40

–50

(dB)

–60

–70

1

–80

–90

–100

START 0Hz STOP 250MHz25MHz/DIV

Figure 4. Wideband SFDR, f

RBW 20kHz RFATT 20d VBW 20kHz SWT 1.6s UNIT dB

= 1.1 MHz, f

OUT

CLK

= 500 MSPS

1AP

REF L

L

0dBm

0

A

1

DELTA 1 (T1) –69.47dB

30.06012024MHz

–10

–20

–30

–40

–50

(dB)

–60

–70

1

–80

–90

05246-004

–100

START 0Hz STOP 250MHz25MHz/DIV

Figure 7. Wideband SFDR, f

RBW 20kHz RF VBW 20kHz SWT 1.6s UNIT dB

= 15.1 MHz, f

OUT

TT 20dB

= 500 MSPS

CLK

A

1AP

05246-007

DELTA 1 (T1)

0

REF LVL 0dBm

1

–62.84dB

40.08016032MHz

–10

–20

–30

–40

–50

(dB)

–60

1

–70

–80

–90

–100

START 0Hz STOP 250Hz25MHz/DIV

Figure 5. Wideband SFDR, f

DELTA 1 (T1) –59.04dB

100.70140281MHz

0

REF LVL 0dBm

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

START 0Hz STOP 250MHz25MHz/DIV

Figure 6. Wideband SFDR, f

RBW 20kHz RF VBW 20kHz SWT 1.6s UNIT dB

= 40.1 MHz, f

OUT

RBW 20kHz RF VBW 20kHz SWT 1. 6s UNIT dB

1

= 100.3 MHz, f

OUT

TT 20d

= 500 MSPS

CLK

TT 20dB

1

= 500 MSPS

CLK

1AP

REF Lv] 0dBm

A

0

DELTA 1 (T1) –60.13dB

75.15030060MHz

1

RBW 20kHz RF VBW 20kHz SWT 1. 6s UNIT dB

TT 20d

A

–10

–20

1AP

–30

–40

–50

(dB)

–60

1

–70

–80

–90

05246-005

A

–100

START 0Hz STOP 250MHz25MHz/DIV

Figure 8. Wideband SFDR, f

–10

REF L 0dBm

0

L

DELTA 1 (T1) –53.84dB –101.20240481MHz

= 75.1 MHz, f

OUT

RBW 20kHz RF VBW 20kHz SWT 1.6s UNIT dB

= 500 MSPS

CLK

TT 20d

1

–20

05246-008

A

1AP

–30

–40

–50

(dB)

–60

1

–70

–80

–90

05246-006

–100

START 0Hz STOP 250MHz25MHz/DIV

Figure 9. Wideband SFDR, f

= 200.3 MHz, f

OUT

= 500 MSPS

CLK

05246-009

Rev. B | Page 11 of 44

AD9959

A

B

V

P

A

V

P

A

B

V

A

V

REF L

L

0dBm

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

CENTER 1.1MHz SPAN 1MHz100kHz/DIV

Figure 10. NBSFDR, ±1 MHz, f

REF L

L

0dBm

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

CENTER 40.1MHz SPAN 1MHz100kHz/DIV

Figure 11. NBSFDR, ±1 MHz, f

DELTA 1 (T1) –84.73dB

254.50901604kHz

DELTA 1 (T1) –84.10dB

120.24048096kHz

RBW 500Hz RF VBW 500Hz SWT 20s UNIT dB

1

= 1.1 MHz, f

OUT

RBW 500Hz RF VBW 500Hz SWT 20s UNI T dB

1

= 40.1 MHz, f

OUT

CLK

1

CLK

TT 20d

1

= 500 MSPS

TT 20dB

= 500 MSPS

REF L 0dBm

A

0

L

DELTA1 (T1) –84.86dB –200.40080160kHz

RBW 500Hz RF VBW 500Hz SWT 20s UNIT dB

1

TT 20d

A

–10

1A

–20

1AP

–30

–40

–50

(dB)

–60

–70

–80

–90

05246-010

–100

CENTER 15.1MHz

Figure 13. NBSFDR, ±1 MHz, f

REF L

L

0dBm

A

0

1

DELTA1 (T1) –86.03dB

262.56513026kHz

= 15.1 MHz, f

OUT

RBW 500Hz RF VBW 500Hz SWT 20s UNI T dB

1

CLK

SPAN 1MHz100kHz/DIV

= 500 MSPS

TT 20dB

05246-013

A

–10

1A

–20

1AP

–30

–40

–50

(dB)

–60

–70

–80

–90

05246-011

–100

CENTER 75.1MHz SPAN 1MHz100kHz/DIV

Figure 14. NBSFDR, ±1 MHz, f

= 75.1 MHz, f

OUT

1

= 500 MSPS

CLK

05246-014

0

REF LVL 0dBm

DELTA 1 (T1) –82.63dB

400.80160321kHz

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

CENTER 100.3MHz SPAN 1MHz100kHz/DI V

Figure 12. NBSFDR, ±1 MHz, f

RBW 500Hz RF ATT 20dB VBW 500Hz SWT 20s UNIT dB

1

= 100.3 MHz, f

OUT

CLK

1

= 500 MSPS

REF LVL 0dBm

A

0

DELTA 1 (T1) –83.72dB –400.80160321kHz

–10

1A

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

05246-012

–100

1

CENTER 200.3MHz SPAN 1MHz

Figure 15. NBSFDR, ±1 MHz, f

RBW 500Hz RF ATT 20dB VBW 500Hz SWT 20s UNIT dB

1

100kHz/DIV

= 200. 3MHz, f

OUT

= 500 MSPS

CLK

A

1AP

05246-015

Rev. B | Page 12 of 44

AD9959

–

100

60

–110

–120

–130

–140

–150

PHASE NOISE (dBc/Hz)

–160

–170

75.1MHz

40.1MHz

15.1MHz

10 100 1k 10k 100k 1M 10M

FREQUENCY OFFSET (Hz)

Figure 16. Residual Phase Noise (SSB) with f

75.1 MHz, 100.3 MHz; f

70

–80

–90

–100

–110

–120

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

–170

10 10M

= 500 MHz with REFCLK Multiplier Bypassed

CLK

100.3MHz

40.1MHz

15.1MHz

100 1k 10k 100k 1M

FREQUENCY O FFSET (Hz)

Figure 17. Residual Phase Noise (SSB) with f

75.1 MHz, 100.3 MHz; f

70

–80

–90

–100

–110

–120

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

–170

10 10M

100 1k 10k 100k 1M

= 500 MHz with REFCLK Multiplier = 5×

CLK

100.3MHz

40.1MHz

15.1MHz

FREQUENCY OFFSET (Hz)

Figure 18. Residual Phase Noise (SSB) with f

75.1 MHz,100.3 MHz; f

= 500 MHz with REFCLK Multiplier = 20×

CLK

75.1MHz

100.3MHz

= 15.1 MHz, 40.1 MHz,

OUT

= 15.1 MHz, 40.1 MHz,

OUT

75.1MHz

= 15.1 MHz, 40.1 MHz,

OUT

–65

–70

–75

CHANNEL ISOLATIO N (dBc)

–80

05246-034

–85

25.3 200.3

50.3 75.3 100.3 125.3 150. 3 175.3

FREQUENCY OF COUPLING SPUR (MHz)

SINGLE DAC PO WER PLANE

SEPARATE DAC POWER PLANES

05246-037

Figure 19. Channel Isolation at 500 MSPS Operation; Conditions are Channel

of Interest Fixed at 110.3 MHz, the Other Channels Are Frequency Swept

600

4 CHANNELS ON

500

400

2 CHANNELS ON

300

1 CHANNEL ON

200

100

TOTAL POWER DI SSIPATION (mW)

05246-035

0

500

450 400 350 300 250 200 150 100 50

3 CHANNELS ON

05246-038

REFERENCE CLO CK FREQUENC Y (MHz)

Figure 20. Power Dissipation vs. Reference Clock Frequency vs. Channel(s)

Power On/Off

45

–50

OUT

(MHz)

SFDR AVERAGED

OUT

05246-045

–55

–60

SFDR (dBc)

–65

–70

05246-036

–75

1.1

15.1 40.1 75.1 100.3 200.3

f

Figure 21. Averaged Channel SFDR vs. f

Rev. B | Page 13 of 44

AD9959

T

A

APPLICATION CIRCUITS

PULSE

AD9959

CH0

FILTER

ANTENN A RADIATING ELEMENTS

CH1

CH2

CH3

REFCLK

FILTER

LO

FILTER

05246-042

Figure 22. Phase Array Radar Using Precision Frequency/Phase Control from DDS in FMCW or Pulsed Radar Applications;

DDS Provides Either Continuous Wave or Frequency Sweep

D8349 AD8348 AD8347 AD8346

RF OUTPU

REFCLK

AD9959

CH2

CH0

CH1

CH3

IMAGE

FREQUENCY

I BASEBAND

LO

LO ±90

DEGREES

ADL5390

Q BASEBAND

05246-043

Figure 23. Single-Sideband-Suppressed Carrier Upconversion

AD9510,AD9511, ADF4106

REFERENCE

÷

PHASE

COMPARATOR

LPF

Figure 24. DDS in PLL Locking to Reference Offering Distribution with Fine Frequency and Delay Adjust Tuning

Rev. B | Page 14 of 44

CHARGE

PUMP

AD9959

REFCLK

LOOP

FILTER

VCO

05249-039

ANALOG DEVICES AD9959 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATION CIRCUITS