Analog Devices AD9929 a Datasheet

CCD Signal Processor with

FEATURES

36 MSPS correlated double sampler (CDS)
12-bit 36 MHz A/D converter
On-chip vertical driver for CCD image sensor
On-chip horizontal driver for CCD image sensor
6 dB to 40 dB variable gain amplifier (VGA)
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with 0.58 ns resolution
2-phase H-clock modes
4-phase vertical transfer clocks
Electronic and mechanical shutter modes
On-chip sync generator with external sync option
64-lead, plastic ball, 9 × 9 grid array Pb-free package

APPLICATION

Digital still cameras
Digital video camcorders

Precision Timing™ Generator

AD9929

PRODUCT DESCRIPTION

The AD9929 is a highly integrated CCD signal processor for
digital still camera and digital video camera applications. It
includes a complete analog front end with A/D conversion,
combined with a full-function, programmable timing generator.
The AD9929 also includes horizontal and vertical clock drivers,
which allow direct connection to the CCD image sensor.

The AD9929 is specified at pixel rates of up to 36 MHz. The
analog front end includes black level clamping, a CDS, a VGA,
and a 12-bit A/D converter. The timing generator provides all
the necessary CCD clocks: RG-clock, H-clocks, V-clocks, sensor
gate pulses, a substrate clock, and a substrate bias pulse. Oper­ation is programmed using a 3-wire serial interface.

The AD9929 is packaged in a 64-lead CSPBGA. It is specified
over an operating temperature range of −25°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

REFT REFB

AD9929

CCDIN

VSUB

RG

H1, H2

V1, V2,

V3, V4

SUBCK

CDS VGA

HORIZONTAL

2

4

DRIVERS

VERTICAL

DRIVERS

6dB TO 40dB

INTERNAL CLOCKS

VREF

PRECISION

TIMING

GENERATOR

SYNC

GENERATOR

HD VD SYNC

Figure 1.

CLAMP

CLI

ADC

INTERNAL

REGISTERS

SL SCKS DI

12

DOUT

DCLK1
FD/DCLK2
MSHUT
STROBE

04593-0-001

Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD9929

TABLE OF CONTENTS

Specifications..................................................................................... 3

Digital Specifications ................................................................... 4

Analog Specifications................................................................... 4

Timing Specifications .................................................................. 5

Vertical Driver Specifications ..................................................... 5

Terminology ...................................................................................... 7

Absolute Maximum Ratings............................................................ 8

Pin Configuration and Functional Descriptions.......................... 9

Equivalent Input Circuits ..............................................................10

System Overview ............................................................................ 18

Theory of Operation ...................................................................... 19

Modes of Operation ................................................................... 19

Horizontal and Vertical Counters ............................................ 19

CLI Input Clock Divider............................................................ 19

Gray Code Registers................................................................... 19

H1 and H2 Blanking .................................................................. 31

VGATE Masking of XV1 to XV4 and CLPOB Outputs............ 33

Vertical Timing Generation.......................................................... 34

Creating Vertical Sequences...................................................... 34

Special Vertical Sweep Mode Operation ................................. 39

Special Vertical Timing (SPATS).............................................. 40

V1 to V4 and SUBCK Output Polarities ..................................... 43

Timing Control............................................................................... 46

Electronic Shutter Timing Control.......................................... 46

VSG Timing ................................................................................ 48

VSUB Timing.............................................................................. 49

MSHUT Timing ......................................................................... 50

Strobe Timing............................................................................. 52

Digital I/O States for Different Operating Conditions.............. 53

Power Supply Sequencing ............................................................. 54

Serial Interface Timing .............................................................. 20

Analog Front End Description and Operation.......................22

Precision Timing, High Speed Timing Generation ............... 23

H Driver and RG Outputs......................................................... 23

Digital Data Outputs.................................................................. 26

External Synchronization (Master Mode)................................... 27

Horizontal and Vertical Synchronous Timing............................ 28

Special Note about the HDLEN Register ................................ 28

Horizontal Clamping and Blanking............................................. 29

Controlling CLPOB Clamp Pulse Timing .............................. 29

Controlling CLPOB Clamp Pulse Outputs............................. 30

REVISION HISTORY

Revision A

2/04—Data Sheet Changed from Rev. 0 to Rev. A

Replaced Figure....................................................................................21

1/04—Revision 0: Initial Version

Recommended Power-Up Supply Sequencing....................... 54

Recommended Power-Down Supply Sequencing ................. 54

Initial Start-Up Sequence.......................................................... 55

Standby Mode Operation.......................................................... 56

Shut-Down Mode Operation.................................................... 57

Applications Where the CLI Clock Frequency Changes

During Operation....................................................................... 58

Circuit Layout Information........................................................... 60

Outline Dimensions....................................................................... 62

Ordering Guide .......................................................................... 62

Rev. A | Page 2 of 64

AD9929

SPECIFICATIONS

Table 1.

Parameter Min Typ Max Unit

TEMPERATURE RANGE

Operating −25 +85 °C
Storage −65 +150 °C

POWER SUPPLY VOLTAGE

AVDD (AFE Analog Supply) 2.7 3.0 3.6 V
TCVDD (Timing Core Analog Supply) 2.7 3.0 3.6 V
RGVDD (RG Driver) 2.7 3.0 3.6 V
HVDD (H1 to H2 Drivers) 2.7 3.0 3.6 V
DRVDD (Data Output Drivers) 2.7 3.0 3.6 V
DVDD (Digital) 2.7 3.0 3.6 V

VERTICAL DRIVER SUPPLY VOLTAGE

VDD (Vertical Driver Input Logic Supply) 2.7 3.0 3.6 V
VH1, VH2 (Vertical Driver High Supply) 11.5 15.0 16.0 V
VM1, VM2 (Vertical Driver Mid Supply) −1.0 0.0 1.0 V
VL (Vertical Driver Low Supply for 3 Level and 2 Level) −9.0 −7.5 −5.0 V

AFETG POWER DISSIPATION

36 MHz, Typ Supply Levels, 100 pF H1 to H2 Loading 180 mW
Power from HVDD Only1 36 mW
Power-down Mode (AFE and Digital in Standby Operation) 1 mW

VERTICAL DRIVER POWER DISSIPATION2 (6000 pF V1 to V4 Loading, 1000 pF SUBCK Loading)

Power from VDD <1.0 mW
Power from VH1 23.0 mW
Power from VH2 15.0 mW
Power from VL 42.0 mW

MAXIMUM CLOCK RATE (CLI) AD9929 36 MHz

1

The total power dissipated by the HVDD supply may be approximated by using the equation:

Total HVDD Power = [C
Actual HVDD power may be slightly different than the calculated value because of the stray capacitance inherent in the PCB layout/routing.

2

Vertical driver loads used when characterizing power consumption. Note: actual power depends on the V1 to V4 timing and number of SUBCKs.

V1, V2, V3, V4

× HVDD × Pixel Frequency] × HVDD × Number of H-Outputs Used.

LOAD

SUBCK

1V MAX

INPUT

1000 pF

6000 pF

INPUT SIGNAL CHARACTERISTICS DEFINED AS FOLLOWS:

500mV TYP

RESET

TRANSIENT

100mV MAX

OPTICAL

BLACK PIXEL

SIGNAL RANGE

04593-0-002

Rev. A | Page 3 of 64

AD9929

DIGITAL SPECIFICATIONS

Table 2. RGVDD = HVDD = 2.7 V to 3.6 V, DVDD = DRVDD = 2.7 V to 3.6 V, CL = 20 pF, T

Parameter Symbol Min Typ Max Unit

LOGIC INPUTS

High Level Input Voltage V
Low Level Input Voltage V
High Level Input Current I
Low Level Input Current I
Input Capacitance C

2.1

IH

IL

IH

IL

IN

LOGIC OUTPUTS (Except H and RG)

High Level Output Voltage @ IOH = 2 mA V
Low Level Output Voltage @ IOL = 2 mA V

2.2

OH

OL

RG and H-DRIVER OUTPUTS (H1 to H2)

High Level Output Voltage @ Max Current V
Low Level Output Voltage @ Max Current V

VDD − 0.5

OH

OL

RG Maximum Output Current (Programmable)
H1 and H2 Maximum Output Current (Programmable)
Maximum Load Capacitance 100

ANALOG SPECIFICATIONS

Table 3. AVDD = 3.0 V, f

Parameter Min Typ Max Unit Notes

CDS

Allowable CCD Reset Transient
Max Input Range before Saturation 1.0
Max CCD Black Pixel Amplitude

VARIABLE GAIN AMPLIFIER (VGA)

Max Output Range 2.0
Gain Control Resolution
Gain Monotonicity
Gain Range

Low Gain
Max Gain

BLACK LEVEL CLAMP

Clamp Level Resolution
Clamp Level

Min Clamp Level
Max Clamp Level

A/D CONVERTER

Resolution 10
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage

VOLTAGE REFERENCE

Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)

SYSTEM PERFORMANCE

Gain Accuracy

Low Gain (VGA Code = 22)

Max Gain (VGA Code = 994)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)

= 36 MHz, T

CLI

MIN

to T

, unless otherwise noted.

MAX

500

±100

mV See input signal characteristics in Table 1.
V p–p
mV

1024
Guaranteed

V p–p
Steps

6
40

dB
dB

255

0
255

Steps

LSB measured at ADC output.

LSB
LSB
LSB

±0.5
Guaranteed

2.0

Bits
LSB

V

2.0

1.0

V
V

6
40

0.1

0.3
40

Gain = (0.035 × Code) + 5.2 dB.

dB
dB
% 12 dB gain applied.
LSB rms AC grounded input, 6 dB gain applied.
dB Measured with step change on supply.

to T

MIN

, unless otherwise noted.

MAX

V

0.6
10
10
10

0.5 V

V

0.5 V

15 mA
30 mA
pF

V

µA
µA
pF

V

Includes entire signal chain.

Rev. A | Page 4 of 64

AD9929

TIMING SPECIFICATIONS

Table 4. CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, f

Parameter Symbol Min Typ Max Unit

MASTER CLOCK, CLI

CLI Clock Period t
CLI High/Low Pulse Width 13.9 ns
Delay from CLI Rising Edge to Internal Pixel Position 0 t

AFE CLAMP PULSES1

CLPOB Pulse Width 4 10 Pixels

AFE SAMPLE LOCATION1 (See Figure 17)

SHP Sample Edge to SHD Sample Edge TS1 20 25 Pixels

DATA OUTPUTS

Output Delay from DCLK1 Rising Edge (See Figure 19) tOD 9 ns
Pipeline Delay from SHP/SHD Sampling (See Figure 70) 9 Cycles

SERIAL INTERFACE (See Figure 10 and Figure 11) tDV

Maximum SCK Frequency f
SL to SCK Setup Time tLS 10 ns
SCK to SL Hold Time tLH 10 ns
SDATA Valid to SCK Rising Edge Setup tDS 10 ns
SCK Falling Edge to SDATA Valid Hold tDH 10 ns
SCK Falling Edge to SDATA Valid Read tOD 10 ns

1

Parameter is programmable.

= 36 MHz, unless otherwise noted.

CLI

27.8 ns

CONV

6 ns

CLIDLY

10 MHz

SCLK

VERTICAL DRIVER SPECIFICATIONS

Table 5. V1 to V4 load = no load, SUBCK load = no load, VDD = 3.0 V, VL = −7.5 V, VH1 = VH2 = +15.0 V, VM1 = VM2 = GND,

= 36 MHz, unless otherwise noted.

f

CLI

Parameter Symbol Min Typ Max Unit

LOGIC INPUTS

High Level Input Voltage VIH 0.8 (VDD) VDD V

Low Level Input Voltage VIL 0 0.3 (VDD) V
Propagation Delays, Rise/Fall Times and Output Currents
V1 and V3 Outputs (See Figure 43)

Delay Times

VL to VM1 t
VM1 to VH1 t
VH1 to VM1 t
VM1 to VL t

Rise Times

VL to VM1 tR1 500 ns
VM1 to VH1 tR2 500 ns

Fall Times

VH1 to VM1 tF1 500 ns
VM1 to VL tF2 500 ns

Output Currents

V1 or V3 @ VL = −7.25 V 10.0 mA
V1 or V3 @ VM1 = −0.25 V −5.0 mA
V1 or V3 @ VM1 = +0.25 V 5.0 mA
V1 or V3 @ VH1 = +14.75 V −7.2 mA

100 ns

PLM1

100 ns

PMH

50 ns

PHM

50 ns

PML1

Rev. A | Page 5 of 64

AD9929

Parameter Symbol Min Typ Max Unit

V2 and V4 Outputs (See Figure 43)

Delay Times

VL to VM2 t
VM2 to VL t

Rise Times

VL to VM2 tR3 500 ns

Fall Times

VM2 to VL tF3 500 ns

Output Currents

V2 or V2 @ VL =−7.25 V 10.0 mA
V2 or V4 @ VM2 = −0.25 V −5.0 mA

SUBCK Output (See Figure 44)

Delay Times

VL to VH2 t
VH2 to VL t

Rise Times

VL to VH2 tR4 90 ns

Fall Times

VH2 to VL tF4 90 ns

Output Currents

SUBCK @ VL = −7.25 V 5.4 mA
SUBCK @ VH2 = 14.75 V −4.0 mA

100 ns

PLM2

50 ns

PML2

100 ns

PLH

50 ns

PHL

Rev. A | Page 6 of 64

AD9929

TERMINOLOGY

Differential Nonlinearity (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. “No missing codes guaranteed to
12-bit resolution” indicates that all 4096 codes, respectively,
must be present over all operating conditions.

Peak Nonlinearity

Peak nonlinearity, a full signal-chain specification, refers to the
peak deviation of the output of the AD9929 from a true straight
line. The point used as zero scale occurs 1/2 LSB before the first
code transition. “Positive full scale” is defined as a level 1 and
1/2 LSB beyond the last code transition. The deviation is mea­sured from the middle of each particular output code to the
true straight line. The error is then expressed as a percentage of
the 2 V ADC full-scale signal. The input signal is always appro­priately gained up to fill the ADC’s full-scale range.

Total Output Noise

The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSBs, and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship
1 LSB = (ADC full scale/2
of the ADC. For the AD9929, 1 LSB is 0.5 mV.

Power Supply Rejection (PSR)

The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.

N

codes) when N is the bit resolution

Rev. A | Page 7 of 64

AD9929

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter With Respect To Min Max Unit

VDD VDVSS VDVSS − 0.3 VDVSS + 4.0 V
VL VDVSS VDVSS − 10.0 VDVSS + 0.3 V
VH1, VH2 VDVSS VL –0.3 VL + 27.0 V
VM1, VM2 VDVSS VL – 0.3 VL + 27.0 V
AVDD AVSS −0.3 +3.9 V
TCVDD TCVSS −0.3 +3.9 V
HVDD HVSS −0.3 +3.9 V
RGVDD RGVSS −0.3 +3.9 V
DVDD DVSS −0.3 +3.9 V
DRVDD DRVSS −0.3 +3.9 V
RG Output RGVSS −0.3 RGVDD + 0.3 V
H1 to H2 Output HVSS −0.3 HVDD + 0.3 V
Digital Outputs DVSS −0.3 DVDD + 0.3 V
Digital Inputs DVSS −0.3 DVDD + 0.3 V
SCK, SL, SDATA DVSS −0.3 DVDD + 0.3 V
REFT, REFB AVSS −0.3 AVDD + 0.3 V
CCDIN AVSS −0.3 AVDD + 0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Package Thermal Resistance

θJA = 61.0 °C/W

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulates on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 8 of 64

AD9929

A

R

A

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

1 CORNE

INDEX ARE

Table 7. Pin Function Descriptions

Pin Mnemonic Type1 Description

D1 VD DIO

Vertical Sync Pulse (Input for Slave
Mode, Output for Master Mode)

Horizontal Sync Pulse (Input for

D2 HD DIO

Slave Mode, Output for Master

Mode)
B8 D0 DO Data Output
A8 D1 DO Data Output
A7 D2 DO Data Output
B7 D3 DO Data Output
A6 D4 DO Data Output
B6 D5 DO Data Output
B5 D6 DO Data Output
A4 D7 DO Data Output
B3 D8 DO Data Output
A3 D9 DO Data Output
B2 D10 DO Data Output
A2 D11 DO Data Output
A1 DCLK1 DO Data Clock Output
B4 DRVSS P Data Output Driver Ground
A5 DRVDD P Data Output Driver Supply

G9 SUBCK DO

D10 V1 DO

E9 V2 DO

G10 V3 DO

H9 V4 DO

H10 VH1 P

C10 VM1 P

F10 VM2 P

CCD Substrate Clock

(2 Level: VH2, VL)

CCD Vertical Transfer Clock

(3 Level: VH1, VM1, VL)

CCD Vertical Transfer Clock

(2 Level: VM2, VL)

CCD Vertical Transfer Clock

(3 Level: VH1, VM1, VL)

CCD Vertical Transfer Clock

(2 Level: VM2, VL)

Vertical Driver High Supply

(High Supply for V1 and V3)

Vertical Driver Midsupply

(Midsupply for V1 and V3)

Vertical Driver Midsupply

(Midsupply for V2 and V4)
F9 VL P Vertical Driver Low Supply

E10 VH2 P

Vertical Driver High Supply for

SUBCK

1

AI = Analog Input, AO = Analog Output, DI = Digital Input,

DO = Digital Output, DIO = Digital Input/Output, P = Power.

12345678910

A
B
C
D
E
F
G
H
J
K

Figure 2. Pin Configuration

AD9929

TOP VIEW

(Not to Scale)

Pin Mnemonic Type1 Description

B10 VDD P Vertical Driver Input Logic Supply
J9 VDVSS P Vertical Driver Ground
A9 VSUB DO CCD Substrate Bias
G1 H1 DO CCD Horizontal Clock
F1 H2 DO CCD Horizontal Clock
E1 HVDD P H1 and H2 Driver Supply
E2 HVSS P H1 and H2 Driver Ground
F2 HVSS P H1 and H2 Driver Ground
G2 HVSS P H1 and H2 Driver Ground
H1 RG DO CCD Reset Gate Clock
J1 RGVDD P RG Driver Supply
H2 RGVSS P RG Driver Ground

C9

C1

K3 AVDD P Analog Supply for AFE
J3 AVSS P Analog Ground for AFE
J4 AVSS P Analog Ground for AFE
J5 AVSS P Analog Ground for AFE
J6 AVSS P Analog Ground for AFE
J7 AVSS P Analog Ground for AFE
J8 AVSS P Analog Ground for AFE
K4 AVSS P Analog Ground for AFE
K6 AVSS P Analog Ground for AFE
J2 CLI DI Reference Clock Input
K2 TCVDD P Analog Supply for Timing Core
K1 TCVSS P Analog Ground for Timing Core
K5 CCDIN AI CCD Input Signal
K7 REFT AO Voltage Reference Top Bypass
K8 REFB AO Voltage Reference Bottom Bypass
K9 SDATA DI 3-Wire Serial Data Input
K10 SL DI 3-Wire Serial Load Pulse
J10 SCK DI 3-Wire Serial Clock
D9 OUTCONT DI Output Control
B1 MSHUT DO Mechanical Shutter Pulse
C2 STROBE DO Strobe Pulse
A10 DVDD P Digital Supply
B9 DVSS P Digital Ground

04593-0-003

SYNC or
VGATE

FD or
DCLK2

DI
DI
DO
DO

External System Sync Input
VGATE Input

Field Designator Output
DCLK2 Output

Rev. A | Page 9 of 64

AD9929

T

EQUIVALENT INPUT CIRCUITS

R

DVDD

DATA

HREE-

STATE

AVDD

AVSS AVSS

Figure 3. Circuit 1. CCDIN

04593-0-004

DRVDD

DOUT

RG, H1 ≠ H2

ENABLE

DVDD

330Ω

DVSS

Figure 5. Circuit 3. Digital Inputs

HVDD OR

RGVDD

04593-0-006

OUTPUT

DVSS

Figure 4. Circuit 2. Digital Data Output

DRVSS

04593-0-005

HVSS OR

RGVSS

Figure 6. Circuit 4. H1 to H2, RG Drivers

04593-0-007

Rev. A | Page 10 of 64

AD9929

Table 8. Control Register Address Map

Bit

Address Content

0x00 (23:0) 24 000000 SW_RESET Software Reset = 000000 (Reset All Registers to Default )
0x01 23 1 0 Unused

(22:21) 2 XSUBCKSUPPRESS

(20:18) 3 0 Unused Test Mode. Should Be Set = 0
17 1 1 HBLKMASK Masking Polarity for H1 During Blanking Period (0 = Low, 1 = High)
16 1 0 SYNCPOL External SYNC Active Polarity (0 = Active Low)
(15:14) 2 0 Unused

13 1 0 XSUBCKMODE_HP

(12:10) 3 0 Unused

(9:8) 2 0 MSHUTPAT

7 1 0 MSHUT/VGATE_EN

6 1 0 Unused
5 1 1 CLPOB_CONT CLPOB Control (0 = CLPOB Off, 1 = CLPOB On)
4 1 1 CLPOB_MODE CLPOB CCD Region Control (See Table 19)
(3:1) 3 0 Unused

0 1 0 VDMODE

0x02 (23:22) 2 0 Unused
(21:16) 6 0x34 SHDLOC SHD Sample Location
(15:14) 2 0 Unused
(13:8) 6 0x18 SHPLOC SHP Sample Location
(7:6) 2 0 DCLKPHASE DCLK Pulse Adjustment
(5:0) 6 0x0B DOUTPHASE Data Output [11:0] Phase Adjustment
0x03 (23:17) 7 0x00 Unused
16 1 0 H1BLKRETIME Retimes the H1 HBLK to Internal Clock
(15:14) 2 0 Unused
(13:8) 6 0x00 H1POSLOC H1 Positive Edge Location
(7:6) 2 0 Unused
(5:0) 6 0x10 RGNEGLOC RG Negative Edge Location
0x04 (23:16) 8 0x80 REFBLACK Black Level Clamp
15 1 – Unused

(14:12) 3 5 H2DRV

11 1 0 Unused

(10:8) 3 5 H1DRV

(7:3) 5 0x00 Unused

(2:0) 3 2 RGDRV

0x05 (23:10) 14 0x0000 Unused
9 1 0 AFESTBY AFE Standby (0 = Standby, 1 = Normal Operation)
8 1 0 DIGSTBY Digital Standby (0 = Standby, 1 = Normal Operation)
(7:2) 6 00 Unused

1 1 0 OUTCONT_REG

0 1 1 OUTCONT_ENB

Width

Default
Value Register Name Register Description

Suppress XSUBCK (00 = No Suppression, 01 = Suppress First XSUBCK
After Last VSG Line Pulse, 10 = Suppress All XSUBCKs, Except Final
XSUBCK, 11 = No Suppression)

High Precision Shutter Mode Operation
(0 = Single Pulse, 1 = Multiple Pulse)

Selects MSHUT Pattern. (See Figure 51)
(0 = Mshutpat0,1 = Mshutpat1,2 = Mshutpat2, 3 = Mshutpat3)

MSHUT Masking of VGATE Input (0 = MSHUT Does Not Mask VGATE,
1 = MSHUT Does Mask VGATE)

VD Synchronous/Asynchronous Mode Setting
(0 = VD Synchronous, 1 = VD Asynchronous )

H2 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA)

H1 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA)

RG Drive Strength (0 = Off, 1 = 2.15 mA, 2 = 4.2 mA, 3 = 6.45 mA,
4 = 8.6 mA, 5 = 10.75 mA, 6 = 12.9 mA, 7 = 15.05 mA)

Internal OUTCONT Signal Control
(0 = Digital Outputs Held at Fixed DC Level, 1 = Normal Operation)

External OUTCONT Signal Input Pin 43 Control (0 = Pin Enabled,
1 = Pin Disabled)

Rev. A | Page 11 of 64

AD9929

Bit

Address Content

0x0A 23 1 0 Unused
22 1 0 FDPOL FD Polarity Control (0 = Low, 1 = High)
(21:16) 6 0x00 XVSGMASK XVSG Masking (See Table 25)
(VD (15:12) 4 0 SYNCCNT External SYNC Setting
SyncReg)1 (11:10) 2 0 SVREP_MODE Super Vertical Repetition Mode
9 1 0 HBLKEXT H Pulse Blanking Extend Control
8 1 0 HPULSECNT H Pulse Control During Blanking
(7:4) 4 C SPATLOGIC SPAT Logic Setting (See Table 27)
(3:2) 2 3 SVOS Second V Output Setting (10 = Ouput Repetition 1)
1 1 0 SPAT_EN SPAT Control (0 = SPAT Disable, 1 = SPAT Enable)
0 1 0 MODE Mode Control Bit (0 = Mode_A, 1 = Mode_B)
0x0B (23:22) 2 0 Unused
21 1 1 XSUBCK_EN XSUBCK Output Enable Control (0 = Disable, 1 = Enable)
20 1 1 XVSG_EN XVSG Output Enable Control (0 = Disable, 1 = Enable)
(VD (19:17) 3 0 Unused
SyncReg)1 16 1 0 STROBE_EN STROBE Output Control (0 = STROBE Output Held Low,
1 = STROBE Output Enabled)
15 1 0 Unused
(14:12) 3 0 XSUBCKNUM_HP High Precision Shutter XSUBCLK Pulse Position/Number
11 1 0 Unused
(10:0) 11 0x7FF XSUBCKNUM Total Number of XSUBCKs Per Field
0x0C (23:21) 3 0 Unused
20 1 0 MSHUTINIT MSHUT Initialize (1 = Forces MSHUT Low)
(19:18) 2 0 Unused
(VD 17 1 0 Unused
SyncReg)1 16 1 0 MSHUTEN MSHUT Control (0 = MSHUT Held at Last State, 1 = MSHUT Output)
15 1 0 Unused
(14:12) 3 0 MSHUTPOS_HP MSHUT Position during High Precision Operation
11 1 0 Unused
(10:0) 11 0x000 MSHUTPOS MSHUT Position during Normal Operation
0x0D (23:17) 7 – Unused
16 1 0 VSUBPOL VSUB Active Polarity (0 = Low, 1 = High)
(VD (15:11) 5 – Unused
SyncReg)1 (10:0) 11 0x000 VSUBTOG VSUB Toggle Position. Active Starting Line in any Field.
0x0E (23:22) 2 0 Unused
(21:20) 2 0 TESTMODE1 This Register Should Always Be Set = 0.
(19:18) 2 0 Unused
(VD 17 1 0 TESTMODE2 This Register Should Always Be Set = 0.
SyncReg)1 16 1 0 TESTMODE3 This Register Should Always Be Set = 0.
(15:10) 6 0x00 Unused
(9:0) 10 0x000 VGAGAIN VGA Gain
0x0F (23:8) 16 0 Unused
(7:0) 8 60 XVSGLEN_1 XVSGTOG_1 Pulse Width
0x17 (23:13) 11 – Unused
(12:0) 13 0x1FFF XV1SPAT_TOG1 XV1SPAT Toggle Position #1 (Mode_A Active)
0x18 (23:13) 11 – Unused
(12:0) 13 0x1FFF XV1SPAT_TOG2 XV1SPAT Toggle Position #2 (Mode_A Active)
0x19 (23:13) 11 – Unused
(12:0) 13 0x1FFF XV2SPAT_TOG1 XV2SPAT Toggle Position #1 (Mode_A Active)
0x1A (23:13) 11 – Unused
(12:0) 13 0x1FFF XV2SPAT_TOG2 XV2SPAT Toggle Position #2 (Mode_A active)

Width

Default
Value Register Name Register Description

Rev. A | Page 12 of 64

AD9929

Bit

Address Content

Width

0x1B (23:13) 11 – Unused
(12:0) 13 0x1FFF XV3SPAT_TOG1 XV3SPAT Toggle Position #1 (Mode_A active)
0x1C (23:13)) 11 – Unused
(12:0 13 0x1FFF XV3SPAT_TOG2 XV3SPAT Toggle Position #2 (Mode_A active)
0x1D (23:13) 11 – Unused
(12:0) 13 0x1FFF XV4SPAT_TOG1 XV4SPAT Toggle Position #1 (Mode_A active)
0x1E (23:13) 11 – Unused
(12:0) 13 0x1FFF XV4SPAT_TOG2 XV4SPAT Toggle Position #2 (Mode_A Active)
0x1F (23:13) 11 – Unused
(12:0) 13 0x1FFF XV1SPAT_TOG1 XV1SPAT Toggle Position #1 (Mode_A Active)
0x20 (23:13) 11 – Unused
(12:0) 13 0x1FFF XV1SPAT_TOG2 XV1SPAT Toggle Position #2 (Mode_B Active)
0x21 (23:13) 11 – Unused
(12:0) 13 0x1FFF XV2SPAT_TOG1 XV2SPAT Toggle Position #1 (Mode_B Active)
0x22 (23:13) 11 – Unused
(12:0) 13 0x1FFF XV2SPAT_TOG2 XV2SPAT Toggle Position #2 (Mode_B Active)
0x23 (23:13) 11 – Unused
(12:0) 13 0x1FFF XV3SPAT_TOG1 XV3SPAT Toggle Position #1 (Mode_B Active)
0x24 (23:13) 11 – Unused
(12:0) 13 0x1FFF XV3SPAT_TOG2 XV3SPAT Toggle Position #2 (Mode_B Active)
0x25 (23:13) 11 – Unused
(12:0) 13 0x1FFF XV4SPAT_TOG1 XV4SPAT Toggle Position #1 (Mode_B Active)
0x26 (23:13) 11 – Unused
(12:0) 13 0x1FFF XV4SPAT_TOG2 XV4SPAT Toggle Position #2 (Mode_B Active)
0xD5 (23:4) 20 0x00000 Unused

3 1 1 DCLK2SEL

2 1 0 DCLK1SEL

(1:0) 2 0 CLKDIV Input Clock Divider (0 = No Division, 1 = 1/2, 2 = 1/3, 3 = 1/4)
0xD6 (23:1) 23 0x000000 Unused
0 1 1 SLAVE_MODE Operating Mode ( 0 = Master Mode, 1 = Slave Mode)

1

This register defaults to VD synchronous mode type at power-up. VD sync type registers do not get updated until the first falling edge of VD is asserted after the

register has been programmed. VD sync type registers can be programmed to be asynchronous registers by setting VDMODE = 1 (Address 0x01).

Default
Value Register Name Register Description

DCLK2 Selector (0 = Select Internal FD Signal To Be Output on
FD/DCLK2 Pin 16, 1 = Select CLI To Be Output on FD/DCLK2 Pin 16)

DCLK1 Selector (0 = Select DLL Version for DCLK1 Output, 1 = Select
CLI for DCLK1 Output)

Rev. A | Page 13 of 64

AD9929

Table 9. System Register Address Map (Address 0x14)

Bit

Register Content

Sys_Reg(0) (31:24) 8 NA System_Reg_addr System Register Address is (Address 0x14)

Sys_Reg(1) (31:23) 9 37 VTPLEN0 Vertical Sequence #0: Length Between Repetitions

Sys_Reg(2) (31:24) 8 12 XV2TOG1POS0 [7:0] Vertical Sequence #0: XV2 Toggle Position 1

Sys_Reg(3) (31:29) 3 19 XV3TOG2POS0 [2:0] Vertical Sequence #0: XV3 Toggle Position 2

Sys_Reg(4) 31 1 1 XV3STARTPOL1 Vertical Sequence #1: XV3 Start Polarity

Sys_Reg(5) (31:26) 6 96 XV2TOG2POS1 [5:0] Vertical Sequence #1: XV2Toggle Position 2

Sys_Reg(6) 31 1 38 XV4TOG1POS1 [0] Vertical Sequence #1: XV4 Toggle Position 1

Sys_Reg(7) (31:23) 9 29 XV1TOG2POS2 Vertical Sequence #2: XV1 Toggle Position 2

Sys_Reg(8) (31:28) 4 0 XV3TOG1POS2 [3:0] Vertical Sequence #2: XV3 Toggle Position 1

(23:0) 24 NA System_Number_N

22 1 0 XV1STARTPOL0 Vertical Sequence #0: XV1 Start Polarity
21 1 0 XV2STARTPOL0 Vertical Sequence #0: XV2 Start Polarity
20 1 1 XV3STARTPOL0 Vertical Sequence #0: XV3 Start Polarity
19 1 1 XV4STARTPOL0 Vertical Sequence #0: XV4 Start Polarity
(18:10) 9 0 XV1TOG1POS0 Vertical Sequence #0: XV1 Toggle Position 1

(9:1) 9 19

0 1 0 XV2TOG1POS0 [8]

(23:15) 9 31 XV2TOG2POS0 Vertical Sequence #0: XV2 Toggle Position 2
(14:6) 9 0 XV3TOG1POS0 Vertical Sequence #0: XV3 Toggle Position 1
(5:0) 6

(28:20) 9 12 XV4TOG1POS0 Vertical Sequence #0: XV4 Toggle Position 1
(19:11) 9 31 XV4TOG2POS0 Vertical Sequence #0: XV4 Toggle Position 2
(10:2) 9 104 VTPLEN1 Vertical Sequence #1: Length Between Repetitions
1 1 0 XV1STARTPOL1 Vertical Sequence #1: XV1 Start Polarity
0 1 0 XV2STARTPOL1 Vertical Sequence #1: XV2 Start Polarity

30 1 1 XV4STARTPOL1 Vertical Sequence #1: XV4 Start Polarity
(29:21) 9 18 XV1TOG1POS1 Vertical Sequence #1: XV1 Toggle Position 1
(20:12) 9 58 XV1TOG2POS1 Vertical Sequence #1: XV1 Toggle Position 2
(11:3) 9 47 XV2TOG1POS1 Vertical Sequence #1: XV2 Toggle Position 1
(2:0) 3

(25:17) 9 0 XV3TOG1POS1 Vertical Sequence #1: XV3 Toggle Position 1
(16:8) 9 76 XV3TOG2POS1 Vertical Sequence #1: XV3 Toggle Position 2
(7:0) 8

(30:22) 9 105 XV4TOG2POS1 Vertical Sequence #1: XV4 Toggle Position 2
(21:13) 9 57 VTPLEN2 Vertical Sequence #2: Length between Repetitions
12 1 0 XV1STARTPOL2 Vertical Sequence #2: XV1 Start Polarity
11 1 0 XV2STARTPOL2 Vertical Sequence #2: XV2 Start Polarity
10 1 1 XV3STARTPOL2 Vertical Sequence #2: XV3 Start Polarity
9 1 1 XV4STARTPOL2 Vertical Sequence #2: XV4 Start Polarity
(8:0) 9 0 XV1TOG1POS2 Vertical Sequence #2: XV1 Toggle Position 1

(22:14) 9 19 XV2TOG1POS2 Vertical Sequence #2: XV2 Toggle Position 1
(13:5) 9 48 XV2TOG2POS2 Vertical Sequence #2: XV2 Toggle Position 2
(4:0) 5

(27:19) 9 29 XV3TOG2POS2 Vertical Sequence #2: XV3 Toggle Position 2
(18:10) 9 19 XV4TOG1POS2 Vertical Sequence #2: XV4 Toggle Position 1
(9:1) 9 48 XV4TOG2POS2 Vertical Sequence #2: XV4 Toggle Position 2
0 1 – Unused

Width

Default
(Decimal)

Register Name Register Description

Number N Register Writes (0x000000 = Write All
Registers)

XV1TOG2POS0 Vertical
Sequence

XV3TOG2POS0 [8:3]

XV2TOG2POS1 [8:6]

XV4TOG1POS1 [8:1]

XV3TOG1POS2 [8:4]

#0: XV1 Toggle Position 2

Rev. A | Page 14 of 64

AD9929

Bit

Register Content

Width

Sys_Reg(9) (31:23) 9 89 VTPLEN3 Vertical Sequence #3: Length Between Repetitions

22 1 0 XV1STARTPOL3 Vertical Sequence #3: XV1 Start Polarity
21 1 0 XV2STARTPOL3
20 1 1 XV3STARTPOL3 Vertical Sequence #3: XV3 Start Polarity
19 1 1 XV4STARTPOL3 Vertical Sequence #3: XV4 Start Polarity
(18:10) 9 0 XV1TOG1POS3 Vertical Sequence #3: XV1 Toggle Position 1
(9:1) 9 60 XV1TOG2POS3 Vertical Sequence #3: XV1 Toggle Position 2
0 1

Sys_Reg(10) (31:24) 8 30 XV2TOG1POS3 [7:0] Vertical Sequence #3: XV2 Toggle Position 1

(23:15) 9 90 XV2TOG2POS3 Vertical Sequence #3: XV2 Toggle Position 2
(14:6) 9 0 XV3TOG1POS3 Vertical Sequence #3: XV3 Toggle Position 1
(5:0) 6

Sys_Reg(11) (31:29) 3 60 XV3TOG2POS3 [2:0] Vertical Sequence #3: XV3 Toggle Position 2

(28:20) 9 30 XV4TOG1POS3 Vertical Sequence #3: XV4 Toggle Position 1
(19:11) 9 90 XV4TOG2POS3 Vertical Sequence #3: XV4 Toggle Position 2
(10:1) 10 0 HBLKHPOS H1 Pulse ON Position during Blanking Period
0 1 – Unused

Sys_Reg(12) (31:20) 12 2283 HDLEN

(19:10) 10 130 HLEN 10-Bit HL Counter Values
(9:1) 9 100 OLEN 9-Bit OL Counter Value
0 1

Sys_Reg(13) (31:24) 8 0 BLLEN [7:0] 9-bit BL Counter Value

(23:16) 8 118 MSHUTLEN MSHUT Sequence Length
(15:5) 11 1048 XVSGTOG_0 XVSGTOG_0 Toggle Position
(4:0) 5

Sys_Reg(14) (31:26) 6 1198 XVSGTOG_1 [5:0] XVSG TOG_1 Toggle Position

(25:18) 8 60 XVSGLEN_0 XVSGTOG_0 Pulse Width
(17:9) 9 19 XSUBCK1TOG1 XSUBCK1 1st Toggle Position
(8:0) 9 88 XSUBCK1TOG2 XSUBCK1 2nd Toggle Position

Sys_Reg(15) (31:23) 9 19 XSUBCK2TOG1 XSUBCK2 1st Toggle Position

(22:14:) 9 88 XSUBCK2TOG2 XSUBCK2 2nd Toggle Position
(13:2) 12 2243 CLPTOG1
(1:0) 2

Sys_Reg(16) (31:22) 10 2278 CLPTOG2 [10:0]

(21:18) 4 9 VDRISE VD Toggle Position 1
(17:8) 10 120 HDRISE HD Toggle Position 2
(7:0) 8 – Unused

1

Register value must be a gray code number (see Gray Code Registers section).

Default
(Decimal)

Register Name Register Description

Vertical Sequence #3: XV2 Start Polarity

XV2TOG1POS3 [8]

XV3TOG2POS3 [8:3]

1

BLLEN [8]

XVSGTOG_1 [10:6]

1

CLPOB Toggle Position 1 (Gray Code Number)

1

CLPTOG2 [11]

1

CLPOB Toggle Position 2 (Gray Code Number)

12-bit Gray Code HD Counter Value
(Gray Code Number)

Rev. A | Page 15 of 64

AD9929

Table 10. Mode_A Register Map (Address 0x15)

Register Content

Mode_Reg(0) (31:24) 8 NA Mode_A_addr Mode_A Address Is (Address 0x15)
(23:0) 24 NA Mode_A_Number_N Number N Register Writes (0x000000 = Write All Registers )
Mode_Reg(1) (31:21) 11 262 VDLEN VD Counter Value
(20:9) 12 1139 HDLASTLEN1 Number of Pixels in Last Line (Gray Code Number)
8 1 1 XVSGSEL1
7 1 0 XVSGSEL2
(6:0) 7 0 XVSGACTLINE XVSG Active Line
Mode_Reg(2) 31 1 0 SUBCKSEL Select one of two SUBCK patterns
(30:28) 3 0 VTPSEQPTR0 Vertical Transfer Sequence Region 0
(27:25) 3 0 VTPSEQPTR1 Vertical Transfer Sequence Region 1
(24:22) 3 0 VTPSEQPTR2 Vertical Transfer Sequence Region 2
(21:19) 3 0 VTPSEQPTR3 Vertical Transfer Sequence Region 3
(18:16) 3 0 VTPSEQPTR4 Vertical Transfer Sequence Region 4
15 1 1 CLPEN0 CLPOB Output Control 1
14 1 0 CLPEN1 CLPOB Output Control 2
13 1 0 CLPEN2 CLPOB Output Control 3
12 1 0 CLPEN3 CLPOB Output Control 4
11 1 0 CLPEN4 CLPOB Output Control 5
(10:3) 8 0 SCP1 Sequence Change Position 1
(2:0) 3 SCP2
Mode_Reg(3) (31:27) 5 0 SCP2 Sequence Change Position 2
(26:19) 8 0 SCP3 Sequence Change Position 3
(18:11) 8 0 SCP4 Sequence Change Position 4
(10:9) 2 0 VTPSEL0 Vertical Pattern Selection 0
(8:7) 2 0 VTPSEL1 Vertical Pattern Selection 1
(6:5) 2 0 VTPSEL2 Vertical Pattern Selection 2
(4:3) 2 0 VTPSEL3 Vertical Pattern Selection 3
(2:0) 3 3 VTPREP0 Number of Vertical Pulse Repetitions for Pattern 0
Mode_Reg(4) (31:29) 3 0 VTPREP1 Number of Vertical Pulse Repetitions for Pattern 1
(28:26) 3 0 VTPREP2 Number of Vertical Pulse Repetitions for Pattern 2
(25:23) 3 0 VTPREP3 Number of Vertical Pulse Repetitions for Pattern 3
(22:12) 11 0 SVREP0 Vertical Sweep Repetition Number for CCD Region 0
(11:1) 11 0 SVREP3 Vertical Sweep Repetition Number for CCD Region 3
0 1 – Unused
Mode_Reg(5) (31:19) 13 988 XV1SPAT_TOG3 XV1SPAT Toggle Position 3
(18:6) 13 1138 XV1SPAT_TOG4 XV1SPAT Toggle Position 4
(5:0) 6 XV2SPAT_TOG3
Mode_Reg(6) (31:25) 7 1078 XV2SPAT_TOG3 XV2SPAT Toggle Position 3
(24:12) 13 1168 XV2SPAT_TOG XV2SPAT Toggle Position 4
(11:0) 12 XV3SPAT_TOG3
Mode_Reg(7) 31 1 958 XV3SPAT_TOG3 XV3SPAT Toggle Position 3
(30:18) 13 1138 XV3SPAT_TOG4 XV3SPAT Toggle Position 4
(17:5) 13 988 XV4SPAT_TOG3 XV4SPAT Toggle Position 3
(4:0) 5 XV4SPAT_TOG4
Mode_Reg(8) (31:24) 8 1228 XV4SPAT_TOG4 XV4SPAT Toggle Position 4
(23:11) 13 1392 SECONDVPOS Second V Pattern Output Position
(10:9) 2 3 VPATSECOND Selected Second V-Pattern Group for VSG Active Line
(8:0) 9 – Unused

Bit
Width

1

Register value must be a gray code number (see Gray Code Registers section).

Default
(Decimal) Register Name Register Description

XVSG1 Sequence Selector (See
XVSG2 Sequence Selector (See

Table 35)

Table 35)

Rev. A | Page 16 of 64

AD9929

Table 11. Mode_B Register Map (Address 0x16)

Bit

Register Content

Width

Mode_Reg(0) (31:24) 8 NA Mode_B_addr Mode_B Address is (Address 0x16)
(23:0) 24 NA Mode_B_Number_N Number N Register Writes (0x000000 = Write All Registers)
Mode_Reg(1) (31:21) 11 262 VDLEN VD Counter Value
(20:9) 12 1139 HDLASTLEN1 Number of Pixels in Last Line (Gray Code Number)
8 1 1 XVSGSEL1 XVSG1 Sequence Selector (See Table 35)
7 1 0 XVSGSEL2 XVSG2 Sequence Selector (See Table 35)
(6:0) 7 0 XVSGACTLINE XVSG Active Line
Mode_Reg(2) 31 1 0 SUBCKSEL Select One of Two SUBCK Patterns
(30:28) 3 0 VTPSEQPTR0 Vertical Transfer Sequence Region 0
(27:25) 3 0 VTPSEQPTR1 Vertical Transfer Sequence Region 1
(24:22) 3 0 VTPSEQPTR2 Vertical Transfer Sequence Region 2
(21:19) 3 0 VTPSEQPTR3 Vertical Transfer Sequence Region 3
(18:16) 3 0 VTPSEQPTR4 Vertical Transfer Sequence Region 4
15 1 1 CLPEN0 CLPOB Output Control 1
14 1 0 CLPEN1 CLPOB Output Control 2
13 1 0 CLPEN2 CLPOB Output Control 3
12 1 0 CLPEN3 CLPOB Output Control 4
11 1 0 CLPEN4 CLPOB Output Control 5
(10:3) 8 0 SCP1 Sequence Change Position 1
(2:0) 3 SCP2
Mode_Reg(3) (31:27) 5 0 SCP2 Sequence Change Position 2
(26:19) 8 0 SCP3 Sequence Change Position 3
(18:11) 8 0 SCP4 Sequence Change Position 4
(10:9) 2 0 VTPSEL0 Vertical Pattern Selection 0
(8:7) 2 0 VTPSEL1 Vertical Pattern Selection 1
(6:5) 2 0 VTPSEL2 Vertical Pattern Selection 2
(4:3) 2 0 VTPSEL3 Vertical Pattern Selection 3
(2:0) 3 3 VTPREP0 Number of VTP0 Pulse Repetitions for Pattern 0
Mode_Reg(4) (31:29) 3 0 VTPREP1 Number of VTP1 Pulse Repetitions for Pattern 1
(28:26) 3 0 VTPREP2 Number of VTP2 Pulse Repetitions for Pattern 2
(25:23) 3 0 VTPREP3 Number of VTP0 Pulse Repetitions for Pattern 3
(22:12) 11 0 SVREP0 Vertical Sweep Repetition Number for CCD Region 0
(11:1) 11 0 SVREP3 Vertical Sweep Repetition Number for CCD Region 3
0 1 – Unused
Mode_Reg(5) (31:19) 13 988 XV1SPAT_TOG3 XV1SPAT Toggle Position 3
(18:6) 13 1138 XV1SPAT_TOG4 XV1SPAT Toggle Position 4
(5:0) 6 XV2SPAT_TOG3
Mode_Reg(6) (31:25) 7 1078 XV2SPAT_TOG3 XV2SPAT Toggle Position 3
(24:12) 13 XV2SPAT_TOG4 XV2SPAT Toggle Position 4
(11:0) 12 XV3SPAT_TOG3
Mode_Reg(7) 31 1 958 XV3SPAT_TOG3 XV3SPAT Toggle Position 3
(30:18) 13 1138 XV3SPAT_TOG4 XV3SPAT Toggle Position 4
(17:5) 13 988 XV4SPAT_TOG3 XV4SPAT Toggle Position 3
(4:0) 5 XV4SPAT_TOG4
Mode_Reg(8) (31:24) 8 1228 XV4SPAT_TOG4 XV4SPAT Toggle Position 4
(23:11) 13 1392 SECONDVPOS Second V Pattern Output Position
(10:9) 2 3 VPATSECOND Selected Second V-Pattern Group for VSG Active Line
(8:0) 9 – Unused

1

Register value must be a gray code number (See Gray Code Registers section).

Default
(Decimal) Register Name Register Description

Rev. A | Page 17 of 64

AD9929

SYSTEM OVERVIEW

Figure 7 shows the typical system block diagram for the
AD9929. The CCD output is processed by the AD9929’s AFE
circuitry, which consists of a CDS, VGA, black level clamp, and
an A/D converter. The digitized pixel information is sent to the
digital image processor chip, which performs post-processing
and compression. To operate the CCD, all CCD timing para­meters are programmed into the AD9929 from the system
microprocessor through the 3-wire serial interface. From the
system master clock, CLI, provided by the image processor or
external crystal, the AD9929 generates all of the CCDs hori­zontal and vertical clocks and all internal AFE clocks. External
synchronization is provided by a SYNC pulse from the

CCD

CCDIN

SUBCK

V1
V2
V3
V4

VERTICAL

DRIVER

AD9929

XVSG1
XVSG2

XSUBCK

microprocessor, which resets internal counters and resyn­chronizes the VD and HD outputs.

The H-drivers for H1 to H2, and RG are included in the
AD9929, allowing these clocks to be directly connected to the
CCD. An H-drive voltage of up to 3.6 V is supported. The
AD9929 also includes the CCD vertical driver circuits for
creating the V1 to V4, and SUBCK outputs that allow direct
connection to the CCD. The AD9929 also provides program­mable MSHUT and STROBE outputs, which may be used to
trigger mechanical shutter and strobe (flash) circuitry.

XV1
XV2
XV3
XV4

TIMING

GENERATOR

DOUT [11:0]

DCLK1

FD

HD, VD

VGATE

CLI

DIGITAL

IMAGE

PROCESSING

ASIC

H1
H2

RG

VSUB

SYNC

SERIAL

Figure 7. Typical System Block Diagram, Master Mode

INTERFACE

µP

OUTCONT

MSHUT

STROBE

04593-0-008

Rev. A | Page 18 of 64

AD9929

THEORY OF OPERATION

MODES OF OPERATION

Slave and Master Mode Operation

The AD9929 can be operated in either slave or master mode.
It defaults to slave mode operation at power-up. The
SLAVE_MODE register (Address 0xD6) can be used to
configure the AD9929 into master mode by setting
SLAVE_MODE = 0.

Slave Mode Operation

While operating in slave mode, VD, HD, and VGATE are pro­vided externally from the image processor. VGATE is input
active high on Pin 45.

Unlike master mode operation, there is a 7 CLI clock cycle delay
from the falling edge of HD to when the 12-bit gray code H
counter is reset to 0 (See Figure 62).

Master Mode Operation

While operating in master mode, VD and HD are outputs
and the SYNC/VGATE pin is configured for an external
SYNC input. Master mode is selected by setting register
SLAVE_MODE (Address 0x06) = 0.

HORIZONTAL AND VERTICAL COUNTERS

Figure 8 and Figure 9 show the horizontal and vertical counter
dimensions for the AD9929. All internal horizontal and vertical
clocking is programmed using these dimensions to specify line
and pixel locations.

CLI INPUT CLOCK DIVIDER

The AD9929 provides the capability of dividing the CLI input
clock using Register CLKDIV (Address 0xD5). The following
procedure must be followed to reset the AFE and digital circuits
when CLKDIV is reprogrammed back to 0 from CLKDIV = 1,
2, or 3. The DCLK1 output becomes unstable if this procedure
isn’t followed.

Step 1: CLKDIV = 1, 2, or 3 (CLI divided by setting value)
Step 2: CLKDIV = 0 (CLI reprogrammed for no division)
Step 3: DIGSTBY = AFESTBY = 0
Step 4: DIGSTBY = AFESTBY = 1

MAX VD LENGTH IS 2048 LINES

MAXIMUM FIELD DIMENSIONS

12-BIT HORIZONTAL COUNTER = 4096 PIXELS MAX

11-BIT VERTICAL COUNTER = 2048 LINES MAX

Figure 8. Horizontal and Vertical Counters

GRAY CODE REGISTERS

See Table 12 for a list of the AD9929 registers requiring gray
code values. The following is an example of applying a gray
code number for HDLEN using a line length of 1560 pixels:

HDLEN = (1560–4) = 1556
HDLEN Register section).

Where 1556

= Address 0x51E

10

The gray code value of Address 0x51E would be programmed in
the 12-bit HDLEN register.

Table 12. AD9929 Gray Code Registers

Register Name Register Type

HDLEN System_Reg(12)
CLPOBTOG1 System_Reg(15)
CLPOBTOG2 System_Reg(16)
HDLASTLEN Mode_Reg(1)

(see Special Note about the

10

04593-0-009

VD

HD

CLI

MAX HD LENGTH IS 4095 PIXELS

Figure 9. Maximum VD/HD Dimensions

04593-0-010

Rev. A | Page 19 of 64

AD9929

S

A

SERIAL INTERFACE TIMING

All of the internal registers of the AD9929 are accessed through
a 3-wire serial interface. The 3-wire interface consists of a clock
(SCK), serial load (SL), and serial data (SDATA).

The AD9929 has three different register types that are confi­gured by the 3-wire serial interface. As described in Table 13,
the three register types are control registers, system registers,
and mode registers.

Table 13. Types of Serial Interface Registers

Register Address Number of Registers

Control

0x00 to
0xD6

System 0x14

Mode_A 0x15

Mode_B 0x16

Registers

Control Register Serial Interface

The control register 3-wire interface timing requirements are
shown in Figure 10. Control data must be written into the
device one address at a time due to the noncontiguous address
spacing for the control registers. This requires writing 8 bits of
address data followed by 24 bits of configuration data between
each active low period of SL for each address. The SL signal
must be kept high for at least one full SCK cycle between
successive writes to control registers.

System Register Serial Interface

There are seventeen 32-bit system registers that are accessed
sequentially at Address 0x14, beginning with Sys_Reg [0]. When

24-Bit Registers at Each Address. Not All
Addresses Are Used. See Table 8.

Seventeen 32-Bit System Registers at
Address 0x14. See Table 9.

Eight 32-bit Mode_A Registers at Address
0x15. See Table 10.

Eight 32-Bit Mode_B Registers at Address
0x16. See Table 11.

writing to the system registers, SDATA contains the 8-bit
Address 0x14, followed by Number Writes N [23:0], followed by
the Sys_Reg [31:0] data, as shown in Figure 5. The system
register map is listed in Table 9.

The value of the Number Writes N [23:0] word determines one
of two options when writing to the system registers. If Number
Writes N[23:0] = 0x000000, the device enters a mode where it
expects all 17 Sys_Reg [31:0] data-words to be clocked in before
SL is asserted high. If the Number Writes N [23:0] is decoded as
some number N other than 0x000000, then the device expects
N number of registers to be programmed, where N equals the
value of Number Writes N [23:0]. For example: if Number
Writes N[23:0] = 0x000004, the device would expect data to be
provided for Sys_Reg [3:0]. In all cases, the system registers are
written beginning with Sys_Reg [0], regardless of the value of
Number Writes N [23:0]. Note that SL can be brought high or
low during access to system registers, as shown in Figure 11.

Mode_A and Mode_B Register Serial Interface

There are eight 32-bit Mode_A and eight 32-bit Mode_B
registers that get accessed sequentially at Address 0x15 and
Address 0x16, respectively. Mode_A and Mode_B registers are
written to in exactly the same way as the system registers, as
explained previously. The mode registers are listed in Table 10
and Table 11.

To change operation between Mode_A and Mode_B, set the
1-bit mode register (Address 0x0A). The desired Mode_A
(Address 0x15) or Mode_B (Address 0x16) data must be
programmed into the Mode_A or Mode_B registers before
changing the mode bit.

DAT

SCK

SL

A7 A4 A3 A2 A1 A0

t

DS

1234567891011 29303132

t

NOTES

1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.

2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.

3. THIS TIMING PATTERN MUST BE WRITTEN FOR EACH REGISTER WRITE WITH SL REMAINING HIGH FOR AT
LEAST ONE FULL SCK PERIOD BEFORE ASSERTING SL LOW AGAIN FOR THE NEXT REGISTER WRITE.

A5A6 D22 D21 D3 D2 D1

t

DH

LS

Figure 10. 3-Wire Serial Interface Timing for Control Registers

Rev. A | Page 20 of 64

D23

....

....

D0

t

LH

04593-0-011