ANALOG DEVICES AD9923A Service Manual

CCD Signal Processor with V-Driver and

V

V

FEATURES

Integrated 15-channel V-driver
12-bit, 36 MHz analog-to-digital converter (ADC)
Similar register map to the AD9923
5-field, 10-phase vertical clock support
Complete on-chip timing generator
Precision Timing core with <600 ps resolution
Correlated double sampler (CDS)
6 dB to 42 dB 10-bit variable gain amplifier (VGA)
Black level clamp with variable level control
On-chip 3 V horizontal and RG drivers
2-phase and 4-phase H-clock modes
Electronic and mechanical shutter support
On-chip driver for external crystal
On-chip sync generator with external sync input
8 mm × 8 mm CSP_BGA package with 0.65 mm pitch

APPLICATIONS

Digital still cameras

Precision Timing Generator

AD9923A

GENERAL DESCRIPTION

The AD9923A is a complete 36 MHz front-end solution for
digital still cameras and other CCD imaging applications.
Similar to the AD9923 product, the AD9923A includes the
analog front end (AFE), a fully programmable timing generator
(TG), and a 15-channel vertical driver (V-driver). A Precision
Timi ng™core allows adjustment of high speed clocks with
approximately 600 ps resolution at 36 MHz operation.

The on-chip V-driver supports up to 15 channels for use with
5-field, 10-phase CCDs.

The analog front end includes black level clamping, CDS, VGA,
and a 12-bit ADC. The timing generator and V-driver provide
all the necessary CCD clocks: RG, H-clocks, vertical clocks, sensor
gate pulses, substrate clock, and substrate bias control. The
internal registers are programmed using a 3-wire serial
interface.

Packaged in an 8 mm × 8 mm CSP_BGA, the AD9923A is
specified over an operating temperature range of −25°C to +85°C.

CCDIN

RG

H1 TO H4

V1, V2, V3,
4, V5A, V5B,
6, V7A, V7B,

V8, V9, V10,

V11, V12, V13

–3dB, 0dB, +3dB, +6d B

CDS

HL

4

15

V-DRIVER

SUBCK

HORIZONT AL

DRIVERS

XV1 TO

XSG1 TO

XSUBCK,

XSUBCNT

FUNCTIONAL BLOCK DIAGRAM

REFT REFB

+6dB TO +42d B

13

XV13

8

XSG8

2

VGA

VERTICAL

TIMING

CONTROL

3

STROBE

INTERNAL CLOCKS

HD

Figure 1.

VREF

PRECISION

TIMING

GENERATOR

SYNC

GENERATOR

VD SYNC CLI CLOVSUB, MSHUT,

12-BIT

ADC

CLAMP

AD9923A

INTERNAL

REGIS TERS

12

D0 TO D11

DCLK

SL

SDI

SCK

05586-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2010 Analog Devices, Inc. All rights reserved.

AD9923A

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 14

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Digital Specifications ................................................................... 4

H-Driver Specifications ............................................................... 4

Vertical Driver Specifications ..................................................... 4

Analog Specifications ................................................................... 5

Timing Specifications .................................................................. 6

Absolute Maximum Ratings ............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 11

Precision Timing High Speed Timing Generation ................. 15

Horizontal Clamping and Blanking ......................................... 18

Vertical Timing Generation ...................................................... 24

Vertical Timing Example ........................................................... 38

Vertical Driver Signal Configuration ........................................... 40

Shutter Timing Control ............................................................. 44

Example of Exposure and Readout of Interlaced Frame....... 53

FG_TRIG Operation .................................................................. 54

Analog Front End Description/Operation ............................. 55

Standby Mode Operation .......................................................... 60

Circuit Layout Information ....................................................... 62

Serial Interface Timing .............................................................. 65

Layout of Internal Registers ...................................................... 66

Updating New Register Values ................................................. 67

Complete Register Listing ......................................................... 68

Equivalent Circuits ......................................................................... 12

Terminology .................................................................................... 13

REVISION HISTORY

1/10—Rev. 0 to Rev. A

Changes to Table 6 ............................................................................ 6

Added Table 8; Renumbered Sequentially .................................... 8

Changes to Individual HBLK Patterns Section .......................... 20

Changes to Table 13 ........................................................................ 20

Change to SUBCK: High Precision Operation Section ............. 45

Changes to Manual Control Section ............................................ 49

10/06—Revision 0: Initial Version

Outline Dimensions ....................................................................... 84

Ordering Guide .......................................................................... 84

Rev. A | Page 2 of 84

AD9923A

SPECIFICATIONS

Table 1.

Parameter Conditions/Comments Min Typ Max Unit

TEMPERATURE RANGE

Operating −25 +85 °C
Storage −65 +150 °C

AFETG POWER SUPPLY VOLTAGES

AVDD AFE analog supply 2.7 3.0 3.6 V
TCVDD Timing Core Analog Supply 2.7 3.0 3.6 V
RGVDD RG Driver 2.7 3.0 3.6 V
HVDD HL, H1 to H4 Drivers 2.7 3.0 3.6 V
DRVDD Data Output Drivers 2.7 3.0 3.6 V
DVDD Digital 2.7 3.0 3.6 V

V-DRIVER POWER SUPPLY

VOLTAGES
VDD1, VDD2 V-Driver Logic +2.7 +3.0 +3.6 V
VH1, VH2 V-Driver High Supply +11.5 +15.0 +16.5 V
VL1, VL2 V-Driver Low Supply −8.5 −7.5 −5.5 V
VM1, VM2 V-Driver Mid Supply −1.5 0.0 +1.5 V
VLL SUBCK Low Supply −8.5 −7.5 −5.5 V
VMM SUBCK Mid Supply −4.0 0.0 +1.5 V

AFETG POWER DISSIPATION

Total 36 MHz, 3.0 V supply, 400 pF total H-load, 20 pF RG load 335 mW
Standby 1 Mode 105 mW
Standby 2 Mode 1 mW
Standby 3 Mode 1 mW
Power from HVDD Only

1

Power from RGVDD Only 10 mW
Power from AVDD Only 75 mW
Power from TCVDD Only 40 mW
Power from DVDD Only 75 mW
Power from DRVDD Only 5 mW

V-DRIVER POWER DISSIPATION2

VH1, VH2 5 mW
VL1, VL2 2.5 mW
VM1, VM2 0 mW
VDD1, VDD2 0.5 mW

MAXIMUM CLOCK RATE (CLI) 36 MHz

1

The total power dissipated by the HVDD supply can be approximated using the equation

Total HVDD Power = [C

Reducing the H-load and/or using a lower HVDD supply reduces the power dissipation. C

2

V-driver power dissipation depends on the frequency of operation and the load they are driving. All inputs to the V-driver were tied low for the

measurements in Table 1.

× HVDD × Pixel Frequency] × HVDD

LOAD

130 mW

VH1, VH2 = +15 V; VL1, VL2 = −7.5 V; VM1, VM2 = 0 V; VDD1, VDD2 =

3.3 V; all V-driver inputs tied low

is the total capacitance seen by all H-outputs.

LOAD

Rev. A | Page 3 of 84

AD9923A

DIGITAL SPECIFICATIONS

DRVDD = 2.7 V to 3.6 V, CL = 20 pF, T

Table 2.

Parameter Conditions/Comments Symbol Min Typ Max Unit

LOGIC INPUTS

High Level Input Voltage VIH 2.1 V
Low Level Input Voltage VIL 0.6 V
High Level Input Current IIH 10 μA
Low Level Input Current IIL 10 μA
Input Capacitance CIN 10 pF

LOGIC OUTPUTS Powered by DVDD, DRVDD

High Level Output Voltage At IOH = 2 mA VOH DVDD − 0.5, DRVDD − 0.5 V
Low Level Output Voltage At IOL = 2 mA VOL 0.5 V

H-DRIVER SPECIFICATIONS

HVDD = RGVDD = 2.7 V to 3.6 V, CL = 20 pF, T

Table 3.

Parameter Conditions/Comments Min Typ Max Unit

RG and H-DRIVER OUTPUTS RG, HL, and H1 to H4 powered by RGVDD, HVDD

High Level Output Voltage At maximum current RGVDD − 0.5, HVDD − 0.5 V
Low Level Output Voltage At maximum current 0.5 V
Maximum Output Current Programmable 30 mA
Maximum Load Capacitance For each output 100 pF

MIN

to T

, unless otherwise noted.

MAX

to T

MIN

, unless otherwise noted.

MAX

VERTICAL DRIVER SPECIFICATIONS

VDD1 = VDD2 = 3.3 V, VH1 = VH2 = 15 V, VM1 = VM2 = VMM = 0 V, VL1 = VL2 = VLL = −7.5 V, 25°C.

Table 4.

Parameter Conditions/Comments Symbol Min Typ Max Unit

V-DRIVER OUTPUTS Simplified load conditions, 3000 pF to ground

Delay Time

VL to VM and VM to VH Rising edges t
VM to VL and VH to VM Falling edges t

Rise Time

VL to VM t
VM to VH t

Fall Time

VM to VL t
VH to VM t

Output Currents

at −7.25 V +10 mA
at −0.25 V −22 mA
at +0.25 V +22 mA
at +14.75 V −10 mA

RON 35 Ω

SUBCK OUTPUT Simplified load conditions, 1000 pF to ground

Delay Time

VLL to VH t
VH to VLL t
VLL to VMM t

Rev. A | Page 4 of 84

, t

35 ns

PLM

PMH

, t

35 ns

PML

PHM

125 ns

RLM

260 ns

RMH

220 ns

FML

125 ns

FHM

25 ns

PLH

30 ns

PHL

25 ns

PLM

AD9923A

Parameter Conditions/Comments Symbol Min Typ Max Unit

VMM to VH t
VH to VMM t
VMM to VLL t

Rise Time

VLL to VH t
VLL to VMM t
VMM to VH t

Fall Time

VH to VLL t
VH to VMM t
VMM to VLL t

Output Currents

at −7.25 V 20 mA
at −0.25 V 12 mA
at +0.25 V 12 mA
at +14.75 V 20 mA

RON 35 Ω

25 ns

PMH

30 ns

PHM

25 ns

PML

40 ns

RLH

45 ns

RLM

30 ns

RMH

40 ns

FHL

90 ns

FHM

25 ns

FML

V-DRIVER

INPUT

V-DRIVER

OUTPUT

50%

10%

90%

50%

t

,

t

,

RLM

t

PLM

t

RMH

RLH

,

t

,

t

PMH

PLH

90%

10%

t

PML

,

t

,

t

PHM

PHL

t

,

t

,

FHM

t

FHL

5586-002

FML

Figure 2. Definition of V-Driver Timing Specifications

ANALOG SPECIFICATIONS

AVDD = 3.0 V, f

Table 5.

Parameter Conditions/Comments Min Typ Max Unit

CDS Input characteristics definition

Allowable CCD Reset Transient 0.5 1.2 V
CDS Gain Accuracy VGA gain = 6 dB (Code 15, default value)

−3 dB CDS Gain −3 −2.5 −2 dB
0 dB CDS Gain Default 0 +0.5 +1 dB
+3 dB CDS Gain +3 +3.5 +4 dB
+6 dB CDS Gain +5.5 +6 +6.5 dB

Maximum Input Range Before Saturation

0 dB CDS Gain Default setting 1.0 V p-p

−3 dB CDS Gain 1.4 V p-p
+6 dB CDS Gain 0.5 V p-p

Maximum CCD Black Pixel Amplitude Positive offset definition

0 dB CDS Gain (Default) −100 +200 mV
+6 dB CDS Gain −50 +100 mV

VARIABLE GAIN AMPLIFIER (VGA)

Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range

Minimum Gain (VGA Code 15) 6 dB
Maximum Gain (VGA Code 1023) 42 dB

= 36 MHz, typical timing specifications, T

CLI

MIN

to T

, unless otherwise noted.

MAX

1

1

Rev. A | Page 5 of 84

AD9923A

Parameter Conditions/Comments Min Typ Max Unit

BLACK LEVEL CLAMP Measured at ADC output

Clamp Level Resolution 1024 Steps

Minimum Clamp Level (Code 0) 0 LSB
Maximum Clamp Level (Code 1023) 255 LSB

ANALOG-TO-DIGITAL CONVERTER (ADC)

Resolution 12 Bits
Differential Nonlinearity (DNL) −1.0 ±0.5 +1.0 LSB
No Missing Codes Guaranteed
Full-Scale Input Voltage 2.0 V

VOLTAGE REFERENCE

Reference Top Voltage (REFT) 2.0 V
Reference Bottom Voltage (REFB) 1.0 V

SYSTEM PERFORMANCE Includes entire signal chain

Gain Accuracy

Low Gain (VGA Code 15) Default CDS gain (0 dB) 6.0 6.5 7.0 dB

Maximum Gain (VGA Code 1023) 42.0 42.5 43.0 dB
Peak Nonlinearity, 500 mV Input Signal 12 dB gain applied 0.1 %
Total Output Noise AC-grounded input, 6 dB gain applied 1.0 LSB rms
Power Supply Rejection (PSR) Measured with step change on supply 50 dB

1

Input signal characteristics are defined as shown in Figure 3.

1V MAX

INPUT SIG NAL RANGE

(0dB CDS GAIN)

500mV TYP

RESET TRANSIENT

TIMING SPECIFICATIONS

CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, f

Table 6.

Parameter Conditions/Comments Symbol Min Typ Max Unit

MASTER CLOCK, CLI

CLI Clock Period t
CLI High/Low Pulse Width 11.2 13.9 16.6 ns
Delay from CLI Rising Edge to Internal Pixel

Position 0
AFE CLPOB Pulse Width

1, 2

2 20 Pixels

Allowable Region for HD Falling Edge to CLI

Rising Edge

SHP Inhibit Region Only valid in slave mode t

AFE SAMPLE LOCATION

1

SHP Sample Edge to SHD Sample Edge tS1 11.6 13.9 ns

DATA OUTPUTS

Output Delay from DCLK Rising Edge

1

t

Inhibited Area for DOUTPHASE Edge

Location
Pipeline Delay from SHP/SHD Sampling to

Data Output

SERIAL INTERFACE

Maximum SCK Frequency f
SL to SCK Setup Time tLS 10 ns
SCK to SL Hold Time tLH 10 ns
SDATA Valid to SCK Rising Edge Setup tDS 10 ns

= 36 MHz, unless otherwise noted.

CLI

t

Only valid in slave mode t

SHD SHD + 11 Edge

16 Cycles

200mV MAX

OPTICAL BLACK PIXEL

Figure 3. Signal Characteristics

CONV

CLIDLY

HDCLI

SHPINH

OD

SCLK

05586-003

27.8 ns

6 ns

4 t

− 2 ns

CONV

30 39 Edge

location

8 ns

location

36 MHz

Rev. A | Page 6 of 84

AD9923A

Parameter Conditions/Comments Symbol Min Typ Max Unit

SCK Falling Edge to SDATA Valid Hold tDH 10 ns
SCK Falling Edge to SDATA Valid Read tDV 10 ns

INHIBIT REGION FOR SHP AND SHD WITH

RESPECT TO H-CLOCK EDGE LOCATION

HxMASK = 0, HxRETIME = 0, HxPOLARITY = 0 t

HxMASK = 0, HxRETIME = 0, HxPOLARITY = 1 t

HxMASK = 0, HxRETIME = 1, HxPOLARITY = 0 t

HxMASK = 0, HxRETIME = 1, HxPOLARITY = 1 t

HxMASK = 1, HxRETIME = 0, HxPOLARITY = 0 t

HxMASK = 1, HxRETIME = 0, HxPOLARITY = 1 t

HxMASK = 1, HxRETIME = 1, HxPOLARITY = 0 t

HxMASK = 1, HxRETIME = 1, HxPOLARITY = 1 t

1

Parameter is programmable.

2

Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.

HxPOS − 9 HxPOS − 18

SHDINH

Edge
location

HxNEG − 9 HxNEG − 18

SHDINH

Edge
location

HxPOS − 7 HxPOS − 16

SHPINH

Edge
location

HxNEG − 7 HxNEG − 16

SHPINH

Edge
location

HxNEG − 9 HxNEG − 18

SHDINH

Edge
location

HxPOS − 9 HxPOS − 18

SHDINH

Edge
location

HxNEG − 7 HxNEG − 16

SHPINH

Edge
location

HxPOS − 7 HxPOS − 16

SHPINH

Edge
location

Rev. A | Page 7 of 84

AD9923A

ABSOLUTE MAXIMUM RATINGS

Table 7.

Parameter To Rating

AVDD AVSS −0.3 V to +3.9 V
TCVDD TCVSS −0.3 V to +3.9 V
HVDD HVSS −0.3 V to +3.9 V
RGVDD RGVSS −0.3 V to +3.9 V
DVDD DVSS −0.3 V to +3.9 V
DRVDD DRVSS −0.3 V to +3.9 V
VDD1, VDD2 VSS1, VSS2 −0.3 V to +6 V
VH1, VH2 VL1, VL2 −0.3 V to +25 V
VH1, VH2 VSS1, VSS2 −0.3 V to +17 V
VL1, VL2 VSS1, VSS2 −17 V to +0.3 V
VM1, VM2 VSS1, VSS2 −6 V to +6 V
VLL VSS1, VSS2 −17 V to +0.3 V
VMM VSS1, VSS2 −6 V to + VH
VDR_EN VSS1, VSS2 −0.3 V to +6 V
V1 to V15 VSS1, VSS2 VL − 0.3 V to VH + 0.3 V
RG Output RGVSS −0.3 V to RGVDD + 0.3 V
H1 to H4 Output HVSS −0.3 V to HVDD + 0.3 V
Digital Outputs DVSS −0.3 V to DVDD + 0.3 V
Digital Inputs DVSS −0.3 V to DVDD + 0.3 V
SCK, SL, SDATA DVSS −0.3 V to DVDD + 0.3 V
REFT/REFB, CCDIN AVSS −0.3 V to AVDD + 0.3 V
Junction Temperature 150°C
Lead Temperature, 10 sec 350°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

Table 8. Thermal Resistance

Package Type θJA Unit

CSP_BGA 40.3 °C/W

ESD CAUTION

Rev. A | Page 8 of 84

AD9923A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD9923A

A1 CORNER
INDEX AREA

Figure 4. 105-Lead CSPBGA Package Pin Configuration

1234567891011

Table 9. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

A7 AVDD P Analog Supply for AFE.

A1, A4, B2, B3, B4, B5, B6, B7 AVSS P Analog Ground for AFE.

B8 TCVDD P Analog Supply for Timing Core.

B9 TCVSS P Analog Ground for Timing Core.

E1 DVDD1 P Digital Logic Power Supply 1.

F2 DVSS1 P Digital Logic Ground 1.

K8, L7, L8 DVDD2 P Digital Logic Power Supply 2.

K9 DVSS2 P Digital Logic Ground 2.

D9 HVDD P H1 to H4, HL Driver Supply.

D10 HVSS P H1 to H4, HL Driver Ground.

B10 RGVDD P RG Driver Supply.

A10 RGVSS P RG Driver Ground.

L4 DRVDD P Data Output Driver Supply.

L5 DRVSS P Data Output Driver Ground.

J4 VDD1 P V-Driver Logic Supply 1.

K5 VSS1 P V-Driver Logic Ground 1.

L10 VDD2 P V-Driver Logic Supply 2.

K10 VSS2 P V-Driver Logic Ground 2.

F9 VH1 P V-Driver High Supply 1.

D1 VH2 P V-Driver High Supply 2.

E9 VL1 P V-Driver Low Supply 1.

C1 VL2 P V-Driver Low Supply 2.

C9 VM1 P V-Driver Mid Supply 1.

D3 VM2 P V-Driver Mid Supply 2.

F3 VLL P SUBCK Driver Low Supply.

E3 VMM P SUBCK Driver Mid Supply.

A6 CCDIN AI CCD Signal Input.

A5 CCDGND AI CCD Signal Ground.

A3 REFT AO Voltage Reference Top Bypass.

A2 REFB AO Voltage Reference Bottom Bypass.

C3 SL DI 3-Wire Serial Load Pulse.

C2 SCK DI 3-Wire Serial Clock.

B1 SDI DI 3-Wire Serial Data Input.

G7 SYNC DI External System Synchronization Input.

E5

RSTB

TOP VIEW

(Not to Scale)

A

B

C

D

E

F

G

H

J

K

L

05586-004

DI Reset Bar, Active Low Pulse.

Rev. A | Page 9 of 84

AD9923A

Pin No. Mnemonic Type1 Description

A8 CLI DI Reference Clock Input (Master Clock).
A9 CLO DO Clock Output for Crystal.
F11 H1 DO CCD Horizontal Clock 1.
E11 H2 DO CCD Horizontal Clock 2.
D11 H3 DO CCD Horizontal Clock 3.
C11 H4 DO CCD Horizontal Clock 4.
B11 HL DO CCD Last Horizontal Clock.
C10 RG DO CCD Reset Gate Clock.
K6 VSUB DO CCD Substrate Bias.
F5 MSHUT DO Mechanical Shutter Pulse.
G5 STROBE DO Strobe Pulse.
G6 SUBCK DO CCD Substrate Clock (E Shutter).
F1 DCLK DO Data Clock Output.
G1 D0 DO Data Output (LSB).
H3 D1 DO Data Output.
H2 D2 DO Data Output.
H1 D3 DO Data Output.
J3 D4 DO Data Output.
J2 D5 DO Data Output.
J1 D6 DO Data Output.
K3 D7 DO Data Output.
K2 D8 DO Data Output.
K1 D9 DO Data Output.
L3 D10 DO Data Output.
L2 D11 DO Data Output (MSB).
D2 VD DIO Vertical Sync Pulse. Input in slave mode, output in master mode.
E2 HD DIO Horizontal Sync Pulse. Input in slave mode, output in master mode.
C8 V1 VO3 CCD Vertical Transfer Clock.
G10 V2 VO2 CCD Vertical Transfer Clock.
E7 V3 VO3 CCD Vertical Transfer Clock.
G9 V4 VO2 CCD Vertical Transfer Clock.
C4 V5A VO3 CCD Vertical Transfer Clock.
C5 V5B VO3 CCD Vertical Transfer Clock.
F10 V6 VO2 CCD Vertical Transfer Clock.
C6 V7A VO3 CCD Vertical Transfer Clock.
C7 V7B VO3 CCD Vertical Transfer Clock.
G11 V8 VO2 CCD Vertical Transfer Clock.
H11 V9 VO2 CCD Vertical Transfer Clock.
H10 V10 VO2 CCD Vertical Transfer Clock.
F6 V11 VO3 CCD Vertical Transfer Clock.
F7 V12 VO3 CCD Vertical Transfer Clock.
E10 V13 VO2 CCD Vertical Transfer Clock.
K11 VDR_EN DI V-Driver Output Enable pin.
J5 TEST0 DI Test Input. Must be tied to VSS1 or VSS2.
J7 TEST1 DI Test Input. Must be tied to VSS1 or VSS2.
J8 TEST3 DI Test Input. Must be tied to VDD1 or VDD2.
A11, E6, H9, J6, J9, J10, J11, K4, K7, L1, L6,

L9, L11, G2, G3

1

AI = analog input, AO = analog output, DI = digital input, DO = digital output, DIO = digital input/output, P = power, VO2 = Vertical Driver Output 2 level, VO3 =

Vertical Driver Output 3 level.

NC No Connect.

Rev. A | Page 10 of 84

AD9923A

TYPICAL PERFORMANCE CHARACTERISTICS

450

400

350

300

250

200

POWER (V)

150

100

50

0

18

FREQUENCY (MHz)

3.3V

3.0V

2.7V

27

36

05586-089

Figure 5. Power vs. Sample Rate

5

4

3

2

1

INL (LSB)

0

–1

–2

–3

0 500 1000 1500 2000 2500 3000 3500

CODE

Figure 7. Typical INL Performance

4000

05586-087

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

0 500 1000 1500 2000 2500 3000 3500

CODE

Figure 6. Typical DNL Performance

4000

55

50

45

40

35

30

25

20

NOISE LSB ( rms)

15

10

5

0

0

05586-086

GAIN CODE

+6dB

+3dB

–3dB

0dB

1000900800700600500400300200100

05586-088

Figure 8. Output Noise vs. VGA Gain

Rev. A | Page 11 of 84

AD9923A

V

EQUIVALENT CIRCUITS

HVDD OR RGVDD

AVDD

R

AVSS

AVSS

05586-005

Figure 9. CCDIN, CCDGND

DVDD

DATA

THREE-STAT E D[0:11]

DVSS DRVSS

DRVDD

RG, HL,

H1 TO H4

THREE-STATE OUTPUT

HVSS OR RGVSS

05586-008

Figure 12. HL, H1 to H4, and RG Drivers

DVDD

VDVSS

3.5kΩ

R

05586-009

VDR_EN

Figure 13. VDR_EN Input

5586-006

Figure 10. Digital Data Outputs

DVDD

330Ω

DVSS

05586-007

Figure 11. Digital Inputs

Rev. A | Page 12 of 84

AD9923A

TERMINOLOGY

Differential Nonlinearity (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Therefore,

every code must have a finite width. No missing codes guaranteed

to 12-bit resolution indicates that all 4096 codes, respectively,

must be present over all operating conditions.

Integral Nonlinearity (INL)

The deviation of each code measured from a true straight line

between the zero and full-scale values. The point used as zero

scale occurs 0.5 LSB before the first code transition. Positive full

scale is defined as a level 1.5 LSB beyond the last code transition.

The deviation is measured from the middle of each output code

to the true straight line.

Peak Nonlinearity

Peak nonlinearity, a full signal chain specification, refers to the

peak deviation of the AD9923A output from a true straight line.

The point used as zero scale occurs 0.5 LSB before the first code

transition. Positive full scale is defined as a level 1.5 LSB beyond

the last code transition. The deviation is measured from the

middle of each output code to the true straight line. The error is

expressed as a percentage of the 2 V ADC full-scale signal. The

input signal is always appropriately gained up to fill the full-scale

range of the ADC.

Tot a l O ut p ut Noi se

The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB, and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship

1 LSB = (ADC full scale/2

where n is the bit resolution of the ADC and 1 LSB is 0.488 mV.

Power Supply Rejection (PSR)

The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.

n

codes)

Rev. A | Page 13 of 84

AD9923A

V

THEORY OF OPERATION

Figure 14 shows the typical system block diagram for the
AD9923A in master mode. The CCD output is processed by
the AD9923A AFE circuitry, which consists of a CDS, VGA,
black level clamp, and ADC. The digitized pixel information is
sent to the digital image processor chip that performs the post­processing and compression. To operate the CCD, CCD timing
parameters are programmed into the AD9923A from the system
microprocessor through the 3-wire serial interface. The AD9923A
generates the CCD horizontal, vertical, and the internal AFE
clocks from the system master clock CLI. The CLI is provided
by the image processor or external crystal. External synchroniza­tion is provided by a sync pulse from the microprocessor, which
resets internal counters and resyncs the VD and HD outputs.

Alternatively, the AD9923A can be operated in slave mode, in
which the VD and HD are provided externally from the image
processor. In this mode, the AD9923A timing is synchronized
with VD and HD.

The H-drivers for HL, H1 to H4, and RG are included in the
AD9923A, allowing these clocks to be directly connected to the
CCD. An H-driver voltage, HVDD, of up to 3.3 V is supported.
An external V-driver is required for the vertical transfer clocks,
the sensor gate pulses, and the substrate clock.

Figure 15 and Figure 16 show the maximum horizontal and
vertical counter dimensions for the AD9923A. Internal hori­zontal and vertical clocking is controlled by these counters to
specify line and pixel locations. The maximum HD length is
8192 pixels per line, and the maximum VD length is 4096 lines
per field.

1 TO V13, SUBCK

HL, H1 TO H4, RG, VSUB

SERIAL
INTERFACE

D[0:11]

DCLK

HD, VD

CLI

DIGITAL

IMAGE

PROCESSING

ASIC

MICRO-

PROCESSOR

CCD

CCDIN

MSHUT

STROBE

AD9923A

V-DRIVER

SYNC

AFETG +

Figure 14. Typical System Block Diagram, Master Mode

MAXIMUM
COUNTER
DIMENSIONS

13-BIT HORIZONTAL = 8192 PIXELS MAX

05586-013

The AD9923A also includes programmable MSHUT and
STROBE outputs that can be used to trigger mechanical shutter
and strobe (flash) circuitry.

MAX VD LENGTH IS 4096 LI NES

VD

HD

CLI

MAX HD LENGT H IS 8192 PIX ELS

Figure 16. Maximum VD/HD Dimensions

12-BIT VERT ICAL = 4096 LINES MAX

05586-014

Figure 15. Vertical and Horizontal Counters

05586-015

Rev. A | Page 14 of 84

AD9923A

PRECISION TIMING

HIGH SPEED TIMING GENERATION

The AD9923A generates high speed timing signals using the

flexible Precision Timing core. This core is the foundation for

generating the timing used for both the CCD and the AFE. It

consists of the reset gate (RG), horizontal drivers (H1 to H4 and

HL), and sample clocks (SHP and SHD). A unique architecture

makes it routine for the system designer to optimize image

quality by providing precise control over the horizontal CCD

readout and the AFE-correlated double sampling.

The high speed timing of the AD9923A operates the same in

master and slave modes. For more information on synchroniza-

tion and pipeline delays, see the Power-Up and Synchronization

in Slave Mode section.

Timing Resolution

The Precision Timing core uses a 1× master clock input (CLI) as

a reference. The frequency of this clock should match the CCD

pixel clock frequency. Figure 17 illustrates how the internal

timing core divides the master clock period into 48 steps, or

edge positions. Using a 36 MHz CLI frequency, the edge

resolution of the Precision Timing core is approximately 0.6 ns.

If a 1× system clock is not available, a 2× reference clock can be

used by programming the CLIDIVIDE register (Address 0x30).

The AD9923A then internally divides the CLI frequency by 2.

The AD9923A includes a master clock output (CLO) which is

the inverse of CLI. This output is intended to be used as a

crystal driver. A crystal can be placed between the CLI and

CLO pins to generate the master clock for the AD9923A. For

more information on using a crystal, see Figure 80.

High Speed Clock Programmability

Figure 18 shows how the RG, HL, H1 to H4, SHP, and SHD

high speed clocks are generated. The RG pulse has programmable

rising and falling edges and can be inverted using the polarity

control. The HL, H1, and H3 horizontal clocks have program-

mable rising and falling edges and polarity control. The H2 and

H4 clocks are inverses of the H1 and H3 clocks, respectively.

Tabl e 10 summarizes the high speed timing registers and their

parameters. Figure 19 shows the typical 2-phase, H-clock

operation, in which H3 and H4 are programmed for the same

edge location as H1 and H2.

The edge location registers are six bits wide, but there are only
48 valid edge locations available. Therefore, the register values
are mapped into four quadrants, each of which contains 12 edge
locations. Tabl e 11 shows the correct register values for the
corresponding edge locations. Figure 20 shows the default
timing locations for high speed clock signals.

H-Driver and RG Outputs

In addition to the programmable timing positions, the
AD9923A features on-chip output drivers for the RG and H1 to
H4 outputs. These drivers are powerful enough to directly drive
the CCD inputs. The H-driver and RG current can be adjusted for
optimum rise/fall times in a particular load by using the H1 to
H4, HL, and RGDRV registers (Address 0x36). The 3-bit drive
setting for each output can be adjusted in 4.1 mA increments,
with the minimum setting of 0 equal to 0 mA or three-state, and
the maximum setting of 7 equal to 30.1 mA.

As shown in Figure 18, Figure 19, and Figure 20, the H2 and H4
outputs are inverses of H1 and H3 outputs, respectively. The
H1/H2 crossover voltage is approximately 50% of the output
swing. The crossover voltage is not programmable.

Digital Data Outputs

The AD9923A data output and DCLK phase are programmable
using the DOUTPHASE register (Address 0x38, Bits[5:0]). Any
edge from 0 to 47 can be programmed, as shown in Figure 21.
Normally, the DOUT and DCLK signals track in phase, based
on the DOUTPHASE register contents. The DCLK output
phase can also be held fixed with respect to the data outputs by
setting the DCLKMODE register to high (Address 0x38, Bit[8]).
In this mode, the DCLK output remains at a fixed phase equal
to a delayed version of CLI, and the data output phase remains
programmable. For more detail, see the Analog Front End
Description/Operation section.

There is a fixed output delay from the DCLK rising edge to the
DOUT transition, called t
four values between 0 ns and 12 ns, using the DOUTDELAY
register (Address 0x38, Bits[10:9]). The default value is 8 ns.

The pipeline delay through the AD9923A is shown in Figure 22.
After the CCD input is sampled by SHD, there is a 16-cycle
delay before the data is available.

. This delay can be programmed to

OD

Table 10. Timing Core Register Parameters for HL, H1 to H4, RG, SHP/SHD

Length

Parameter

Polarity 1 High/low Polarity control for HL, H1, H3, and RG (0 = no inversion, 1 = inversion)

Positive Edge 6 0 to 47 edge location Positive edge location for HL, H1, H3, and RG (H2/H4 are inverses of H1/H3, respectively)

Negative Edge 6 0 to 47 edge location Negative edge location for HL, H1, H3, and RG (H2/H4 are inverses of H1/H3, respectively)

Sampling

Location

Drive Strength 3 0 to 7 current steps Drive current for HL, H1 to H4, and RG outputs (4.1 mA per step)

(Bits) Range Description

6 0 to 47 edge location Sampling location for internal SHP and SHD signals

Rev. A | Page 15 of 84

AD9923A

Table 11. Precision Timing Edge Locations

Quadrant Edge Location (Decimal) Register Value (Decimal) Register Value (Binary)

I 0 to 11 0 to 11 000000 to 001011
II 12 to 23 16 to 27 010000 to 011011
III 24 to 35 32 to 43 100000 to 101011
IV 36 to 47 48 to 59 110000 to 111011

POSITION

CLI

1 PIXEL

PERIOD

P[0] P[48] = P[0]P[12] P[24] P[36]

t

CLIDLY

NOTES

1. THE PIXEL CLOCK PE RIOD IS DI VIDED INT O 48 POSITIONS, PROVIDING FINE EDG E RESOLUT ION FO R HIGH SPEED CLOCK.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITION (t

CLIDLY

= 6ns TYP ).

Figure 17. High Speed Clock Resolution from CLI Master Clock Input

3

CCD

SIGNAL

12

RG

56

HL

78

H1

4

05586-016

H2

910

H3

H4

PROGRAMMABLE CLOCK POSI TIONS:

1

RG RISING E DGE.

2

RG FALLING EDGE.

3

SHP SAMPLE LOCATION.

4

SHD SAMPLE LOCATION.

5

HL RISING E DGE POSITION.

6

HL FALLING EDGE POSITION.

7

H1 RISING EDGE POSITION.

8

H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1).

9

H3 RISING EDGE POSITION.

10

H3 FALLING EDGE POSITION (H4 IS INVERSE OF H3).

05586-017

Figure 18. High Speed Clock Programmable Locations

Rev. A | Page 16 of 84

AD9923A

2

3

CCD

SIGNAL

RG

HL/H1/H3

H2/H4

NOTES

1. USING T HE SAME TOG GLE PO SITIO NS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKI NG.

Figure 19. 2-Phase H-Clock Operation

05586-018

POSITION

PIXEL

PERIOD

RG

HL/H1/H3

H2/H4

CCD

SIGNAL

NOTES

1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.

2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.

P[0]

RGr[0] RGf[12]

Hr[0] Hf[24]

P[24]P[12] P [36]

SHP[24]

t

S1

P[48] = P[0]

SHD[48]

5586-019

Figure 20. High Speed Timing Default Locations

P[0]

P[12]

P[24]

P[36]

P[48] = P[0]

PIXEL

PERIOD

DCLK

t

OD

DOUT

NOTES

1. DATA OUTP UT (DOUT) AND DCL K PHASE ARE ADJUSTABLE WITH RES PECT TO THE PIXEL PERIOD.
. WITHIN 1 CLOCK PERI OD, THE DAT A TRANSITI ON CAN BE PROG RAMMED TO 48 DI FFERENT LOCATIONS.
. OUTPUT DELAY (

t

) FROM DCLK RI SING EDGE TO DOUT RI SING EDG E IS PROGRAMMABLE.

OD

05586-020

Figure 21. Digital Output Phase Adjustment

Rev. A | Page 17 of 84

AD9923A

CLI

t

CCDIN

SHD

(INTERNAL)

ADC DOUT

(INTERNAL)

DCLK

D[0:11]

CLIDLY

NN+1

SAMPLE PIXEL N

N–17

N–17

NOTES

1. TIMING VALUES SHO WN ARE SHDLO C = 0, WITH DCLKMODE = 0.

2. HIGHER VAL UES OF SHD AND/OR DOUTPHASE S HIFT DOUT TRANSITION TO T HE RIGHT WITH RESPE CT TO CLI LOCATI ON.

3. INHIBIT TIME F OR DOUT PHASE IS DEFI NED BY
THE 12 EDGE LOCATIONS F OLLO WING SHDL OC NOT BE USED FOR THE DOUTPHASE LOCATION.

4. RECOMMENDED VALUE FOR DOUT PHASE IS TO USE THE SHPLOC EDGE OR THE 11 EDGES FOLLOWING SHPLOC.

5. RECOMMENDED V ALUE FOR

6. THE DOUT LATCH CAN BE BYPASSED USING REG ISTER 0x01, BIT [1] = 1 SO THAT THE ADC DATA OUTPUTS APPEAR DIRECTLY AT
THE DATA OUTPUT PINS. THIS CONFI GURATION IS RECOMMENDED IF THE ADJUST ABLE DOUT PHASE IS NOT REQUIRED.

N–16

N–16

t

DOUTINH

N+2

N–15

N+3

N–14

N–13

t

(DOUT DLY) IS 4ns.

OD

PIPELI NE LATENCY = 16 CY CLES

t

DOUTINH

N+8N+7N+6N+5N+4

N–8N–9N–10N–11N–12N–13N–14N–15

, WHICH IS EQUAL TO SHDLOC PLUS 11 EDGES. IT IS RECO MMENDED THAT

N+11N+10N+9

N–7 N–6

N–5

N–4

N–4

N–5N–6N–7N–8N–9N–10N–11N–12

N–3

N–3

N+15N+14N+13N+12

N–2NN–1

N–2NN–1

Figure 22. Digital Data Output Pipeline Delay

N+16

N+17

05586-021

HORIZONTAL CLAMPING AND BLANKING

The AD9923A horizontal clamping and blanking pulses are
fully programmable to suit a variety of applications. Individual
controls are provided for CLPOB, PBLK, and HBLK during
different regions of each field. This allows dark pixel clamping
and blanking patterns to be changed at each stage of the readout
to accommodate different image transfer timing and high speed
line shifts.

Individual CLPOB and PBLK Patterns

The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 23. These two signals are independently
programmed using the registers in Tab le 1 2 . SPOL is the start
polarity for the signal, and TOG1 and TOG2 are the first and
second toggle positions of the pulse. Both signals are active low
and should be programmed accordingly.

A separate pattern for CLPOB and PBLK can be programmed
for each V-sequence. As described in the Ver tic a l Ti m ing
Generation section, several V-sequences can be created, each
containing a unique pulse pattern for CLPOB and PBLK.

Figure 46 shows how the sequence change positions divide the
readout field into regions. A different V-sequence can be
assigned to each region, allowing the CLPOB and PBLK signals
to change with each change in the vertical timing. Unused CLPOB
and PBLK toggle positions should be set to 8191.

CLPOB and PBLK Masking Area

The AD9923A allows the CLPOB and/or PBLK signals to be
disabled during certain lines in the field without changing the
existing CLPOB and/or PBLK pattern settings.

To use CLPOB masking, the CLPMASKSTART and CLPMASKEND
registers are programmed to specify the starting and ending lines
in the field where the CLPOB patterns are ignored. There are three
sets of CLPMASKSTART and CLPMASKEND registers,
allowing up to three CLPOB masking areas to be created.

CLPOB masking registers are not specific to a given V-sequence;
they are active for any existing field of timing. To disable the
CLPOB masking feature, set these registers to the maximum
value, 0xFFF (default value).

To use PBLK masking, the PBLKMASKSTART and
PBLKMASKEND registers are programmed to specify the
starting and ending lines in the field where the PBLK patterns
are ignored. There are three sets of PBLKMASKSTART and
PBLKMASKEND registers, allowing the creation of up to three
PBLK masking areas.

PBLK masking registers are not specific to a given V-sequence;
they are active for any existing field of timing. To disable the
PBLK masking feature, set these registers to the maximum
value, 0xFFF (default value).

Rev. A | Page 18 of 84

AD9923A

C

K

Table 12. CLPOB and PBLK Pattern Registers

Register Length (Bits) Range Description

CLPOBPOL 1 High/low Starting polarity of CLPOB for each V-sequence
PBLKPOL 1 High/low Starting polarity of PBLK for each V-sequence
CLPOBTOG1 13 0 to 8191 pixel location First CLPOB toggle position within the line for each V-sequence
CLPOBTOG2 13 0 to 8191 pixel location Second CLPOB toggle position within the line for each V-sequence
PBLKTOG1 13 0 to 8191 pixel location First PBLK toggle position within the line for each V-sequence
PBLKBTOG2 13 0 to 8191 pixel location Second PBLK toggle position within the line for each V-sequence
CLPMASKSTART 12 0 to 4095 line location CLPOB masking area—starting line within the field (maximum of three areas)
CLPMASKEND 12 0 to 4095 line location CLPOB masking area—ending line within the field (maximum of three areas)
PBLKMASKSTART 12 0 to 4095 line location PBLK masking area—starting line within the field (maximum of three areas)
PBLKMASKEND 12 0 to 4095 line location PBLK masking area—ending line within the field (maximum of three areas)

HD

32

CLPOB

1

PBLK

PROGRAMMABLE SETTINGS:

1

START POLARITY (CLAMP AND BLANK REGIO NS ARE ACTIVE L OW).

2

FIRST TOGGLE POSITION.

3

SECOND TOGGLE POSITION.

ACTIVE

Figure 23. Clamp and Preblank Pulse Placement

ACTIVE

05586-022

NO CLPOB SI GNAL

FOR LINE 600

NO PBLK SIG NAL

FOR LINE 703

05586-023

5586-010

LPOB

PBL

VD

0 1 2 597 598

HD

CLPMASKSTART 1 = 6 CLPMASKEND1 = 8

NO CLPOB SI GNAL

FOR LINES 6 TO 8

Figure 24. CLPOB Masking Example

VD

0 1 2 700 701

HD

PBLKMASKSTART 1 = 6 PBLKMASKEND1 = 8

NO PBLK SIG NAL
FOR LINES 6 TO 8

Figure 25. PBLK Masking Example

CLPMASKSTART 2 = CLPMASKEND2 = 600

PBLKMASKSTART2 = PBLKMASKEND2 = 703

Rev. A | Page 19 of 84

AD9923A

Individual HBLK Patterns

The HBLK programmable timing shown in Figure 26 is similar
to CLPOB and PBLK; however, there is no start polarity control.
Only the toggle positions are used to designate the start and end
positions of the blanking period. Additionally, there is a polarity
control register, HBLKMASK, that designates the polarity of the
horizontal clock signals during the blanking period. Setting
HBLKMASK high sets H1 = H3 = high and H2 = H4 = low
during blanking, as shown in Figure 27. As with CLPOB and
PBLK registers, HBLK registers are available in each V-sequence,
allowing different blanking signals to be used with different
vertical timing sequences.

Note that 8189 is the recommended setting for any unused
HBLK toggle locations on the AD9923A, regardless of the

Table 13. HBLK Pattern Registers

Length

Register

(Bits) Range Description

HBLKMASK 1 High/low Masking polarity for H1, H3, HL (0 = mask low, 1 = mask high)
HBLKALT 3 0 to 7 alternation modes Enables different odd/even alternation of HBLK toggle positions
0: disable alternation (HBLKTOGE1 to HBLKTOGE6 registers are used for each line)
1: TOGE1 and TOGE2 odd lines, TOGE3 to TOGE6 even lines
2: TOGE1 and TOGE2 even lines, TOGE3 to TOGE6 odd lines

3: TOGE1 to TOGE6 even lines, TOGO1 to TOGE6 odd lines (FREEZE/RESUME not
available)

4 to 7: HBLKSTART, HBLKEND, HBLKLEN, and HBLKREP registers are used for each line
HBLKTOGE1 13 0 to 8189 pixel location HBLK first toggle position (for even lines only when HBLKALT = 3)
HBLKTOGE2 13 0 to 8189 pixel location HBLK second toggle position (for even lines only when HBLKALT = 3)
HBLKTOGE3 13 0 to 8189 pixel location HBLK third toggle position (for even lines only when HBLKALT = 3)
HBLKTOGE4 13 0 to 8189 pixel location HBLK fourth toggle position (for even lines only when HBLKALT = 3)
HBLKTOGE5 13 0 to 8189 pixel location Fifth toggle position, even lines (HBLKSTART when HBLKALT = 4 to 7)
HBLKTOGE6 13 0 to 8189 pixel location Sixth toggle position, even lines (HBLKEND when HBLKALT = 4 to 7)
HBLKLEN 13 0 to 8189 pixels HBLK pattern length, only used when HBLKALT = 4 to 7
HBLKREP 8 0 to 255 repetitions Number of HBLK pattern repetitions, only used when HBLKALT = 4 to 7
HBLKTOGO1 13 0 to 8189 pixel location First toggle position for odd lines when HBLKALT = 3 (usually VREPA_3)
HBLKTOGO2 13 0 to 8189 pixel location Second toggle position for odd lines when HBLKALT = 3 (usually VREPA_4)
HBLKTOGO3 13 0 to 8189 pixel location Third toggle position for odd lines when HBLKALT = 3 (usually FREEZE1)
HBLKTOGO4 13 0 to 8189 pixel location Fourth toggle position for odd lines when HBLKALT = 3 (usually RESUME1)
HBLKTOGO5 13 0 to 8189 pixel location Fifth toggle position for odd lines when HBLKALT = 3 (usually FREEZE2)
HBLKTOGO6 13

0 to 8189 pixel location

Sixth toggle position for odd lines when HBLKALT = 3 (usually RESUME2)

setting for HBLKALT. 8190 and 8191 are not valid settings for
HBLK toggle positions that are unused and causes undesired
HBLK toggle activity.

Generating Special HBLK Patterns

There are six toggle positions available for HBLK. Normally,
only two of the toggle positions are used to generate the
standard HBLK interval. However, additional toggle positions
can be used to generate special HBLK patterns, as shown in
Figure 28. The pattern in this example uses all six toggle
positions to generate two extra groups of pulses during the
HBLK interval. By changing the toggle positions, different
patterns can be created.

HBLK

HD

HBLKTOGE1 HBLKTOGE2

BLANK BLANK

BASIC HBLK PULSE IS GENERAT ED USING HBLKT OGE1 AND HBLKTOGE2 REG ISTERS (HBLKALT = 0).

Figure 26. Typical Horizontal Blanking (HBLK) Pulse Placement

Rev. A | Page 20 of 84

05586-024

AD9923A

HD

HBLK

HL/H1/H3

THE POLARI TY OF HL/H1/H3 DURING BLANKING ARE I NDEPENDENTLY P ROGRAMMABLE
(H2/H4 IS OPPOSITE POLARITY OF H1/H3).

H1/H3

H2/H4

...

...

05586-025

Figure 27. HBLK Masking Polarity Control

HBLKTOGE2

HBLKTOGE1

HBLK

HBLKTOGE4

HBLKTOGE3

HBLKTOGE6

HBLKTOGE5

HL/H1/ H3

H2/H4

SPECIAL H-BL ANK PATTERN IS CREATED USING M ULTIPL E HBLK TOG GLE PO SITIO NS (HBLKALT = 0).

Figure 28. Using Multiple Toggle Positions for HBLK (HBLKALT = 0)

Generating HBLK Line Alternation

The AD9923A can alternate different HBLK toggle positions on
odd and even lines. This feature can be used in conjunction with
V-pattern odd/even alternation, or on its own. When 1 is written
to the HBLKALT register, HBLKTOGE1 and HBLKTOGE2 are
used on odd lines, and HBLKTOGE3 to HBLKTOGE6 are used
on even lines. Writing 2 to the HBLKALT register gives the oppo­site result: HBLKTOGE1 and HBLKTOGE2 are used on even
lines, and HBLKTOGE3 to HBLKTOGE6 are used on odd lines.
When 3 is written to the HBLKALT register, all six even toggle
positions, HBLKTOGE1 to HBLKTOGE6, are used on even

5586-026

lines. There are also six additional toggle positions, HBLKTOGO1
to HBLKTOGE6, for odd lines. These registers are normally
used for VPAT Group A, VPAT Group B, and freeze/resume
functions, but when HBLKALT = 3, these registers become the
odd line toggle positions for HBLK.

Another HBLK feature is enabled by writing 4, 5, 6, or 7 to
HBLKALT. In these modes, the HBLK pattern is generated using
a different set of registers—HBLKSTART, HBLKEND, HBLKLEN,
and HBLKREP—along with four toggle positions. This allows
for multiple repeats of the HBLK signal, as shown in Figure 32.

Rev. A | Page 21 of 84

AD9923A

HD

HBLK

HL/H1/H3

H2/H4

ODD LINE EVEN LINE

HBLKTOGE1

HBLKTOGE2

HBLKTOGE3 HBLKT OGE5

HBLKTOGE4 HBLKT OGE6

ALTERNATING H-BLANK PATTERN USING HBLKAL T = 1 MODE.

05586-027

Figure 29. HBLK Odd/Even Alternation Using HBLKALT = 1

HD

HBLK

HL/H1/H3

H2/H4

ODD LINE EVEN LINE

HBLKTOGE4 HBLKTOG E6 HBLKTO GE2

HBLKTOGE3 HBLKTO GE5 HBLKTOGE1

ALTERNATING H-BLANK PATTERN USING HBLKAL T = 2 MODE.

Figure 30. HBLK Odd/Even Alternation Using HBLKALT = 2

05586-028

HD

HBLK

ODD LINE EVEN LINE

HBLKTOGO2 HBLKTOGO4 HBLKTOGE2 HBLKTOGE 4

HBLKTOGO1 HBLKTO GO3 HBLKTOGE1 HBLKTOGE3

HBLK

HL/H1/H3

H2/H4

HL/H1/H3

H2/H4

HBLKSTART

ALTERNATING H-BLANK PATTERN USING HBLKAL T = 3 MODE.
(FREEZE/ RESUME FUNCTI ON NOT AVAI LABLE IN T HIS MODE.)

Figure 31. HBLK Odd/Even Alternation Using HBLKALT = 3

HBLKTOGE1 HBLKTOGE3

HBLKLEN

HBLKREP = 3

HBLKREP NUMBER 1 HBLKRE P NUMBER 2 HBLKREP NUMBER 3

H-BLANK REPEATING PATTERN IS CREATED USING HBLKLEN AND HBLKREP REGISTERS.

HBLKTOGE4HBLKTOGE2

Figure 32. HBLK Repeating Pattern Using HBLKALT = 4 to 7

Rev. A | Page 22 of 84

HBLKEND

06415-029

06415-030

AD9923A

Increasing H-Clock Width During HBLK

The AD9923A allows the H1 to H4 pulse width to be increased
during the HBLK interval. The H-clock pulse width can in­crease by reducing the H-clock frequency (see Tabl e 14).

The HBLKWIDTH register (Register 0x35, Bits[6:4]) is a 3-bit
register that allows the H-clock frequency to be reduced by 1/2,
1/4, 1/6, 1/8, 1/10, 1/12, or 1/14. The reduced frequency only
occurs for H1 to H4 pulses that are located within the HBLK area.

be used, such as adding a separate sequence to clamp during the
entire line of OB pixels. This requires configuring a separate
V-sequence for reading the OB lines.

The CLPMASKSTART and CLPMASKEND registers can be used
to disable the CLPOB on a few lines without affecting the setup of
the clamp sequences.

Horizontal Timing Sequence Example

Figure 33 shows an example of a CCD layout. The horizontal
register contains 28 dummy pixels that occur on each line

V

EFFECTIVE IMAGE AREA

clocked from the CCD. In the vertical direction, there are 10
optical black (OB) lines at the front of the readout and two at
the back of the readout. The horizontal direction has four OB
pixels in the front and 48 OB pixels in the back.

Figure 34 shows the basic sequence layout to use during the
effective pixel readout. The 48 OB pixels at the end of each line
are used for CLPOB signals. PBLK is optional and it is often
used to blank the digital outputs during the noneffective CCD

4 OB PIXELS

HORIZONTAL CCD REGIST ER

H

48 OB PIXELS

pixels. HBLK is used during the vertical shift interval.

The HBLK, CLPOB, and PBLK parameters are programmed in
the V-sequence registers. More elaborate clamping schemes can

28 DUMMY PIXELS

Figure 33. CCD Configuration Example

Table 14. HBLK Width Register

Register Length (Bits) Range Description

HBLKWIDTH 3 1× to 1/14× pixel rate Controls H1 to H4 width during HBLK as a fraction of pixel rate
0: same frequency as the pixel rate
1: 1/2 pixel frequency, that is, doubles the H1 to H4 pulse width
2: 1/4 pixel frequency
3: 1/6 pixel frequency
4: 1/8 pixel frequency
5: 1/10 pixel frequency
6: 1/12 pixel frequency
7: 1/14 pixel frequency

OPTICAL BLACK

OPTICAL BL ACK

2 VERTICAL
OB LINES

10 VERTICAL
OB LINES

05586-032

HD

CCDIN

SHP

SHD

HL/H1/H3

H2/H4

HBLK

PBLK

CLPOB

VERTICAL SHI FT VERT. SHIFT

DUMMY EFFECTIVE PIXELS

Figure 34. Horizontal Sequence Example

Rev. A | Page 23 of 84

OPTICAL BLACK

5586-033

AD9923A

,

VERTICAL TIMING GENERATION

The AD9923A provides a very flexible solution for generating
vertical CCD timing; it can support multiple CCDs and different
system architectures. The 13-phase vertical transfer clocks, XV1 to
XV13, are used to shift lines of pixels into the horizontal output
register of the CCD. The AD9923A allows these outputs to be
individually programmed into various readout configurations,
using a four-step process as shown in Figure 35.

1. Use the vertical pattern group registers to create the individual

pulse patterns for XV1 to XV13.

2. Use the V-pattern groups to build the sequences and add more

information.

CREATE THE VERTICAL PATTERN GROUPS,

1

UP TO FOUR TOGGLE POSITIONS FOR EACH OUTPUT.

XV1

XV2

VPAT 0

XV3

XV11

XV12

V-SEQUENCE 0
(VPAT0, 1 REP)

3. Construct the readout for an entire field by dividing the field

into regions and assigning a sequence to each region. Each
field can contain up to nine regions to accommodate different
steps, such as high speed line shifts and unique vertical line
transfers, of the readout. The total number of V-patterns,
V-sequences, and fields are programmable and limited by the
number of registers. High speed line shifts and unique vertical
transfers are examples of the different steps required for
readout.

4. Use the MODE register to combine fields in any order for

various readout configurations.

BUILD THE V-SEQUENCES BY ADDING START POLARITY,

2

LINE START POSITION, NUMBER O F REPEATS, ALTERNATI ON
GROUP A/B INF ORMATIO N, AND HBLK/CLPOB PULSES.

XV1

XV2

XV3

XV11

XV12

XV1

XV2

VPAT 1

XV3

XV11

XV12

USE THE MODE REGISTER TO CONTRO L WHICH FI ELDS

4

ARE USED, AND IN WHAT ORDER (MAXIMUM OF SEVE N
FIELDS MAY BE COMBINED IN ANY ORDER).

FIELD 0

FIELD 3

FIELD 1 FIELD 2

FIELD 4

V-SEQUENCE 1
(VPAT1, 2 REP)

V-SEQUENCE 2
(VPAT1, N REP)

3

FIELD 0

XV1

XV2

XV3

XV11

XV12

XV1

XV2

XV3

XV11

XV12

BUILD EACH FIELD BY DIVIDI NG IT I NTO DIFF ERENT
REGIONS AND ASSIGNING A V-SEQUENCE TO EACH
(MAXIMUM OF NINE REGI ONS IN EACH FI ELD).

REGION 0: USE V-SEQUENCE 2

REGION 1: USE V-SEQUENCE 0

REGION 2: USE V-SEQUENCE 3

REGION 3: USE V-SEQUENCE 0

FIELD 5

FIELD 1 FIELD 4

Figure 35. Summary of Vertical Timing Generation

FIELD 2

REGION 4: USE V-SEQUENCE 2

FIELD 1

FIELD 2

05586-034

Rev. A | Page 24 of 84

AD9923A

X

Vertical Pattern (VPAT) Groups

A vertical pattern (VPAT) group defines the individual pulse
pattern for each XV1 to XV13 output signal. Tab le 1 5 summarizes
the registers that are available for generating each VPAT group.
The first, second, third, fourth, fifth, and sixth toggle positions
(XVTOG1, XVTOG2, XVTOG3, XVTOG4, XVTOG5,
XVTOG6) are the pixel locations where the pulse transitions. All
toggle positions are 13-bit values that can be placed anywhere in
the horizontal line.

More registers are included in the vertical sequence registers to
specify the output pulses: XV1POL to XV13POL specifies the

Table 15. Vertical Pattern Group Registers

Register Length (Bits) Range Description

XVTOG1 13 0 to 8191 pixel location First toggle position within line for each XV1 to XV12 output
XVTOG2 13 0 to 8191 pixel location Second toggle position
XVTOG3 13 0 to 8191 pixel location Third toggle position
XVTOG4 13 0 to 8191 pixel location Fourth toggle position
XVTOG5 13 0 to 8191 pixel location Fifth toggle position
XVTOG6 13 0 to 8191 pixel location Sixth toggle position

START POSITION OF VERTICAL PATTERN GROUP IS PROGRAMMABLE IN VERTICAL SEQUENCE REGISTERS.

start polarity for each signal, VSTART specifies the start
position of the VPAT group, and VLEN designates the total
length of the VPAT group, which determines the number of
pixels between each pattern repetition, if repetitions are used.

To achieve the best possible noise performance, ensure that
VSTART + VLEN < the end of the H-blank region.

Toggle positions programmed to either Pixel 0 or Pixel 8191 are
ignored. The toggle positions of unused XV-channels must be
programmed to either Pixel 0 or Pixel 8191. This prevents unpre­dictable behavior because the default values of the V-pattern
group registers are unknown.

HD

4

XV1

XV2

V12

PROGRAMMABLE SETTINGS:

1

START POLARITY (LOCATED IN V-SEQUENCE REGISTERS).

2

FIRST TOGGLE POSITION.

3

SECOND TOGGLE POSITION (A TOTAL OF SIX TOGGLE POSITIONS ALSO AVAILABLE FOR MORE COMPLEX PATTERNS).

4

TOTAL P ATTERN LENG TH FOR ALL VERTICAL OUTPUTS (LOCATED IN VERTICAL SEQUENCE REGIS TERS).

1

2

3

1

23

1

2

3

05586-035

Figure 36. Vertical Pattern Group Programmability

Rev. A | Page 25 of 84

AD9923A

X

Vertical Sequences (VSEQ)

A vertical sequence (VSEQ) is created by selecting one of the
V-pattern groups and adding repeats, a start position, and
horizontal clamping and blanking information. Each VSEQ is
programmed using the registers shown in Tab l e 1 6 . Figure 37
shows how each register is used to generate a V-sequence.

The VPATSELA and VPATSELB registers select the V-pattern
group that is used in a given V-sequence. Having two groups
available allows each vertical output to be mapped to a different
V-pattern group. The selected V-pattern group can have
repetitions added for high speed line shifts or line binning by
using the VREP registers for odd and even lines. Generally, the
same number of repetitions is programmed into both registers.
If a different number of repetitions is required on odd and even
lines, separate values can be used for each register (see the

1

HD

3

V1 TO XV13

V-PATTERN GROUP

44

VREP 2

Generating Line Alternation for V-Sequences and HBLK
section). The VSTARTA and VSTARTB registers specify the pixel
location where the V-pattern group starts. The VMASK register is
used in conjunction with the FREEZE/RESUME registers to enable
optional masking of the XV outputs. Either or both of the
FREEZE1/RESUME1 and FREEZE2/RESUME2 registers can be
enabled.

The line length (in pixels) is programmable using the HDLEN
registers. Each V-sequence can have a different line length to
accommodate various image readout techniques. The maximum
number of pixels per line is 8192. Note that the last line of the
field can be programmed separately using the HDLAST register,
located in the field register (see Ta ble 1 7).

2

VREP 3

CLPOB

PBLK

HBLK

PROGRAMMABLE SETTING S FOR EACH VERTICAL SEQ UENCE:

1

START POSI TION I N THE LINE OF SELECTED V-PATT ERN GROUP.

2

HD LINE LENG TH.

3

V-PATTERN SELECT (VPATSEL) TO SELECT ANY V-PATTERN GROUP.

4

NUMBER OF REPETITIONS OF THE V-PATTERN GROUP (IF NEEDED).

5

START POL ARITY AND TO GGLE POSITIO NS FOR CLP OB AND PBLK SIG NALS.

6

MASKING POLARITY AND TOGGLE POSITIONS FOR HBLK SIGNAL.

6

5

05586-036

Figure 37. V-Sequence Programmability

Rev. A | Page 26 of 84