ANALOG DEVICES AD9920A Service Manual

12-Bit CCD Signal Processor with V-Driver

FEATURES

Integrated 19-channel V-driver

1.8 V AFETG core
24 programmable vertical clock signals
Correlated double sampler (CDS) with −3 dB, 0 dB,

+3 dB, and +6 dB gain
12-bit, 40.5 MHz analog-to-digital converter (ADC)
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with ~400 ps resolution
On-chip 3 V horizontal and RG drivers
General-purpose outputs (GPOs) for shutter and

system support
On-chip sync generator with external sync input
On-chip 1.8 V low dropout (LDO) regulator
105-ball, 8 mm × 8 mm CSP_BGA package

APPLICATIONS

Digital still cameras

and Precision Timing Generator

AD9920A

GENERAL DESCRIPTION

The AD9920A is a highly integrated charge-coupled device (CCD)
signal processor for digital still camera applications. It includes a
complete analog front end (AFE) with analog-to-digital conversion,
combined with a full-function programmable timing generator
and 19-channel vertical driver (V-driver). The timing generator
is capable of supporting up to 24 vertical clock signals to control
advanced CCDs. The on-chip V-driver supports up to 19 channels
for use with six-field CCDs. A Precision Timing® core allows adjust-
ment of high speed clocks with approximately 400 ps resolution
at 40.5 MHz operation. The AD9920A also contains six GPOs
that can be used for shutter and system functions.

The analog front end includes black level clamping, variable
gain CDS, and a 12-bit ADC. The timing generator provides all
the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate
pulses, substrate clock, and substrate bias control.

The AD9920A is specified over an operating temperature range
of −25°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

REFT REFB

CCDIN

LDOIN

LDOOUT

RG

HL

H1 TO H8

V1A TO V6 (3-LEVEL)

V7 TO V16 (2-LEVEL)

SUBCK

–3dB, 0dB, +3dB, +6dB

CDS

LDO
REG

HORIZONTAL

VERTICAL

DRIVER

XSUBCNT

DRIVERS

XV1 TO XV24

8

19

VGA

6dB TO 42d B

24
GPO5
GPO6

XSUBCK

VREF

VERTICAL

TIMING

CONTROL

6

GPO7, GPO8

12-BIT

ADC

CLAMP

INTERN AL CLOCK S

PRECISION

TIMING

GENERATOR

SYNC

GENERATOR

HD VD

Figure 1.

12

CLI

AD9920A

INTERNAL

REGISTERS

CLOGPO1 TO GPO4,

SYNC/RST

D0 TO D11

DCLK

SL
SCK

SDATA

06878-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.

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Tel: [phone] www.analog.com
Fax: [phone] ©2009–2010 Analog Devices, Inc. All rights reserved.

AD9920A

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications ..................................................................................... 4

Digital Specifications ................................................................... 5

Analog Specifications ................................................................... 5

Timing Specifications .................................................................. 7

Vertical Driver Specifications ..................................................... 8

Absolute Maximum Ratings .......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution ................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11

Typical Performance Characteristics ........................................... 14

Equivalent Circuits ......................................................................... 15

Terminology .................................................................................... 16

Theory of Operation ...................................................................... 17

H-Counter Behavior in Slave Mode ......................................... 17

High Speed Precision Timing Core ........................................... 18

Digital Data Outputs .................................................................. 22

Horizontal Clamping and Blanking ......................................... 23

Horizontal Timing Sequence Example .................................... 30

Vertical Timing Generation ...................................................... 32

Vertical Sequences (VSEQ) ....................................................... 34

Vertical Timing Example ........................................................... 51

Internal Vertical Driver Connections (18-Channel Mode) .. 53

Internal Vertical Driver Connections (19-Channel Mode) .. 54

Output Polarity of Vertical Transfer Clocks and Substrate

Clock ............................................................................................ 55



V-Driver Slew Rate Control ...................................................... 60

Shutter Timing Control ............................................................. 60

Substrate Clock Operation (SUBCK) ...................................... 60

Field Counters ............................................................................. 63

General-Purpose Outputs (GPOs) .......................................... 64

GP Lookup Table (LUT) ............................................................ 68

Complete Exposure/Readout Operation Using Primary

Counter and GPO Signals ......................................................... 69

SG Control Using GPO ............................................................. 71

Manual Shutter Operation Using Enhanced SYNC Modes .. 73

Analog Front End Description and Operation ...................... 77

Applications Information .............................................................. 79

Power-Up Sequence for Master Mode ..................................... 79

Power-Up Sequence for Slave Mode ........................................ 81

Power-Down Sequence for Master and Slave Modes ............ 83

Additional Restrictions in Slave Mode .................................... 84

Vertical Toggle Position Placement Near Counter Reset ...... 85

Standby Mode Operation .......................................................... 86

CLI Frequency Change .............................................................. 86

Circuit Layout Information ........................................................... 88

Typical 3 V System ..................................................................... 88

External Crystal Application .................................................... 88

Circuit Configurations .............................................................. 89

Serial Interface ................................................................................ 93

Serial Interface Timing .............................................................. 93

Layout of Internal Registers ...................................................... 94

Updating New Register Values ................................................. 95

Complete Register Listing ............................................................. 96

Outline Dimensions ..................................................................... 112

Ordering Guide ........................................................................ 112



Rev. B | Page 2 of 112

AD9920A

REVISION HISTORY

6/10—Rev. A to Rev. B

Changes to Figure 1 ........................................................................... 1

Changes to Figure 9, Figure 10, Figure 12, and Figure 13 ......... 15

Moved Terminology Section .......................................................... 16

Changes to Figure 15 ...................................................................... 17

Moved Generating HBLK Line Alternation Section .................. 24

Moved Figure 32 .............................................................................. 25

Moved Figure 33 .............................................................................. 27

Changes to Vertical Sequences (VSEQ) Section ......................... 34

Changes to Special Vertical Sequence Alternation

(SVSA) Mode Section ..................................................................... 38

Added Table 18; Renumbered Tables Sequentially ..................... 44

Deleted Figure 77; Renumbered Figures Sequentially ............... 61

Changes to SUBCK Low Speed Operation Section

and Table 43 ..................................................................................... 61

Changes to Figure 81 ...................................................................... 62

Changes to Table 45 ........................................................................ 64

Changes to Scheduled Toggles Section and Figure 85 ............... 66

Changes to Figure 86, ShotTimer Sequences Section,

and Figure 87 ................................................................................... 67

Changes to Complete Exposure/Readout Operation

Using Primary Counter and GPO Signals Section ..................... 69

Changes to Triggered Control of GPO5 Section ......................... 71

Changes to Figure 96 ...................................................................... 75

Changes to Figure 100 .................................................................... 77

Changes to Figure 102 .................................................................... 80

Changes to Power-Up Sequence for Slave Mode Section .......... 81

Changes to Figure 103 .................................................................... 82

Changes to Power-Down Sequence for Master and

Slave Modes Section........................................................................ 83

Added Table 48; Renumbered Tables Sequentially ..................... 86

Changes to Figure 108 .................................................................... 88

Changes to Figure 109 .................................................................... 89

Changes to Figure 110 .................................................................... 90

Changes to Figure 111 .................................................................... 91

Changes to Figure 112 .................................................................... 92

Changes to Layout of Internal Registers Section

and Figure 115 ................................................................................. 94

Changes to Table 53 ........................................................................ 97

Changes to Table 57 ........................................................................ 99

Changes to Table 59 ...................................................................... 101

Changes to Table 61 ...................................................................... 105

Changes to Table 63 ...................................................................... 108

Updated Outline Dimensions ...................................................... 112

6/09—Revision A: Initial Version

Rev. B | Page 3 of 112

AD9920A

SPECIFICATIONS

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

TEMPERATURE RANGE

Operating −25 +85 °C
Storage −65 +150 °C

POWER SUPPLY VOLTAGE INPUTS

AVDD AFE analog supply 1.6 1.8 2.0 V
TCVDD Timing core supply 1.6 1.8 2.0 V
CLIVDD CLI input supply 1.6 3.0 3.6 V
RGVDD RG, HL driver supply 2.1 3.0 3.6 V
HVDD1 and HVDD2 H1 to H8 driver supplies 2.1 3.0 3.6 V
DVDD Digital logic supply 1.6 1.8 2.0 V
DRVDD Parallel data output driver supply 1.6 3.0 3.6 V
IOVDD Digital I/O supply 1.6 3.0 3.6 V

V-DRIVER POWER SUPPLY VOLTAGES

VDVDD V-driver/logic supply 1.6 3.0 3.6 V
VH1, VH2 V-driver high supply 11.0 15.0 16.5 V
VL1, VL2 V-driver low supply −8.5 −7.5 −5.5 V
VM1, VM2 V-driver midsupply −1.5 0.0 +1.5 V
VLL SUBCK low supply −11.0 −7.5 −5.5 V
VH1, VH2 to VL1, VL2, VLL 23.5 V

1

VMM

2

LDO

LDOIN LDO supply input 2.5 3.0 3.6 V
Output Voltage 1.8 1.9 2.05 V
Output Current 60 100 mA

POWER SUPPLY CURRENTS—40.5 MHz

OPERATION
AVDD 1.8 V 27 mA
TCVDD 1.8 V 5 mA
CLIVDD 3 V 1.5 mA
RGVDD 3.3 V, 20 pF RG load, 20 pF HL load 10 mA
HVDD1 and HVDD2

3

DVDD 1.8 V 9.5 mA
DRVDD

IOVDD

POWER SUPPLY CURRENTS—STANDBY

MODE OPERATION
Standby1 Mode 20 mA
Standby2 Mode 5 mA

Standby3 Mode 1.5 mA
MAXIMUM CLOCK RATE (CLI) 40.5 MHz
MINIMUM CLOCK RATE (CLI) 10 MHz

1

VMM must be greater than VLL and less than VDVDD.

2

LDO should be used only for the AD9920A 1.8 V supplies, not for external circuitry.

3

The total power dissipated by the HVDD (or RGVDD) can be approximated using the following equation:

Total HVDD Power = (CL × HVDD × Pixel Frequency) × HVDD

SUBCK midsupply VLL 0.0 VDVDD V

3.3 V, 480 pF total load on H1 to H8 59 mA

3 V, 10 pF load on each data output pin

6 mA

(D0 to D11)
3 V, depends on load and output

2 mA

frequency of digital I/O

Rev. B | Page 4 of 112

AD9920A

DIGITAL SPECIFICATIONS

IOVDD = 1.6 V to 3.6 V, RGVDD = HVDD1 and HVDD2 = 2.7 V to 3.6 V, CL = 20 pF, T

Table 2.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

LOGIC INPUTS (IOVDD)

High Level Input Voltage VIH V
Low Level Input Voltage VIL 0.6 V
High Level Input Current IIH 10 μA
Low Level Input Current IIL 10 μA
Input Capacitance CIN 10 pF

LOGIC OUTPUTS (IOVDD, DRVDD)

High Level Output Voltage VOH I
Low Level Output Voltage VOL I

RG and H-DRIVER OUTPUTS (HVDD1,

= 2 mA VDD − 0.5 V

OH

= 2 mA 0.5 V

OL

HVDD2, and RGVDD)
High Level Output Voltage VOH Maximum current VDD − 0.5 V
Low Level Output Voltage VOL Maximum current 0.5 V
Maximum H1 to H8 Output Current Programmable 30 mA
Maximum HL and RG Output Current Programmable 17 mA
Maximum Load Capacitance Each output 60 pF

CLI INPUT With CLO oscillator disabled

High Level Input Voltage V
Low Level Input Voltage V

CLIVDD/2 + 0.5 V

IHCLI

CLIVDD/2 − 0.5 V

ILCLI

to T

MIN

− 0.6 V

DD

, unless otherwise noted.

MAX

ANALOG SPECIFICATIONS

AVDD = 1.8 V, f

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

1

CDS

DC Restore AVDD − 0.5 V 1.21 1.3 1.44 V
Allowable CCD Reset Transient Limit is the lower of AVDD + 0.3 V or 2.2 V 0.5 0.8 V
CDS Gain Accuracy VGA gain = 6.3 dB (Code 15, default value)

−3 dB CDS Gain −3.1 −2.6 −2.1 dB
0 dB CDS Gain −0.6 −0.1 +0.4 dB
+3 dB CDS Gain 2.7 3.2 3.7 dB
+6 dB CDS Gain 5.2 5.7 6.2 dB

Maximum Input Range Before

Saturation

−3 dB CDS Gain 1.4 V p-p
0 dB CDS Gain 1.0 V p-p
+3 dB CDS Gain 0.7 V p-p
+6 dB CDS Gain 0.5 V p-p

Allowable OB Pixel Amplitude

0 dB CDS Gain (Default) −100 +200 mV
+6 dB CDS Gain −50 +100 mV

VARIABLE GAIN AMPLIFIER (VGA)

Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range

Low Gain VGA Code 15, default 6.3 dB
Maximum Gain VGA Code 1023 42.4 dB

= 40.5 MHz, typical timing specifications, T

CLI

1

MIN

to T

, unless otherwise noted.

MAX

Rev. B | Page 5 of 112

AD9920A

Parameter Test Conditions/Comments Min Typ Max Unit

BLACK LEVEL CLAMP

Clamp Level Resolution 1024 Steps

Clamp Level Measured at ADC output

Minimum Clamp Level Code 0 0 LSB
Maximum Clamp Level Code 1023 255 LSB

ADC

Resolution 12 Bits

Differential Nonlinearity (DNL)

No Missing Codes Guaranteed

Integral Nonlinearity (INL)

Full-Scale Input Voltage 2.0 V
VOLTAGE REFERENCE

Reference Top Voltage (REFT) 1.4 V

Reference Bottom Voltage (REFB) 0.4 V
SYSTEM PERFORMANCE Includes entire signal chain

Gain Accuracy 0 dB CDS gain

Low Gain

Maximum Gain VGA Code 1023 41.8 42.3 42.8 dB
Peak Nonlinearity, 1 V Input Signal
Total Output Noise

2

Power Supply Rejection (PSR)

1

Input signal characteristics are defined as shown in Figure 2.

2

See the Terminology section.

2

2

±3.0 LSB

±0.5 LSB

VGA Code 15

5.7 6.2 6.7 dB

Gain = (0.0358 × code) + 5.76 dB

2

6 dB VGA gain, 0 dB CDS gain applied 0.1 0.3 %

AC-grounded input, 6 dB VGA gain

0.6 LSB rms

applied

2

Measured with step change on supply 40 dB

MAXIMUM INPUT LIMIT = L E SSE R OF

2.2V OR AVDD + 0.3V

800mV
MAXIMUM

500mV TYP

RESET TRANSIENT

200mV MAX

OPTICAL BL ACK PI X EL

Figure 2. Input Signal Characteristics

+1.8V TYP (AVDD)

+1.3V TYP (AVDD – 0.5V)
DC RESTORE VOLTAGE

1V MAXIMUM INPUT SIGNAL RANGE
(0dB CDS GAIN)

0V (AVSS)

MINIMUM INPUT LIMIT
(AVSS – 0.3V )

06878-002

Rev. B | Page 6 of 112

AD9920A

TIMING SPECIFICATIONS

CL = 20 pF, AVDD = DVDD = TCVDD = 1.8 V, f

Table 4.

Parameter

MASTER CLOCK See Figure 18

CLI Clock Period t
CLI High/Low Pulse Width 0.8 × t
Delay from CLI Rising Edge to Internal

Pixel Position 0

SLAVE MODE SPECIFICATIONS See Figure 105

VD Falling Edge to HD Falling Edge t
HD Falling Edge to CLI Rising Edge

HD Falling Edge to CLO Rising Edge
CLI Rising Edge to SHPLOC Internal sample edge t

AFE

SHPLOC Sample Edge to SHDLOC

Sample Edge

SHDLOC Sample Edge to SHPLOC

Sample Edge
AFE Pipeline Delay See Figure 26 16 Cycles
AFE CLPOB Pulse Width 2 20 Pixels

DATA OUTPUTS

Output Delay from DCLK Rising Edge See Figure 25 tOD 1 ns
Pipeline Delay from SHP/SHD

Sampling to Data Output

SERIAL INTERFACE

Maximum SCK Frequency

SL to SCK Setup Time tLS 10 ns
SCK to SL Hold Time tLH 10 ns
SDATA Valid to SCK Rising Edge Setup tDS 10 ns
SCK Falling Edge to SDATA Valid Hold tDH 10 ns

TIMING CORE SETTING RESTRICTIONS

Inhibited Region for SHP Edge

Location
Inhibited Region for SHP or SHD with

Respect to H-Clocks

1

2, 3, 4

RETIME = 0, MASK = 0 t

RETIME = 0, MASK = 1 t

RETIME = 1, MASK = 0 t

RETIME = 1, MASK = 1 t

Inhibited Region for DOUTPHASE Edge

Location

1

Applies only to slave mode operation. The inhibited area for SHP is needed to meet the timing requirement for t

2

When the HBLKRETIME bits (Address 0x35, Bits[3:0]) are enabled, the inhibit region for the SHD location changes to the inhibit region for the SHP location.

3

When the HBLK masking polarity registers (V-sequence Register 0x18[24:21]) are set to 0, the H-edge reference becomes HxNEGLOC.

4

The H-clock signals that have SHP/SHD inhibit regions depend on the HCLK mode: Mode 1 = H1; Mode 2 = H1, H2; Mode 3 = H1, H3; and 3-Phase Mode = Phase 1,

Phase 2, and Phase 3.

= 40.5 MHz, unless otherwise noted.

CLI

Test Conditions/
Comments Symbol Min Typ Max Unit

24.7 ns

CONV

/2 t

CONV

t

Only valid if OSC_RST
Only valid if OSC_RST

See Figure 23

See Figure 23

= 0
= 1

t

t

6 ns

CLIDLY

0 VD period − t

VDHD

t

3 t

HDCLI

t

3 t

HDCLO

3 t

CLISHP

0.8 × t

S1

0.8 × t

S2

CONV

CONV

/2 t

/2 t

/2 1.2 × t

CONV

/2 t

CONV

/2 t

CONV

/2 ns

CONV

ns

CONV

− 2 ns

CONV

− 2 ns

CONV

− 2 ns

CONV

− tS2 ns

CONV

− tS1 ns

CONV

16 Cycles

40.5 MHz

Must not exceed CLI

f

SCLK

frequency

See Figure 23 t

50 62

SHPINH

Edge
location

See Figure 23 and
Figure 24

HxNEGLOC − 14 HxNEGLOC − 2

SHDINH

Edge
location

HxPOSLOC − 14 HxPOSLOC − 2

SHDINH

Edge
location

HxNEGLOC − 14 HxNEGLOC − 2

SHPINH

Edge
location

HxPOSLOC − 14 HxPOSLOC − 2

SHPINH

Edge
location

See Figure 23

t

SHDLOC + 1 SHDLOC + 12

DOUTINH

Edge
location

for proper H-counter reset operation.

CLISHP

Rev. B | Page 7 of 112

AD9920A

VERTICAL DRIVER SPECIFICATIONS

VH1, VH2 = 12 V; VM1, VM2, VMM = 0 V; VL1, VL2, VLL = −6 V; CL shown in load model; TA = 25°C.

Table 5.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

V1A TO V13

Simplified load conditions, 3000 pF to

ground + 30 Ω in series, SRSW = VSS
Delay Time, VL to VM and VM to VH t
Delay Time, VM to VL and VH to VM t
Rise Time, VL to VM t
Rise Time, VM to VH t
Fall Time, VM to VL t
Fall Time, VH to VM t

, t

40 ns

PLM

PMH

, t

40 ns

PML

PHM

150 ns

RLM

315 ns

RMH

250 ns

FML

165 ns

FHM

Output Currents

At −7.25 V 10 mA
At −0.25 V −22 mA
At +0.25 V 22 mA
At +14.75 V −10 mA

RON 35 Ω

V14, V15, V16

Simplified load conditions, 3000 pF to

ground + 30 Ω in series
Delay Time, VL to VM t
Delay Time, VM to VL t
Rise Time, VL to VM t
Fall Time, VM to VL t

45 ns

PLM

45 ns

PML

345 ns

RLM

280 ns

FML

Output Currents

At −7.25 V 10 mA
At −0.25 V −7 mA

RON 55 Ω

SUBCK OUTPUT Simplified load conditions, 1000 pF to ground

Delay Time, VLL to VH t
Delay Time, VH to VLL t
Delay Time, VLL to VMM t
Delay Time, VMM to VH t
Delay Time, VH to VMM t
Delay Time, VMM to VLL t
Rise Time, VLL to VH t
Rise Time, VLL to VMM t
Rise Time, VMM to VH t
Fall Time, VH to VLL t
Fall Time, VH to VMM t
Fall Time, VMM to VLL t

50 ns

PLH

50 ns

PHL

50 ns

PLM

50 ns

PMH

50 ns

PHM

50 ns

PML

50 ns

RLH

55 ns

RLM

50 ns

RMH

55 ns

FHL

100 ns

FHM

40 ns

FML

Output Currents

At −7.25 V 20 mA
At −0.25 V −12 mA
At +0.25 V 12 mA
At +14.75 V −20 mA

RON 35 Ω

SRCTL INPUT RANGE Valid only when SRSW is high 0.8 VDVDD V

Rev. B | Page 8 of 112

AD9920A

V-DRIVER

INPUT

V-DRIVER

OUTPUT

50%

10%

90%

t

PLM

t

,

t

,

RLM

t

RMH

RLH

,

t

,

t

PMH

PLH

50%

90%

10%

t

PML

t

,

FML

t

Figure 3. Definition of V-Driver Timing Specifications

PHM

,

t

FHM

,

t

PHL

,

t

FHL

06878-003

Rev. B | Page 9 of 112

AD9920A

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

AVDD to AVSS −0.3 V to +2.2 V
TCVDD to TCVSS −0.3 V to +2.2 V
HVDD1, HVDD2 to HVSS1, HVSS2 −0.3 V to +3.9 V
RGVDD to RGVSS −0.3 V to +3.9 V
DVDD to DVSS −0.3 V to +2.2 V
DRVDD to DRVSS/LDOVSS −0.3 V to +3.9 V
IOVDD to IOVSS −0.3 V to +3.9 V
VDVDD to VDVSS −0.3 V to +3.9 V
CLIVDD to TCVSS −0.3 V to +3.9 V
VH1, VH2 to VL1, VL2, VLL −0.3 V to +25.0 V
VH1, VH2 to VDVSS −0.3 V to +17.0 V
VL1, VL2 to VDVSS −17.0 V to +0.3 V
VM1, VM2 to VDVSS −6.0 V to +3.0 V
VLL to VDVSS −17.0 V to +0.3 V
VMM to VDVSS VLL − 0.3 V to VDVDD + 0.3 V
V1A to V16 to VDVSS VLx − 0.3 V to VHx + 0.3 V
RG and HL Outputs to RGVSS −0.3 V to RGVDD + 0.3 V
H1 to H8 Outputs to HVSSx −0.3 V to HVDDx + 0.3 V
VDR_EN, XSUBCNT, SRCTL, SRSW

to VDVSS

Digital Outputs to IOVSS −0.3 V to IOVDD + 0.3 V
Digital Inputs to IOVSS −0.3 V to IOVDD + 0.3 V
SCK, SL, SDATA to DVSS −0.3 V to DVDD + 0.3 V
REFT, REFB, CCDIN to AVSS −0.3 V to AVDD + 0.3 V
Junction Temperature 150°C
Lead Temperature

(Soldering, 10 sec)

−0.3 V to VDVDD + 0.3 V

350°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 7. Thermal Resistance

Package Type θJA Unit

CSP_BGA (BC-105-1) 40.3 °C/W

ESD CAUTION

Rev. B | Page 10 of 112

AD9920A

A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1 CORNER

1110987654321

Figure 4. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Type1Description

L6 AVDD P Analog Supply.
J7, K8 AVSS P Analog Supply Ground.
A10 DVDD P Digital Logic Supply.
A9 DVSS P Digital Logic Ground.
L5 CLIVDD P CLI Input Supply.
K6 TCVDD P Analog Timing Core Supply.
K4 TCVSS P Analog Timing Core Ground.
A2 DRVDD P Data Driver Supply.
B2 DRVSS/LDOVSS P Data Driver and LDO Ground.
E1 HVDD1 P H-Driver Supply.
E2 HVSS1 P H-Driver Ground.
G1 HVDD2 P H-Driver Supply.
G2 HVSS2 P H-Driver Ground.
J1 HVDD2 P H-Driver Supply.
J2 HVSS2 P H-Driver Ground.
L3 RGVDD P RG, HL Driver Supply.
K3 RGVSS P RG, HL Driver Ground.
B1 LDOIN P LDO 3.3 V Input.
C1 LDOOUT P LDO Output Voltage.
H11 IOVDD P Digital I/O Supply.
G11 IOVSS P Digital I/O Ground.
C11 VDVDD P V-Driver Logic Supply (3 V).
C10 VDVSS P V-Driver Ground.
E3 VM1 P V-Driver Midsupply.
D3 VL1 P V-Driver Low Supply.
C3 VH1 P V-Driver High Supply.
J3 VH2 P V-Driver High Supply.
H3 VL2 P V-Driver Low Supply.
F3 VM2 P V-Driver Midsupply.
G3 VMM P V-Driver Midsupply for SUBCK Output.
J4 VLL P V-Driver Low Supply for SUBCK Output.
L7 CCDIN AI CCD Signal Input.
K7 CCDGND AI CCD Ground.
C2 SRCTL AI Slew Rate Control Pin. Tie to VDVSS if not used.
L8 REFT AO Voltage Reference Top Bypass.
L9 REFB AO Voltage Reference Bottom Bypass.
D11 VD DIO Vertical Sync Pulse.
E10 HD DIO Horizontal Sync Pulse.

INDEX AREA

BOTTOM V I EW

(Not to S cale)

A
B
C
D
E
F
G
H
J
K
L

06878-004

Rev. B | Page 11 of 112

AD9920A

Pin No. Mnemonic Type1Description

E11

SYNC/RST
K9 SL DI 3-Wire Serial Load Pulse (Internal Pull-Up Resistor).
K10 SDATA DI 3-Wire Serial Data.
L10 SCK DI 3-Wire Serial Clock.
B11 VDR_EN DI Enable V-Outputs When High.
K11 XSUBCNT DI XSUBCNT Input to SUBCK Buffer.
C9 SRSW DI Slew Rate Control Enable. Tie to ground to disable.
J6

LEGEN
J5 CLI DI Reference Clock Input.
K5 CLO DO Clock Output for Crystal.
F10 GPO1 DO General-Purpose Output.
H9 GPO2 DO General-Purpose Output.
G10 GPO3 DO General-Purpose Output.
F11 GPO4 DO General-Purpose Output.
H10 GPO7 DO General-Purpose Output.
J11 GPO8 DO General-Purpose Output.
B9 D0 DO Data Output (LSB).
C6 D1 DO Data Output.
C7 D2 DO Data Output.
A8 D3 DO Data Output.
A7 D4 DO Data Output.
B7 D5 DO Data Output.
B6 D6 DO Data Output.
A6 D7 DO Data Output.
A5 D8 DO Data Output.
B4 D9 DO Data Output.
A4 D10 DO Data Output.
A3 D11 DO Data Output (MSB).
B3 DCLK DO Data Clock Output.
D1 H1 DO CCD Horizontal Clock.
D2 H2 DO CCD Horizontal Clock.
F1 H3 DO CCD Horizontal Clock.
F2 H4 DO CCD Horizontal Clock.
H1 H5 DO CCD Horizontal Clock.
H2 H6 DO CCD Horizontal Clock.
K1 H7 DO CCD Horizontal Clock.
K2 H8 DO CCD Horizontal Clock.
L2 HL DO CCD Horizontal Clock.
L4 RG DO CCD Reset Gate Clock.
G9 V1A VO3 CCD Vertical Transfer Clock. Three-level output (XV1 + XV16).

G6 V1B VO3 CCD Vertical Transfer Clock. Three-level output (XV1 + XV17).
G5 V2A VO3 CCD Vertical Transfer Clock. Three-level output (XV2 + XV18).
E9 V2B VO3 CCD Vertical Transfer Clock. Three-level output (XV2 + XV19).
J9 V3A VO3 CCD Vertical Transfer Clock. Three-level output (XV3 + XV20).
F6 V3B VO3

F5 V4 VO3 CCD Vertical Transfer Clock. Three-level output (XV4 + XV22).
E5 V5 VO3

D10 V6 VO3

F9 V7 VO2 CCD Vertical Transfer Clock. Two-level output (XV7).
F7 V8 VO2 CCD Vertical Transfer Clock. Two-level output (XV8).

DO SYNC Pin (Internal Pull-Up Resistor)/External Reset Input (Active Low).

DI Legacy Mode Enable Bar. Tie to ground for legacy 18-channel mode.

CCD Vertical Transfer Clock. Three-level output. LEGEN

is low, XV3 + XV21. LEGEN is high,

XV23 + XV21.

CCD Vertical Transfer Clock. Three-level output. LEGEN

is low, XV5 + XV23. LEGEN is high,

XV5 + GPO5.
CCD Vertical Transfer Clock. Three-level output. LEGEN

is low, XV6 + XV24. LEGEN is high,

XV6 + GPO6.

Rev. B | Page 12 of 112

AD9920A

Pin No. Mnemonic Type1Description

D9 V9 VO2 CCD Vertical Transfer Clock. Two-level output (XV9).
C4 V10 VO2 CCD Vertical Transfer Clock. Two-level output (XV10).
C5 V11 VO2 CCD Vertical Transfer Clock. Two-level output (XV11).
B5 V12 VO2 CCD Vertical Transfer Clock. Two-level output (XV12).
E6 V13 VO2 CCD Vertical Transfer Clock. Two-level output (XV13).
E7 V14 VO2 CCD Vertical Transfer Clock. Two-level output (XV14).
C8 V15 VO2 CCD Vertical Transfer Clock. Two-level output (XV15).
J8 V16 VO2

CCD Vertical Transfer Clock. Two-level output (XV24). Available only when LEGEN

(19-channel mode).
G7 SUBCK VO3 CCD Substrate Clock Output.
A1, A11, B8,

NC Not Internally Connected.
B10, J10, L1,
L11

1

AI = analog input; AO = analog output; DI = digital input; DO = digital output; DIO = digital input/output; P = power; VO2 = vertical driver output, two-level;

VO3 = vertical driver output, three-level.

is high

Rev. B | Page 13 of 112

AD9920A

TYPICAL PERFORMANCE CHARACTERISTICS

400

350

3.3V, 2.0V

3.0

2.5

300

250

200

150

POWER (mW)

100

50

0

18 32 40

FREQUENCY (MHz )

3.0V, 1.8V

2.7V, 1.6V

Figure 5. AFETG Power vs. Frequency (V-Driver Not Included);

AVDD = TCVDD = DVDD = 1.8 V, All Other Supplies at 2.7 V, 3.0 V, or 3.3 V

1.0

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 0.5k 1.0k 1.5k 2.0k 2.5k 3.0k 3.5k 4.0k

ADC OUTPUT CODE

Figure 6. Typical Differential Nonlinearity (DNL) Performance

2.0

1.5

1.0

INL (LSB)

0.5

0

–0.5

06878-005

–1.0

0

0.5k 1.0k 1.5k 2.0k 2.5k 3.0k 3.5k 4.0k

ADC OUTPUT CODE

06878-007

Figure 7. Typical System Integral Nonlinearity (INL) Performance

50

45

40

35

30

25

20

15

RMS OUTPUT NOISE (LS B)

10

5

0

06878-006

0 10203040506

–3dB CD S GA IN

0dB CDS GAIN

+3dB CDS GAIN
+6dB CDS GAIN

TOTAL GAIN — CDS + VGA (dB)

06878-008

0

Figure 8. Output Noise vs. Total Gain (CDS + VGA)

Rev. B | Page 14 of 112

AD9920A

A

V

T

V

V

V

EQUIVALENT CIRCUITS

IOVDD

DD

DATA

HREE­STATE

CCDIN

R

AVSS AVSS

Figure 9. CCDIN

DVDD

DRVDD

06878-009

D0 TO D11

DIGITAL

INPUTS

RG, HL, H1 TO H8

THREE-STATE

330Ω

IOVSS

Figure 12. Digital Inputs

HVDD OR

RGVDD

06878-012

OUTPUT

DVSS DRVSS

Figure 10. Digital Data Outputs

DVDD

XSUBCNT

VDVSS

Figure 11. XSUBCNT

3.5k

Ω

06878-011

06878-010

HVSS OR

RGVSS

06878-013

Figure 13. H1 to H8, HL, RG Drivers

DVDD

Ω

VDVSS

3.5k

R

06878-014

DR_EN

Figure 14. VDR_EN

Rev. B | Page 15 of 112

AD9920A

TERMINOLOGY

Differential Nonlinearity (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of resolution for which no missing codes are
guaranteed. No missing codes guaranteed to 12-bit resolution
indicates that all 4096 codes, each for its respective input, must
be present over all operating conditions.

Integral Nonlinearity (INL)

INL is defined as the maximum deviation of the actual analog
output from the ideal output, determined by a straight line
drawn from zero scale to full scale.

Peak Nonlinearity

Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9920A from a true straight
line. The point used as zero scale occurs 0.5 LSB before the first
code transition. Positive full scale is defined as a level 1 LSB and

0.5 LSB beyond the last code transition. The deviation is measured
from the middle of each particular output code to the true straight
line. The error is then expressed as a percentage of the 2 V ADC
full-scale signal. The input signal is always appropriately amplified
to fill the ADC full-scale range.

Power Supply Rejection (PSR)

The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.

Tot a l O ut p ut Noi se

The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage using the relationship

1 LSB = (ADC Full Scale/2

where n is the bit resolution of the ADC.

For the AD9920A, 1 LSB = 0.244 mV.

n

Codes)

Rev. B | Page 16 of 112

AD9920A

V

THEORY OF OPERATION

Figure 15 shows the typical system block diagram for the AD9920A
in master mode. The CCD output is processed by the AD9920A
AFE circuitry, which consists of a CDS, black level clamp, and
ADC. The digitized pixel information is sent to the digital image
processor chip, which performs the postprocessing and com­pression. To operate the CCD, all CCD timing parameters are
programmed into the AD9920A from the system microprocessor
through the 3-wire serial interface. From the master clock, CLI,
provided by the image processor or external crystal, the AD9920A
generates the CCD horizontal and vertical clocks and the internal
AFE clocks. External synchronization is provided by a sync pulse
from the microprocessor, which resets the internal counters and
resyncs the VD and HD outputs.

1A TO V16, SUBCK

H1 TO H8, HL ,

RG, VSUB

CCD

GPO1 TO GPO8

CCDIN

Figure 15. Typical System Block Diagram, Master Mode

AD9920A

V-DRIVER

SYNC

AFETG

D0 TO D11

DCLK

HD, VD

SERIAL
INTERFACE

CLI

MICROPROCESSOR

DIGITAL

IMAGE

PROCESSING

ASIC

Alternatively, the AD9920A can be operated in slave mode. In
this mode, the VD and HD are provided externally from the
image processor, and all AD9920A timing is synchronized with
VD and HD.

The H-drivers for H1 to H8, HL, and RG are included in the
AD9920A, allowing these clocks to be directly connected to the
CCD. An H-driver voltage of up to 3.6 V is supported. V1A to
V16 and SUBCK vertical clocks are included as well, allowing
the AD9920A to provide all horizontal and vertical clocks
necessary to clock data out of a CCD.

MAXIMUM VD LENGTH I S 8192 LINES

06878-015

The AD9920A includes programmable general-purpose outputs
(GPOs) that can trigger mechanical shutter and strobe (flash)
circuitry.

Figure 16 and Figure 17 show the maximum horizontal and
vertical counter dimensions for the AD9920A. All internal
horizontal and vertical clocking is controlled by these counters,
which specify line and pixel locations. Maximum HD length is
16,384 pixels per line, and maximum VD length is 8192 lines
per field.

MAXIMUM COUNT E R DIMENSIONS

14-BIT HORIZONTAL = 16,384 PIXE LS MAXIMUM

13-BIT VERTICAL = 8192 LINES MAXIMUM

06878-016

Figure 16. Vertical and Horizontal Counters

H-COUNTER BEHAVIOR IN SLAVE MODE

In the AD9920A, the internal H-counter holds at its maximum
count of 16,383 instead of rolling over. This feature allows the
AD9920A to be used in applications that contain a line length
greater than 16,384 pixels. Although no programming values
for the vertical and horizontal signals are available beyond 8191,
the H, RG, and AFE clocking continues to operate, sampling the
remaining pixels on the line.

VD

HD

CLI

MAXIMUM HD LENGTH IS 16,384 PIXELS

Figure 17. Maximum VD/HD Dimensions

06878-017

Rev. B | Page 17 of 112

AD9920A

HIGH SPEED PRECISION TIMING CORE

The AD9920A generates high speed timing signals using the
flexible Precision Timing core. This core is the foundation for
generating the timing used for both the CCD and the AFE; it
includes the reset gate (RG), horizontal drivers (H1 to H8, HL),
and SHP/SHD sample clocks. A unique architecture makes it
routine for the system designer to optimize image quality by
providing precise control over the horizontal CCD readout
and the AFE correlated double sampling.

The high speed timing of the AD9920A operates the same
way in either master or slave mode configuration. For more
information on synchronization and pipeline delays, see
the Power-Up Sequence for Master Mode section.

Timing Resolution

The Precision Timing core uses a 1× master clock input as a
reference (CLI). This clock should be the same as the CCD pixel
clock frequency. Figure 18 illustrates how the internal timing core

POSITION

CLI

t

CLIDLY

1 PIXEL
PERIOD

NOTES

1. PIXEL CLOCK PERIOD IS DIVIDED INTO 64 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.

2. THERE IS A FIXED DELAY FROM THE CLI INPUTTO THE INTERNAL PIXEL PERIOD POSITIONS (

P[0] P[64] = P[0]P[16] P[32] P[48]

...

Figure 18. High Speed Clock Resolution from CLI, Master Clock Input

1

divides the master clock period into 64 steps or edge positions.
Using a 40.5 MHz CLI frequency, the edge resolution of the
Precision Timing core is approximately 0.4 ns. If a 1× system clock
is not available, it is possible to use a 2× reference clock by pro­gramming the CLIDIVIDE register (AFE Register Address 0x0D).
The AD9920A then internally divides the CLI frequency by 2.

High Speed Clock Programmability

Figure 19 shows when the high speed clocks RG, H1 to H8, HL,
SHP, and SHD are generated. The RG pulse has programmable
rising and falling edges and can be inverted using the polarity
control. Horizontal Clock H1 has programmable rising and falling
edges and polarity control. In HCLK Mode 1, H3, H5, and H7
are equal to H1. H2, H4, H6, and H8 are always inverses of H1.

The edge location registers are each six bits wide, allowing the
selection of all 64 edge locations. Figure 23 shows the default
timing locations for all of the high speed clock signals.

...

t

CONV

t

= 6 ns TYP).

CLIDLY

06878-018

CCD

SIGNAL

RG

H1, H3, H5, H7

H2, H4, H6, H8

34

56

78

HL

PROGRAMMABLE CLOCK POSI T IONS:

1

SHP SAMPLE LO CAT I O N.

2

SHD SAMPLE LOCATION.

3

RG RISING EDGE.

4

RG FALLING EDGE.

5

H1 RISING EDGE.

6

H1 FALLING EDGE.

7

HL RISING EDGE.

8

HL FALLING EDGE.

2

6878-019

Figure 19. High Speed Clock Programmable Locations (HCLKMODE = 0x01)

Rev. B | Page 18 of 112

AD9920A

H-Driver and RG Outputs

In addition to the programmable timing positions, the AD9920A
features on-chip output drivers for the RG, HL, and H1 to H8
outputs. These drivers are powerful enough to drive the CCD
inputs directly. The H-driver and RG current can be adjusted for
optimum rise/fall time for a particular load by using the drive
strength control registers (Address 0x36 and Address 0x37). The
3-bit drive setting for each H1 to H8 output is adjustable in

4.3 mA increments: 0 = off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 17.3 mA, 5 = 21.6 mA, 6 = 25.9 mA, and 7 = 30.2 mA.

The 3-bit drive settings for the HL and RG outputs are also
adjustable in 4.3 mA increments, but with a maximum drive
strength of 17.3 mA: 0 = off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 4.3 mA, 5 = 8.6 mA, 6 = 12.9 mA, and 7 = 17.3 mA.

As shown in Figure 19, when HCLK Mode 1 is used, the H2,
H4, H6, and H8 outputs are inverses of the H1, H3, H5, and H7
outputs. Using the HCLKMODE register (Address 0x24,
Bits[4:0]), it is possible to select a different configuration.

Table 9. Timing Core Register Parameters for H1, H2, HL, RG, SHP, and SHD

Parameter Length (Bits) Range Description

Positive Edge 6 0 to 63 edge location Positive edge location for H1, H2, HL, H3P1, and RG.
Negative Edge 6 0 to 63 edge location Negative edge location for H1, H2, HL, H3P1, and RG.
Sampling Location 6 0 to 63 edge location Sampling location for internal SHP and SHD signals.
Drive Strength 3 0 to 7 current steps Drive current for H1 to H8, HL, and RG outputs (4.3 mA per step).

Tabl e 10 shows a comparison of the different programmable
settings for each HCLK mode. Figure 20 and Figure 21 show the
settings for HCLK Mode 2 and HCLK Mode 3, respectively.

It is recommended that all H1 to H8 outputs on the AD9920A be
used together for maximum flexibility in drive strength settings.
A typical CCD with H1 and H2 inputs should have only the
AD9920A H1, H3, H5, and H7 outputs connected together to
drive the CCD H1 and should have only the AD9920A H2, H4,
H6, and H8 outputs connected together to drive the CCD H2.

In 3-phase HCLK mode, only six of the HCLK outputs are used,
with two outputs driving each of the three phases:

• H1 and H2 are connected to CCD Phase 1.

• H5 and H6 are connected to CCD Phase 2.

• H7 and H8 are connected to CCD Phase 3.

Table 10. HCLK Modes, Selected by Address 0x24, Bits[4:0]

HCLKMODE Register Value Description

Mode 1 0x01 H1 edges are programmable with H3 = H5 = H7 = H1, H2 = H4 = H6 = H8 = inverse of H1.
Mode 2 0x02

Mode 3 0x04

3-Phase Mode 0x10 H1 edges are programmable using Address 0x33 and H2 = H1 (Phase 1).
H5 edges are programmable using Address 0x31 and H6 = H5 (Phase 2).
H7 edges are programmable using Address 0x30 and H8 = H7 (Phase 3).
Invalid Selection All other values Invalid register settings. Do not use.

H1 edges are programmable with H3 = H5 = H7 = H1.
H2 edges are programmable with H4 = H6 = H8 = H2.

H1 edges are programmable with H3 = H1 and H2 = H4 = inverse of H1.
H5 edges are programmable with H7 = H5 and H6 = H8 = inverse of H5.

Rev. B | Page 19 of 112

AD9920A

12

H1, H3, H5, H7

43

H2, H4, H6, H8

H1 TO H8 PROGRAMMABLE LOCATIONS:

1

H1 RISING EDGE.

2

H1 FALLING EDGE.

3

H2 RISING EDGE.

4

H2 FALLING EDGE.

Figure 20. HCLK Mode 2 Operation

12

H1, H3

H2, H4

34

H5, H7

H6, H8

H1 TO H8 PROGRAMMABLE LOCATIONS:

1

H1 RISING EDGE.

2

H1 FALLING EDGE.

3

H5 RISING EDGE.

4

H5 FALLING EDGE.

06878-021

Figure 21. HCLK Mode 3 Operation

H1, H2

1

2

06878-020

H5, H6

56

H7, H8

H1 TO H8 PROGRAMMABLE LOCATIONS:

1

H1 FALLING EDGE.

2

H1 RISI NG EDGE .

3

H5 FALLING EDGE.

4

H5 RISI NG EDGE .

5

H7 RISI NG EDGE .

6

H7 FALLING EDGE.

3

4

06878-022

Figure 22. 3-Phase HCLK Mode Operation

Rev. B | Page 20 of 112

AD9920A

CLI

RG

H1

H2

CCD

SIGNAL

SHP

SHD

DOUTPHASEP

NOTES

1. ALL SIGNAL EDGE S ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN O NE PIXEL PE RIOD.
TYPICAL POSITIO NS FOR EACH S I G NAL ARE SHOWN. HCLK MODE 1 IS SHOWN.

2. CERTAIN PO SITIONS SHOULD BE AVOIDED FOR EACH SIGNAL, SHOWN ABOVE AS INHIBIT RE GIONS.

3. IF A SETTING IN THE INHIBIT REGION IS USED, AN UNSTABLE PIXEL SHIFT CAN OCCUR IN THE HBLK LO CATION OR AFE PIPELINE.

4. THE t

5. THE t

H1HBLK MASKING POLARITY.

6. THE t

P[0]

RGr[0] RGf[16]

H1r[0] H1f[32]

t

SHDINH

t

S2

SHDLOC[0]

1

t

DOUTINH

AREA FROM 50 TO 62 ONLY APPLIES IN SLAVE MODE.

SHPINH

AREA WILL APPLY TO EITHER H1 RISING OR FALLING EDGE, DEPENDING ON T HE VALUE OF THE

SHDINH

AREA CAN ALSO BE CHANGED TO A t

SHDINH

12

SHPINH

P[32]P[16] P[48]POSITION

t

S1

SHPLOC[32]

AREA IF THE H1HBLKRETI M E BIT = 1.

50

t

SHDINH

t

SHPINH

P[64] = P[0]

62

06878-023

Figure 23. High Speed Timing Default Locations

PHASE 1

P[0]

P[32]P[16] P[48]TAP POSITION

SHDINH/SHPINH

P[64] = P[0]

PHASE 2

PHASE 3

RGr[0] RGf[16]

RG

HLr[0] HLf[32]

HL

CCD

SIGNAL

SHP

SHDLOC[0]

SHD

NOTES

1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.
TYPICAL P OSITIONS FOR EACH SIGNAL ARE SHO WN USING 3-PHAS E HBLK MODE.

2. THE RISING EDGE O F EACH HCLK PHASE HAS AN ASSOCIATED SHDINH.

3. WHEN THE HBLK RETIME BITS (0x35 [3:0] ) ARE ENABLED, THE I NHIBITED AREA BECOMES SHPINH.

4. WHEN THE HBLK MASK LEVEL FOR PHASE 1, 2, OR 3 IS CHANGED TO L OW, THE INHIBIT AREA IS
REFERENCED TO THE HCLK FALLING EDGE, INSTEAD OF THE HCLK RISING EDGE.

Figure 24. High Speed Timing Typical Locations, 3-Phase HCLK Mode

SHDINH/SHPINH

SHPLOC[32]

SHDINH/SHPINH

t

S1

06878-024

Rev. B | Page 21 of 112

AD9920A

DIGITAL DATA OUTPUTS

The AD9920A data output and DCLK phase are programmable
using the DOUTPHASE registers (Address 0x39, Bits[13:0]).
DOUTPHASEP (Bits[5:0]) selects any edge location from 0 to
63, as shown in Figure 25. DOUTPHASEN (Bits[13:8]) does
not actually program the phase of the data outputs but is used
internally and should always be programmed to a value of
DOUTPHASEP plus 32 edges. For example, if DOUTPHASEP
is set to 0, DOUTPHASEN should be set to 32 (0x20).

P[0]

PIXEL

PERIOD

DCLK

t

OD

DOUT

NOTES

1. DATA OUTPUT (DOUT) AND DCL K P HAS E ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.

2. WITHIN ONE CLO CK PERIOD, T HE DAT A TRANSITI ON CAN BE PROGRAMMED TO 64 DIFFERENT LOCATIONS .

3. DCLK CAN BE INVERTED WITH RE S P E CT TO DOUT BY USING THE DCLKINV REGISTER.

Figure 25. Digital Output Phase Adjustment Using DOUTPHASEP Register

P[16]

Normally, the data output and DCLK signals track in phase,
based on the contents of the DOUTPHASE registers. The DCLK
output phase can also be held fixed with respect to the data out­puts by setting the DCLKMODE register high (Address 0x39,
Bit 16). In this mode, the DCLK output remains at a fixed phase
equal to a delayed version of CLI, and the data output phase
remains programmable.

The pipeline delay through the AD9920A is shown in Figure 26.
After the CCD input is sampled by SHD, there is a 16-cycle
delay until the data is available.

P[32]

P[48]

P[64] = P[0]

06878-025

CCDIN

SHD

(INTERNAL)

ADC DOUT

(INTERNAL)

DCLK

DOUT

CLI

t

CLIDLY

NN + 2N + 1

SAMPLE PIXEL N

t

DOUTINH

NOTES

1. TIMING VALUES SHOWN ARE SHDLOC = 0, WITH DCLKMO DE = 0.

2. HIGHER VALUES OF SHD AND/OR DOUTPHASE SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.

3. RECOMMENDED VALUE F O R DOUT P HASE I S TO USE SHPLOC OR UP TO 15 EDGES FOL LOWING SHPL O C.

N – 14 N – 4N – 5N – 6N – 7N – 8N – 9N – 10N – 11N – 12N – 13 N – 3 N – 2 N – 1 N N + 1N – 15N – 16N – 17

N + 3

N – 14 N – 4N – 5N – 6N – 7N – 8N – 9N – 10N – 11N – 12N – 13 N – 3 N – 2 N – 1 N N + 1N – 15N – 16N – 17

N + 4

PIPELINE LATENCY = 16 CYCLES

Figure 26. Digital Data Output Pipeline Delay

N + 13N + 12N + 11N + 10N + 9N + 8N + 7N + 6N + 5

N + 14

N + 16 N + 17N + 15

06878-026

Rev. B | Page 22 of 112

AD9920A

HORIZONTAL CLAMPING AND BLANKING

The horizontal clamping and blanking pulses of the AD9920A are
fully programmable to suit a variety of applications. Individual
control is provided for CLPOB, PBLK, and HBLK in the different
regions of each field. This allows the dark pixel clamping and
blanking patterns to be changed at each stage of the readout to
accommodate different image transfer timing and high speed
line shifts.

Individual CLPOB and PBLK Patterns

The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 27. These two signals are programmed inde­pendently using the registers shown in Tab le 1 1. The start polarity
for the CLPOB (or PBLK) signal is CLPOBPOL (PBLKPOL), and
the first and second toggle positions of the pulse are CLPOBTOG1
(PBLKTOG1) and CLPOBTOG2 (PBLKTOG2). Both signals
are active low and should be programmed accordingly.

A separate pattern for CLPOB and PBLK can be programmed
for each vertical sequence. As described in the Ver t ica l Tim i ng
Generation section, several V-sequences can be created, each
containing a unique pulse pattern for CLPOB and PBLK.

Figure 57 shows how the sequence change positions divide the
readout field into regions. By assigning a different V-sequence
to each region, the CLPOB and PBLK signals can change with
each change in the vertical timing.

CLPOB and PBLK Masking Areas

Additionally, the AD9920A allows the CLPOB and PBLK signals
to be disabled in certain lines in the field without changing any
of the existing CLPOB pattern settings.

To use CLPOB (or PBLK) masking, the CLPMASKSTART
(PBLKMASKSTART) and CLPMASKEND (PBLKMASKEND)
registers are programmed to specify the start and end lines in
the field where the CLPOB (PBLK) patterns are ignored. The
three sets of start and end registers allow up to three CLPOB
(PBLK) masking areas to be created.

The CLPOB and PBLK masking registers are not specific to a
certain V-sequence; they are always active for any existing field
of timing. During operation, to disable the CLPOB masking
feature, these registers must be set to the maximum value of
0x1FFF or a value greater than the programmed VD length.

Note that to disable CLPOB (or PBLK) masking during power-up,
it is recommended that CLPMASKSTART (PBLKMASKSTART)
be set to 8191 and that CLPMASKEND (PBLKMASKEND) be
set to 0. This prevents any accidental masking caused by register
update events.

Table 11. CLPOB and PBLK Pattern Registers

Length

Register

CLPOBPOL 1 High/low Starting polarity of CLPOB for each V-sequence.
PBLKPOL 1 High/low Starting polarity of PBLK for each V-sequence.
CLPOBTOG1 13 0 to 8191 pixel location First CLPOB toggle position within line for each V-sequence.
CLPOBTOG2 13 0 to 8191 pixel location Second CLPOB toggle position within line for each V-sequence.
PBLKTOG1 13 0 to 8191 pixel location First PBLK toggle position within line for each V-sequence.
PBLKTOG2 13 0 to 8191 pixel location Second PBLK toggle position within line for each V-sequence.
CLPMASKSTART 13 0 to 8191 line location CLPOB masking area—starting line within field (maximum of three areas).
CLPMASKEND 13 0 to 8191 line location CLPOB masking area—ending line within field (maximum of three areas).
PBLKMASKSTART 13 0 to 8191 line location PBLK masking area—starting line within field (maximum of three areas).
PBLKMASKEND 13 0 to 8191 line location PBLK masking area—ending line within field (maximum of three areas).

(Bits)

Range Description

Rev. B | Page 23 of 112

AD9920A

HD

CLPOB

1

PBLK

PROGRAMMABL E S E TTINGS :

1

START POL ARITY (CLAMP AND BLANK REGION ARE ACT IVE LOW).

2

FIRST TOGGLE POSITION.

3

SECOND TOGGLE POSITION.

32

ACTIVE

Figure 27. Clamp and Preblank Pulse Placement

VD

0 1 2 597 598

HD

CLPOB

CLPMASKSTART1 = 6 CLPMASKEND1 = 9

NO CLPOB SI G NAL

FOR LINES 6 TO 8

Figure 28. CLPOB Masking Example

Individual HBLK Patterns

The HBLK programmable timing shown in Figure 29 is similar to
the timing of CLPOB and PBLK; however, there is no start polarity
control. Only the toggle positions are used to designate the start
and stop positions of the blanking period. Additionally, separate
masking polarity controls for each H-clock phase designate the
polarity of the horizontal clock signals during the blanking period.
Setting HBLKMASK_H1 high sets H1—and, therefore, H3, H5,
and H7—low during the blanking, as shown in Figure 30. As with
the CLPOB and PBLK signals, HBLK registers are available in
each V-sequence, allowing different blanking signals to be used
with different vertical timing sequences.

The AD9920A supports two modes of HBLK operation. HBLK
Mode 0 supports basic operation and pixel mixing HBLK oper­ation. HBLK Mode 1 supports advanced HBLK operation.

The following sections describe each mode in detail. Register
parameters are described in detail in Ta b le 1 2 .

ACTIVE

06878-027

NO CLPOB SI GNAL

FOR LINE 600

CLPMASKSTART2 = 600 CLPMASKEND2 = 601

06878-028

HBLK Mode 0 Operation

There are six toggle positions available for HBLK. Normally, only
two of the toggle positions are used to generate the standard
HBLK interval. However, the additional toggle positions can be
used to generate special HBLK patterns, as shown in Figure 31.
The pattern in this example uses all six toggle positions to gen­erate two extra groups of pulses during the HBLK interval. By
changing the toggle positions, different patterns can be created.

Separate toggle positions are available for even and odd lines. If
alternation is not needed, the same values should be loaded into
the registers for even (HBLKTOGE) and odd (HBLKTOGO) lines.

Multiple repeats of the HBLK signal are enabled by setting the
HBLKLEN and HBLKREP registers along with the six toggle
positions (four are shown in Figure 32).

Generating HBLK Line Alternation

HBLK Mode 0 provides the ability to alternate different HBLK
toggle positions on even and odd lines. HBLK line alternation
can be used alone or in conjunction with V-pattern odd/even
alternation (see the Generating Line Alternation for V-Sequences
and HBLK section). Separate toggle positions are available for
even and odd lines. If even/odd line alternation is not needed,
the same values should be loaded into the registers for even
(HBLKTOGE) and odd (HBLKTOGO) lines.

Rev. B | Page 24 of 112

AD9920A

G

HD

HBLKSTART HBLKEND

HBLK

BLANK BLANK

BASIC HBLK PULSE IS GENERATED US ING HBLKSTART AND HBLKEND REGISTERS

06878-118

Figure 29. Typical Horizontal Blanking Pulse Placement (HBLK_MODE = 0)

HD

HBLK

H1/H3/H5/H7

THE POLARITY OF H1/H3/H5/H7 DURING BLANKING IS P ROGRAMMABLE
(H2/H4/H6/H8 AND HL ARE SEPARATELY PROGRAMMABL E)

H1/H3/H5/H7

H2/H4/H6/H8

6878-029

Figure 30. HBLK Masking Polarity Control

HBLKSTART

HBLKTOGE2

HBLKTOGE1 HBLKTOGE3

HBLKTO

HBLKTOGE4

E5

HBLKTOGE6

HBLKEND

HBLK

H1/H3

H2/H4

SPECIAL H-BL ANK P AT TERN IS CREATE D US ING MULTI PLE HBLK TO GGLE PO S ITIONS

06878-030

Figure 31. Using Multiple Toggle Positions for HBLK (HBLK_MODE = 0)

HBLKSTART HBLKTOGE1

HBLK

H1/H3

H2/H4

HBLKTOGE2

HBLKLEN

HBLKREP = 3

HBLKREP NUMBER 1 HBLKREP NUMBER 2 HBLKREP NUMBER 3

H-BLANK REPEATING PATTERN IS CREATED USING HBLKLE N AND HBLKREP REGISTERS

HBLKTOGE4

Figure 32. HBLK Repeating Pattern Using HBLK_MODE = 0

HBLKENDHBLKTOGE3

06878-031

Rev. B | Page 25 of 112

AD9920A

Table 12. HBLK Pattern Registers

Length

Register

HBLK_MODE 2 0 to 1 HBLK modes Enables different HBLK toggle position operations.

2 = test mode only; do not access.
3 = test mode only; do not access.
HBLKSTART 13 0 to 8191 pixel location Start location for HBLK in HBLK Mode 0 and HBLK Mode 1.
HBLKEND 13 0 to 8191 pixel location End location for HBLK in HBLK Mode 0 and HBLK Mode 1.
HBLKLEN 13 0 to 8191 pixels HBLK length in HBLK Mode 0 and HBLK Mode 1.
HBLKREP 13 0 to 8191 repetitions Number of HBLK repetitions in HBLK Mode 0 and HBLK Mode 1.
HBLKMASK_H1 1 High/low Masking polarity for H1/H3/H5/H7 during HBLK.
HBLKMASK_H2 1 High/low Masking polarity for H2/H4/H6/H8 during HBLK.
HBLKMASK_HL 1 High/low Masking polarity for HL during HBLK.
HBLKMASK_H3P 1 High/low Masking polarity for H3P during 3-phase mode during HBLK.
HBLKTOGO1 13 0 to 8191 pixel location First HBLK toggle position for odd lines in HBLK Mode 0.
HBLKTOGO2 13 0 to 8191 pixel location Second HBLK toggle position for odd lines in HBLK Mode 0.
HBLKTOGO3 13 0 to 8191 pixel location Third HBLK toggle position for odd lines in HBLK Mode 0.
HBLKTOGO4 13 0 to 8191 pixel location Fourth HBLK toggle position for odd lines in HBLK Mode 0.
HBLKTOGO5 13 0 to 8191 pixel location Fifth HBLK toggle position for odd lines in HBLK Mode 0.
HBLKTOGO6 13 0 to 8191 pixel location Sixth HBLK toggle position for odd lines in HBLK Mode 0.
HBLKTOGE1 13 0 to 8191 pixel location First HBLK toggle position for even lines in HBLK Mode 0.
HBLKTOGE2 13 0 to 8191 pixel location Second HBLK toggle position for even lines in HBLK Mode 0.
HBLKTOGE3 13 0 to 8191 pixel location Third HBLK toggle position for even lines in HBLK Mode 0.
HBLKTOGE4 13 0 to 8191 pixel location Fourth HBLK toggle position for even lines in HBLK Mode 0.
HBLKTOGE5 13 0 to 8191 pixel location Fifth HBLK toggle position for even lines in HBLK Mode 0.
HBLKTOGE6 13 0 to 8191 pixel location Sixth HBLK toggle position for even lines in HBLK Mode 0.
RA0H1REPA/B/C 12

RA1H1REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 1. Number of H1 repetitions for HBLKSTARTA/B/C.
RA2H1REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 2. Number of H1 repetitions for HBLKSTARTA/B/C.
RA3H1REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 3. Number of H1 repetitions for HBLKSTARTA/B/C.
RA4H1REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 4. Number of H1 repetitions for HBLKSTARTA/B/C.
RA5H1REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 5. Number of H1 repetitions for HBLKSTARTA/B/C.
RA0H2REPA/B/C 12

RA1H2REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 1. Number of H2 repetitions for HBLKSTARTA/B/C.
RA2H2REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 2. Number of H2 repetitions for HBLKSTARTA/B/C.
RA3H2REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 3. Number of H2 repetitions for HBLKSTARTA/B/C.
RA4H2REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 4. Number of H2 repetitions for HBLKSTARTA/B/C.
RA5H2REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 5. Number of H2 repetitions for HBLKSTARTA/B/C.

(Bits) Range Description

0 = normal mode; six toggle positions available for even and odd lines.
If even/odd alternation is not needed, set toggles for even and odd lines to the
same value. In addition to the six toggle positions, the HBLKSTART, HBLKEND,
HBLKLEN, and HBLKREP registers can be used to generate HBLK patterns. If even/
odd alternation is not needed, set toggles for even and odd lines to the same value.

1 = advanced HBLK mode; divides HBLK interval into six repeat areas.
Uses HBLKSTARTA/B/C and RAxHxREPA/B/C registers; the latter, depending on the
mode of operation, are stored in the HBLKTOGO1 to HBLKTOGO6 and HBLKTOGE1
to HBLKTOGE6 registers (Address 0x19 to Address 0x1E; see Table 63).

0 to 15 HCLK pulses for
each A, B, and C

0 to 15 HCLK pulses for
each A, B, and C

HBLK Repeat Area 0. Number of H1 repetitions for HBLKSTARTA/B/C in
HBLK Mode 1 for even lines; odd lines defined using HBLKALT_PAT.

Bits[3:0]: RA0H1REPA. Number of H1 pulses following HBLKSTARTA.
Bits[7:4]: RA0H1REPB. Number of H1 pulses following HBLKSTARTB.
Bits[11:8]: RA0H1REPC. Number of H1 pulses following HBLKSTARTC.

HBLK Repeat Area 0. Number of H2 repetitions for HBLKSTARTA/B/C in
HBLK Mode 1 for even lines; odd lines defined using HBLKALT_PAT.

Bits[3:0]: RA0H2REPA. Number of H2 pulses following HBLKSTARTA.
Bits[7:4]: RA0H2REPB. Number of H2 pulses following HBLKSTARTB.
Bits[11:8]: RA0H2REPC. Number of H2 pulses following HBLKSTARTC.

Rev. B | Page 26 of 112

AD9920A

Length

Register

HBLKSTARTA 13 0 to 8191 pixel location HBLK Repeat Area Start Position A for HBLK Mode 1. Set to 8191 if not used.
HBLKSTARTB 13 0 to 8191 pixel location HBLK Repeat Area Start Position B for HBLK Mode 1. Set to 8191 if not used.
HBLKSTARTC 13 0 to 8191 pixel location HBLK Repeat Area Start Position C for HBLK Mode 1. Set to 8191 if not used.
HBLKALT_PAT0 3 0 to 5 even repeat area

HBLKALT_PAT1 3 0 to 5 even repeat area HBLK Mode 1, Repeat Area 1 pattern for odd lines.
HBLKALT_PAT2 3 0 to 5 even repeat area HBLK Mode 1, Repeat Area 2 pattern for odd lines.
HBLKALT_PAT3 3 0 to 5 even repeat area HBLK Mode 1, Repeat Area 3 pattern for odd lines.
HBLKALT_PAT4 3 0 to 5 even repeat area HBLK Mode 1, Repeat Area 4 pattern for odd lines.
HBLKALT_PAT5 3 0 to 5 even repeat area HBLK Mode 1, Repeat Area 5 pattern for odd lines.

(Bits) Range Description

HBLK Mode 1, Repeat Area 0 pattern for odd lines. Selected from previously
defined even line repeat areas.

PHASE 1

PHASE 2

PHASE 3

INTERNAL

DIGITAL

CLOCK

MASTER

BLANKING

SIGNAL

H1/H2

H5/H6

H7/H8

1 PIXEL

A3

A

1 PIXEL 1 PIXEL 1 PIXEL

A1

A2

MASK LEVEL = HIGH

MASK LEVEL = LOW

MASK LEVEL = HIGH

Figure 33. Example of Correct HBLK Behavior

HBLK Fine Retime Control

An additional set of register bits is available for use during
3-phase HCLK mode to provide fine adjustment of each HCLK
phase during the HBLK interval. The fine retime bits (Address 0x35,
Bits[23:20]) allow for the adjustment of the correct number of
HCLK cycles during the HBLK interval.

Figure 33 through Figure 35 show the different settings that can
be used based on the location of the HBLK toggle positions, the
location of the internal digital clock, and the masking polarity
of the different HCLK phases. By using the fine retime bits, the
exact pulse behavior for each HCLK phase can be generated.

Rev. B | Page 27 of 112

BLANKING

B1

B2

B3

B

06878-032

Figure 33 shows the desired HBLK behavior for all three phases
when the internal digital clock is located before the Phase 3 rising
edge. Figure 34 shows the effect of changing the internal clock
phase (changing SHDLOC) to a different location. This causes
incorrect blanking on Phase 1 and Phase 2.

Figure 35 shows how the fine retime bits for Phase 1 and Phase 2
are used to generate the correct blanking behavior, matching the
result shown in Figure 33.

AD9920A

1 PIXEL 1 PIXEL1 PIXEL1 PIXEL1 P IXEL

PHASE 1

PHASE 2

PHASE 3

INTERNAL

DIGITAL

CLOCK

MASTER

BLANKING

SIGNAL

H1/H2

H5/H6

H7/H8

A1

A2

A3

A

MASK LEVEL = HIGH

MASK LEVEL = LOW

MASK LEVEL = HIGH

BLANKING

B1

B2

B3

B

06878-033

Figure 34. Incorrect HBLK Behavior Caused by Internal Clock Position

1 PIXEL 1 PIXEL1 PIXEL1 PIXEL1 PIXEL

FINE RET I ME

PHASE 1

PHASE 2

A2

PHASE 3

INTERNAL

DIGITAL

CLOCK

MASTER

BLANKING

SIGNAL

H1/H2

H5/H6

H7/H8

A

A1

FINE RET I ME

FINE RETIME

A3

MASK LEVEL = HIGH

MASK LEVEL = LOW
MASK LEVEL = HIGH

BLANKING

Figure 35. Fine Retime on Phase 2 to Achieve Correct HBLK

B1

FINE RET IME

B2

B3

B

6878-034

Rev. B | Page 28 of 112

AD9920A

Increasing H-Clock Width During HBLK

The AD9920A allows the H1 to H8 pulse width to be increased
during the HBLK interval. As shown in Figure 36, the H-clock fre­quency can be reduced by a factor of 1/2, 1/4, 1/6, 1/8, 1/10, 1/12,
and so on, up to 1/30. To enable this feature, the HCLK_WIDTH
register (Address 0x35, Bits[7:4]) is set to a value between 1 and 15.
When this register is set to 0, the wide HCLK feature is disabled.
The reduced frequency occurs for only the H1 to H8 pulses that
are located within the HBLK area.

The HCLK_WIDTH register is generally used in conjunction
with special HBLK patterns to generate vertical and horizontal
mixing in the CCD.

Table 13. HCLK Width Register

Register Length (Bits) Description

HCLK_WIDTH 4 Controls the H1 to H8 pulse widths during HBLK as a fraction of pixel rate
0 = same frequency as pixel rate; 1 = 1/2 pixel frequency (doubles the HCLK pulse width);
2 = 1/4 pixel frequency; 3 = 1/6 pixel frequency; 4 = 1/8 pixel frequency;
5 = 1/10 pixel frequency; 15 = 1/30 pixel frequency

HBLK Mode 1 Operation

HBLK Mode 1 allows more advanced HBLK pattern operation.
If multiple areas of HCLK pulses that are unevenly spaced from
one another are needed, HBLK Mode 1 can be used. Using a
separate set of registers, HBLK Mode 1 can divide the HBLK
region into up to six repeat areas (see Ta b le 1 2).

As shown in Figure 37, each repeat area shares a common
group of toggle positions: HBLKSTARTA, HBLKSTARTB, and
HBLKSTARTC. However, the number of toggles following a start
position can be unique in each repeat area by using the RAxH1REP
and RAxH2REP registers; these registers, depending on the mode
of operation, are stored in the HBLKTOGO1 to HBLKTOGO6
and HBLKTOGE1 to HBLKTOGE6 registers (Address 0x19 to
Address 0x1E; see Tab le 6 3 ).

HBLK

H1/H3

H2/H4

1/f

PIX

H-CLOCK FREQUENCY CAN BE REDUCED DURING HBLK BY 1/2 (AS SHO WN),
1/4, 1/6, 1/8, 1/10, 1/12, AND SO ON, UP TO 1/30 USIN G HBLK_WI DTH REGISTER.

2 × (1/f

)

PIX

06878-035

Figure 36. Generating Wide H-Clock Pulses During HBLK Interval

HD

H1

H2

CREATE UP TO THREE GROUPS OF TOG GLES
(A, B, C) COMMON IN ALL REP EAT AREAS

A

B

C

HBLKSTART

REPEAT AREA 0

REPEAT AREA 1 REPEAT AREA 2

MASK A, B, C PULS E S IN ANY REPEAT

AREA BY SETTI N G RAxHxREPx = 0

REPEAT AREA 3

Figure 37. HBLK Mode 1 Registers

CHANGE NUMBER OF A, B, C PULSES IN ANY

REPEAT AREA USING RAxHxREPx REGISTERS

REPEAT AREA 4 REPEAT AREA 5

HBLKEND

06878-036

Rev. B | Page 29 of 112

AD9920A

K

HD

HBLKLEN

HBL

HBLKSTARTA

HBLKSTARTB

HBLKSTARTC

H1

RA0H1REPA

H2

HBLKSTART

RA0H2REPA

RA0H1REPB RA0H1REPC

RA0H2REPB RA0H2REPC

REPEAT AREA 0

TO CREATE TWO REPEAT ARE AS

ALL RAxHxREPA/B/C REGISTERS = 2 TO CREATE TWO HCLK PULSE S

HBLKREP = 2

Figure 38. HBLK Mode 1 Operation

As shown in Figure 38, setting the RAxH1REPA/B/C or
RAxH2REPA/B/C register to 0 masks HCLK groups from
appearing in a particular repeat area. Figure 37 shows only two
repeat areas being used, although six are available. It is possible
to program a separate number of repeat area repetitions for H1
and H2, but generally the same value is used for both H1 and
H2. Figure 37 shows an example of RA0H1REPA/B/C =
RA0H2REPA/B/C = RA1H1REPA/B/C = RA1H2REPA/B/C = 2.

Furthermore, HBLK Mode 1 allows a different HBLK pattern on
even and odd lines. The HBLKSTARTA/B/C registers, as well as
the RAxH1REPA/B/C and RAxH2REPA/B/C registers, define
operation for the even lines. For separate control of the odd lines,
the HBLKALT_PAT registers specify up to six repeat areas on
the odd lines by reordering the repeat areas used for the even
lines. New patterns are not available, but the order of the pre­viously defined repeat areas on the even lines can be changed
for the odd lines to accommodate advanced CCD operation.

HORIZONTAL TIMING SEQUENCE EXAMPLE

Figure 39 shows an example CCD layout. The horizontal register
contains 28 dummy pixels that occur on each line clocked from
the CCD. In the vertical direction, there are 10 optical black
(OB) lines at the front of the readout and two at the back of the
readout. The horizontal direction has four OB pixels in the
front and 48 OB pixels in the back.

RA1H1REPA

RA1H2REPA

RA1H1REPB RA1H1REPC

RA1H2REPB RA1H2REPC

REPEATAREA 1

HBLKEND

Figure 40 shows the basic sequence to be used during the
effective pixel readout. The 48 OB pixels at the end of each line
are used for the CLPOB signals. PBLK is optional and is often
used to blank the digital outputs during the HBLK time. HBLK
is used during the vertical shift interval.

Because PBLK is used to isolate the CDS input (see the Analog
Preblanking section), the PBLK signal should not be used
during CLPOB operation. The change in the offset behavior
that occurs during PBLK affects the accuracy of the CLPOB
circuitry.

The HBLK, CLPOB, and PBLK parameters are programmed
in the V-sequence registers. More elaborate clamping schemes,
such as adding a separate sequence to clamp in the entire shield
OB lines, can be used. This requires configuring a separate
V-sequence for clocking out the OB lines.

The CLPMASK registers are also useful for disabling the CLPOB
on a few lines without affecting the setup of the clamping
sequences. It is important that CLPOB be used only during
valid OB pixels. During other portions on the frame timing,
such as vertical blanking or SG line timing, the CCD does not
output valid OB pixels. Any CLPOB pulse that occurs during
this time causes errors in clamping operation and changes in
the black level of the image.

06878-037

Rev. B | Page 30 of 112