ANALOG DEVICES AD9913 Service Manual

Low Power 250 MSPS 10-Bit DAC 1.8 V

FEATURES

50 mW at up to 250 MSPS internal clock speed 100 MHz analog output Integrated 10-bit DAC

0.058 Hz or better frequency resolution

0.022° phase tuning resolution Programmable modulus in frequency equation Phase noise ≤ –135 dBc per Hz @ 1 kHz offset (DAC output)

(<115 dBc per Hz when using on-board PLL multiplier)

Excellent dynamic performance

>80 dB SFDR @ 100 MHz (±100 kHz offset) A Automatic linear frequency sweeping capability 8 frequency or phase offset profiles

1.8 V power supply Software and hardware controlled power-down Parallel and serial programming options 32-lead LFCSP package Optional PLL REF_CLK multiplier Internal oscillator (can be driven by a single crystal) Phase modulation capability

APPLICATIONS

Portable and handheld equipment Agile LO frequency synthesis Programmable clock generator FM chirp source for radar and scanning systems

OUT

CMOS Direct Digital Synthesizer

AD9913

GENERAL DESCRIPTION

The AD9913 is a complete direct digital synthesizer (DDS) designed to meet the stringent power consumption limits of portable, handheld, and battery-powered equipment. The AD9913 features a 10-bit digital-to-analog converter (DAC) operating up to 250 MSPS. The AD9913 uses advanced DDS technology, coupled with an internal high speed, high performance DAC to form a complete, digitally-programmable, high frequency synthesizer capable of generating a frequency agile analog output sinusoidal waveform at up to 100 MHz.

The AD9913 provides fast frequency hopping and fine tuning resolution. The AD9913 also offers fine resolution phase offset control. Control words are loaded into the AD9913 through the serial or parallel I/O port. The AD9913 also supports a userdefined linear sweep mode of operation for generating highly linearized swept waveforms of frequency. To support various methods of generating a system clock, the AD9913 includes an oscillator, allowing a simple crystal to be used as the frequency reference, as well as a high speed clock multiplier to convert the reference clock frequency up to the full system clock rate. For power saving considerations, many of the individual blocks of the AD9913 can be powered down when not in use.

The AD9913 operates over the extended industrial temperature range of −40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

AD9913

REF_CLK INPUT

CIRCUITRY

USER INTERFACE

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

DDS

TIMINGAND

CONTROL LO GIC

Figure 1.

10-BIT

DAC

07002-001

AD9913

REVISION HISTORY

6/10—Rev. 0 to Rev. A

Added Digital Input Voltage to Table 2 ......................................... 5

Added Exposed Pad Notation to Figure 3 and Table 3 ................ 5

Changes to Programmable Modulus Mode Section .................. 14

Changes to Serial Programming Section ..................................... 22

Changes to Data Write Operation Section .................................. 24

Added Register Update (I/O Update) section and Figure 35 ... 25

Added Endnote 1 to Table 9 .......................................................... 26

Changes to Register Bit Descriptions Section and Bit 7

Description in Table 10 .................................................................. 28

Changes to Table 15 and Table 16 ................................................ 31

Added Exposed Pad Notation to Outline Dimensions ............. 32

10/07—Revision 0: Initial Version

Rev. A | Page 2 of 32

AD9913

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

AVDD (1.8 V), DVDD (1.8 V), and DVDD_I/O = 1.8 V ± 5%, T = 25°C, R reference clock frequency = 250 MHz with REF_CLK multiplier disabled, unless otherwise noted.

Table 1.

Parameter Conditions/Comments Min Typ Max Unit

REF_CLK INPUT CHARACTERISTICS

Frequency Range

REF_CLK Multiplier Disabled 250 MHz Enabled 250 MHz REF_CLK Input Divider Frequency Full temperature range 83 MHz VCO Oscillation Frequency VCO1 16 250 MHz VCO2 100 250 MHz

PLL Lock Time 25 MHz reference clock, 10× PLL 60 µs External Crystal Mode 25 MHz CMOS Mode VIH 0.9 V

VIL 0.65 V Input Capacitance 3 pF Input Impedance (Differential) 2.7 kΩ Input Impedance (Single-Ended) 1.35 kΩ Duty Cycle 45 55 % REF_CLK Input Level 355 1000 mV p-p

DAC OUTPUT CHARACTERISTICS

Full-Scale Output Current 4.6 mA Gain Error −14 −6 %FS Output Offset +0.1 µA Differential Nonlinearity −0.4 +0.4 LSB Integral Nonlinearity −0.5 +0.5 LSB AC Voltage Compliance Range

SPURIOUS-FREE DYNAMIC RANGE Refer to Figure 6 SERIAL PORT TIMING CHARACTERISTICS

SCLK Frequency 32 MHz SCLK Pulse Width Low 17.5 ns High 3.5 ns SCLK Rise/Fall Time 2 ns Data Setup Time to SCLK 5.5 ns Data Hold Time to SCLK 0 ns Data Valid Time in Read Mode 22 ns

PARALLEL PORT TIMING CHARACTERISTICS

PCLK Frequency 33 MHz PCLK Pulse Width Low 10 ns High 20 ns PCLK Rise/Fall Time 2 ns Address/Data Setup Time to PCLK 3.0 ns Address/Data Hold Time to PCLK 0.3 ns Data Valid Time in Read Mode 8 ns

IO_UPDATE/PROFILE(2:0) TIMING

Setup Time to SYNC_CLK 0.5 ns Hold Time to SYNC_CLK 1 SYNC_CLK cycles

= 4.64 kΩ, DAC full-scale current = 2 mA, external

SET

mV

±400

Rev. A | Page 3 of 32

AD9913

Parameter Conditions/Comments Min Typ Max Unit

MISCELLANEOUS TIMING CHARACTERISTICS

Wake-Up Time1

Fast Recovery Mode 1 SYSCLK cycles2

Full Sleep Mode 60 s

Reset Pulse Width High 5 SYSCLK cycles

DATA LATENCY (PIPELINE DELAY)

Frequency, Phase-to-DAC Output Matched latency enabled 11 SYSCLK cycles Frequency-to-DAC Output Matched latency disabled 11 SYSCLK cycles Phase-to-DAC Output Matched latency disabled 10 SYSCLK cycles Delta Tuning Word-to-DAC Output (Linear Sweep) 14 SYSCLK cycles

CMOS LOGIC INPUTS

Logic 1 Voltage 1.2 V Logic 0 Voltage 0.4 V Logic 1 Current −700 +700 nA Logic 0 Current −700 +700 nA Input Capacitance 3 pF

CMOS LOGIC OUTPUTS 1 mA load

Logic 1 Voltage 1.5 V Logic 0 Voltage 0.125 V

POWER SUPPLY CURRENT

DVDD (1.8 V) Pin Current Consumption 46.5 mA DAC_CLK_AVDD (1.8 V) 4.7 mA DAC_AVDD (1.8 V) Pin Current Consumption 6.2 mA PLL_AVDD (1.8 V) 1.8 mA CLK_AVDD (1.8 V) Pin Current Consumption 4.3 mA

POWER CONSUMPTION

Single Tone Mode PLL enabled, CMOS input 50 66.5 mW PLL disabled, differential input 57 70.5 mW PLL enabled, XTAL input 52 68.5 mW Modulus Mode PLL disabled 94.6 mW Linear Sweep Mode PLL disabled 98.4 mW Power-Down

Full 15 mW Safe PLL enabled 44.8 mW

PLL Modes

VCO 1

Differential Input Mode 11 mW CMOS Input Mode 7.5 mW Crystal Mode 5.4 mW

VCO 2

Differential Input Mode 15 mW CMOS Input Mode 11.5 mW Crystal Mode 9.4 mW

1

Refer to the Power-Down Features section.

2

SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,

the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier and divider are not used, the SYSCLK frequency is the same as the external reference clock frequency.

Rev. A | Page 4 of 32

AD9913

A

C

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Maximum Junction Temperature 150°C AVDD, DVDD 2 V Digital Input Voltage −0.7 V to +2.2 V Digital Output Current 5 mA Storage Temperature –65°C to +150°C Operating Temperature –40°C to +105°C Lead Temperature (Soldering, 10 sec) 300°C θJA 36.1°C/W θJC 4.2°C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

EQUIVALENT CIRCUITS

DIGITAL INPUTS

INPUT

VOID OVERDRIVING DIGITAL INPUTS.

FORWARD BIASING ESD DIO DES M AY

OUPLE DIGIT AL NOISE ONTO P O WER

PINS.

DVDD_I/O

Figure 2. Equivalent Input and Output Circuits

DAC OUTPUTS

AVDD

IOUT IOUT

MUST TERMI NATE OUTPUT S TO AGND FOR CURRENT FLOW. DO NOT EXCEED THE OUTPUT V OLTAGE COMPLIANCE RATING.

07002-002

Rev. A | Page 5 of 32

AD9913

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

D)

RESET

N_CTL

R/R

ADR6/D6

ADR7/D7

SCLK(PCLK)

SDIO(W

CS

IO_UPDATE

PWR_DW

MASTER_

29

28

27

26

31

30

32

25

1PS2/ADR5/D5

PIN 1

2PS1/ADR4/D4

INDICATOR

3PS0/ADR3/D3 4DVDD

AD9913

5DGND

TOP VIEW

6ADR2/D2

(Not to S cale) 7ADR1/D1 8ADR0/D0

9

11

10

12

13

R

CLK

_

AVDD

AGND

SER/PA

REF

SYNC

NOTES

1. EXPOSE D PAD SHOULD BE SO LDERED TO G ROUND.

24 RSET 23 AGND 22 AVDD 21 AGND 20 IOUT 19 IOUT 18 AGND 17 AVDD

14

15

16

CLK

GND

_

AVDD

A

REF

07002-003

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic I/O Description

1 PS2/ADR5/D5 I/O

Multipurpose pin: Profile Select Pin (PS2) in Direct Switch Mode, Parallel Port Address Line (ADR5), and Data Line (D5) to program registers.

2 PS1/ADR4/D4 I/O

Multipurpose pin: Profile Select Pin (PS1) in Direct Switch Mode or Linear Sweeping Mode, Parallel Port Address Line (ADR4), and Data Line (D4) to program registers.

3 PS0/ADR3/D3 I/O

Multipurpose pin: Profile Select Pin (PS0) in Direct Switch Mode or Linear Sweeping Mode, Parallel Port

Address Line (ADR3), and Data Line (D3) to program registers. 4 DVDD I Digital Power Supply (1.8 V). 5 DGND I Digital Ground. 6 ADR2/D2 I/O Parallel Port Address Line 2 and Data Line 2. 7 ADR1/D1 I/O Parallel Port Address Line 1and Data Line 1. 8 ADR0/D0 I/O Parallel Port Address Line 0 and Data Line 0. 9 SYNC_CLK O

Clock Out. The profile pins [PS0:PS2] and the IO_UPDATE pin (Pin 27) should be set up to the rising

edge of this signal to maintain constant pipe line delay through the device. 10

11, 15,

/PAR

SER AGND I Analog Ground.

I Serial Port and Parallel Port Selection. Logic low = serial mode; logic high = parallel mode.

18, 21, 23

12, 16,

AVDD I Analog Power Supply (1.8 V).

17, 22 13 REF_CLK I Reference Clock Input. See the REF_CLK Overview section for more details. 14

19

REF_CLK IOUT

I Complementary Reference Clock Input. See the REF_CLK Overview section for more details.

O Open Source DAC Complementary Output Source. Current mode. Connect through 50 Ω to AGND. 20 IOUT O Open Source DAC Output Source. Current mode. Connect through 50 Ω to AGND. 24 RSET I

Analog Reference. This pin programs the DAC output full-scale reference current. Attach a 4.64 kΩ resistor to AGND.

25 MASTER_RESET I

Master Reset, Digital Input (Active High). This pin clears all memory elements and reprograms registers to default values.

Rev. A | Page 6 of 32

AD9913

Pin No. Mnemonic I/O Description

26 PWR_DWN_CTL I

27 IO_UPDATE I

28

29 30 SCLK/PCLK I Input Clock for Serial and Parallel Port.

31 ADR7/D7 I/O Parallel Port Address Line 7 and Data Line 7. 32 ADR6/D6 I/O Parallel Port Address Line 6 and Data Line 6. 33 Exposed Paddle The EPAD should be soldered to ground.

CS

SDIO(WR

/RD)

External Power-Down, Digital Input (Active High). A high level on this pin initiates the currently programmed power-down mode. See the Power-Down Features section for further details. If unused, tie to ground.

I/O Update; Digital Input. A high on this pin indicates a transfer of the contents of the I/O buffers to the corresponding internal registers.

I

Chip Select for Serial and Parallel Port. Digital input (active low). Bringing this pin low enables the AD9913 to detect serial (SCLK) or parallel (PCLK) clock rising/falling edges. Bringing this pin high causes the AD9913 to ignore input on the data pins.

I/O Bidirectional Data Line for Serial Port Operation and Write/Read Enable for Parallel Port Operation.

Rev. A | Page 7 of 32

AD9913

–

TYPICAL PERFORMANCE CHARACTERISTICS

0

−10

−20

−30

−40

−50

−60

POWER (d Bm)

−70

−80

−90

−100

0 20406080100120

FREQUENCY (MHz)

Figure 4. Wideband SFDR @ 99.76 MHz f

OUT

(250 MHz Clock, 4 mA DAC Full-Scale Current, PLL Bypassed)

0

−10

−20

−30

−40

−50

−60

POWER (d Bc)

−70

−80

−90

−100

0 20406080100120

FREQUENCY (MHz)

Figure 5. Wideband SFDR @ 25.14 MHz f

OUT

(250 MHz Clock, 4 mA DAC Full-Scale Current, PLL Bypassed)

50

07002-004

07002-005

0

−20

−40

−60

SFDR (dBm)

−80

−100

−120

99.758381 99.783381

99.763381 99.768381 99.773381 99.778381 FREQUENCY (MHz )

Figure 7. Narrow-Band SFDR @ 99.76 MHz f

OUT

(250 MHz Clock, 4 mA DAC Full-Scale Current, PLL Bypassed)

0

−20

−40

−60

SFDR (dBm)

−80

−100

−120

25.124918 25.17491825.134918 25.144918 25.154918 25.164918

25.129918 25.139918 25.149918 25.159918 25.169918

Figure 8. Narrow-Band SFDR @ 25.14 MHz f

FREQUENCY (MHz )

OUT

(250 MHz Clock, 4 mA DAC Full-Scale Current, PLL Bypassed)

50

07002-007

07002-008

–55

–60

–65

–70

SFDR (dBc)

–75

–80

–85

–90

00

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40

f

(% of System Cl o ck)

OUT

1.9V

1.7V

1.8V

07002-031

.45

Figure 6. SFDR vs. Supply Variation

(250 MHz Clock, 4 mA DAC Full-Scale Current, PLL Bypassed)

–55

–60

–65

–70

SFDR (dBc)

–75

–80

–85

–90

00

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40

f

OUT

+85ºC

+25°C

(% of System Clock)

–40°C

07002-032

.45

Figure 9. SFDR vs. Temperature

(250 MHz Clock, 4 mA DAC Full-Scale Current, PLL Bypassed)

Rev. A | Page 8 of 32

AD9913

–

50

–55

–60

–65

–70

SFDR (dBc)

–75

–80

–85

–90

0 250

50 100 150 200

39.88%

10.21%

SYSTEM CLO CK (MHz )

Figure 10. SFDR vs. System Clock Frequency (PLL Bypassed)

100

–110

–120

–130

–140

–150

PHASE NOISE (dBc/Hz)

–160

–170

100 1k 10k 100k 1M 10M

10 100M

FREQUENCY (MHz)

26.58%

92.3MHz

48.9MHz

23.1MHz

6.1MHz

−50

−60

−70

−80

−90

−100

−110

−120

PHASE NOISE (dBc/Hz)

−130

−140

07002-033

−150 100 100M

1k 10k 100k 1M 10M

FREQUENCY (MHz)

Figure 12. Absolute Phase Noise vs. f

99MHz

49MHz

25MHz

12.5MHz

Using the Internal PLL

OUT

07002-012

(REF_CLK 25 MHz × 10 = 250 MHz Using PLL)

50

–55

–60

–65

–70

SFDR (dBc)

–75

–80

–85

07002-042

–90

00

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40

f

OUT

REFSPUR

(% of System Clock)

BYPASS

PLL ×10

07002-034

.45

Figure 11. Residual Phase Noise vs. f

(PLL Bypassed)

OUT

Figure 13. SFDR Without the Internal PLL

(REF_CLK = 25 MHz × 10 = 250 MHz Using PLL, 4 mA DAC Full-Scale Current)

Rev. A | Page 9 of 32

AD9913

80

−60

−80

VCO 1

−100

VCO 2

−120

PHASE NOISE ( dBc/Hz)

−140

−160

100 100M

1k 10k 100k 1M 10M

FREQUENCY (MHz)

Figure 14. Absolute Phase Noise, VCO1 vs. VCO2

40

35

30

25

20

15

DVDD AVDD (PLL) AVDD (CLK) AVDD (DAC) AVDD (DAC CLK)

70

60

CMOS INPUT LINEAR SWEEP

50

40

30

20

TOTAL P OWER DISSI P ATED (mW)

10

07002-011

0

50 250

DIFF INP UT LINEAR SWE E P

DIFF INPUT SINGLE TONE

CMOS INPUT SINGLE T O NE

70 90 110 130 150 170 190 210 230

SYSTEM CLOCK FREQUENCY (M Hz )

07002-036

Figure 16. Power Dissipation vs. System Clock Frequency

vs. Clock Input Mode

10

POWER DISSIPATION (mW)

5

0

70 90 110 130 150 170 190 210 230

50 250

SYSTEM CLOCK FREQUENCY (M Hz )

Figure 15. Power Supply Current Domains

(CMOS Input Mode, 4 mA DAC Full-Scale Current, Single Tone)

07002-035

Rev. A | Page 10 of 32

ANALOG DEVICES AD9913 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

EQUIVALENT CIRCUITS

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS